WO2001006382A1

WO2001006382A1 - Software fifos in a multimaster bus system

Info

Publication number: WO2001006382A1
Application number: PCT/NO2000/000242
Authority: WO
Inventors: Geir Robert Svelmoe
Original assignee: Telefonaktiebolaget Lm Ericsson
Priority date: 1999-07-20
Filing date: 2000-07-19
Publication date: 2001-01-25
Also published as: DE10084835B3; GB0200399D0; AU6324000A; NO993558D0; NO312926B1; GB2367671B; NO993558L; GB2367671A

Abstract

The present invention relates to communication of data between two parties in a multi master bus system, like PCI bus or VME bus, using shared RAM. The parties may comprise two CPUs, two SW processes executing on the same processor, or a SW process and an interrupt routine. In said RAM there is arranged a FIFO memory locally to each party. Each part may read from its local FIFO memory and write to the other party's FIFO memory only. In this way only write operations are performed on the bus.

Description

IT, LU, MC, NL, PT, SE), OAPI patent (BF, BJ, CF, CG, For two-letter codes and other abbreviations, refer to the "Guid- CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG). once Notes on Codes and Abbreviations " appearing at the beginning of each regular issue of the PCT Gazette Published:

— With international search report

— Before the expiration of the time limit for amending the claims and to be republished in the event of receipt of amendments

1

SOFTWARE FIFOS A MULTIMASTERBUS SYSTEM

TECHNICAL FIELD

This invention is applicable to a multi master bus system (e.g. PCI, VME, etc.) where point to point communication between two masters is to be carried out by using shared RAM to pass data. A special case will be data exchange between two SW processes executing on the same processor, or between a SW process and an interrupt routine.

TECHNICAL BACKGROUND

PROBLEM AREA

When shared memory is used to exchange data between two communicating parties, which executes asynchronous to each other, one must ensure that the two does not update the same memory location (s) at the same time.

In some systems a bus read operation will be slower than a bus write operation (the address decoding for the target will be the same, but for a read operation to complete the data must be fetched by the bus interface, while for a write operation the data can be temporarily buffered in the bus interface circuitry) . Hence a "write-only" system would be more efficient.

KNOWN SOLUTIONS AND PROBLEMS WITH THESE

To gain access to a shared memory resource some processors and bus systems have an atomic "Test-And-Set " instruction which becomes a single read-modify-write operation on the bus. These instructions may not be supported by all processors/bus-systems, and if they are one must have a platform specific part of the SW (usually this will partly be manually coded in assembly language) . If common memory 2

locations to be updated by more than one party could be avoided one would get a more portable high level SW.

For processes executing on the same CPU it would typically be necessary to mask interrupts during the memory update. Usually processes at user level are not allowed to do this and they would have to issue a system call for doing the update. By eliminating the need for having memory locations updated by more than one party, there would be no difference in the SW if the two processes executes on the same processor or on two different processors which have bus access to each others memory.

THE INVENTION

BRIEF SUMMARY OF THE INVENTION

The objects of the present invention are thus to provide an arrangement for point to point communication between two masters or processes over a multi master bus system, which allows communication to be executed asynchronous and concurrently, which is hardware independent, allows faster transfer of data between the masters or processes and eases the load on bus and CPU(s) .

Further objects of the invention are to avoid using common memory locations updated by more than one party, and avoid read operations on the bus .

These objects are met in an arrangement according to the invention comprising FIFO memories for transferring data between the two CPUs/communicating parties, one FIFO assigned to each CPU/party, where each party is allowed to read from its assigned FIFO only, and write to the FIFO assigned to the other party only.

The exact scope of protection for the present invention is as defined in the appended patent claims. 3

DRAWINGS

The invention will now be described in reference to the appended drawings where :

Figure 1 shows two FIFO memories arranged for transferring data between two CPUs/parties, A and B.

Figure 2 shows in principle how one FIFO is arranged to receive data from CPU/party B only, and how the read/write indexes are updated.

Figure 3 shows the full arrangement of FIFOs according to the invention.

Figure 4 shows a simplified overview of a system to which the invention may be applied.

DETAILED DESCRIPTION OF THE INVENTION

The invention proposes a HW independent solution for a shared memory communication mechanism. The two communicating parties may be located on the same processor or at different processors in a multi master bus system.

The communication between the two CPUs/communicating parties is done through a pair of SW FIFOs, one for each direction of data flow. The particular about these FIFOs are the physical location of their components.

To describe this FIFO organisation we will start by drawing two regular SW FIFOs in one common physical memory, Figure 1, and gradually migrate towards the SW FIFO organisation proposed by the invention.

The read index and the write index respectively points to the next location to be read and written. The amount of 4

data in the FIFOs must be calculated upon the values of the read and write indexes together with the FIFO size, which in this case is N. The communicating processes/processors executes asynchronous and concurrently. Using a counter to hold the number of data entries in a FIFO would imply the need for a mutual exclusion mechanism for updating this counter.

When the read index equals the write index, the FIFO is empty. The FIFO can at most contain N-l entries. If the FIFO was to contain N entries, the read index would equal the write index and it would be impossible to distinguish between a full and an empty data area.

Process B, which sends data to process A by inserting them into FIFO (A) , is the only process that may write to the data area of FIFO (A) and to wri teld (A) . Before any data is written, process B must compute the amount of space available in FIFO (A) . Process A reads the wri teldx (A) , computes the number of data in the FIFO, reads the data and updates readldx (A) (which may be updated only by process A) . For data in the other direction the roles are reversed. Since the two processes are asynchronous to each other, It is important that the respective index is updated after the read or write operation is completed.

If the FIFO components are located in such a manner that only write accesses are to be performed on the bus connecting the two processors one would have only the net amount of bus accesses to transfer the data (i.e. one would never access the bus to read an index which is not updated) . By organising the FIFOs in this manner one would write information to the other CPU to the bus and read all incoming information in the local memory (which also will be faster) .

Figure 2 shows the suggested placement of the components for the FIFO used for data from a CPU(B) to another CPU (A) . When B wishes to send data to A it checks in its local memory for the value of the readldx (A) . Since A is not allowed to update the wri teldx (A) in its local memory, B can calculate the space available in FIFO (A) based on the readldx (A) and the remembered value of wri teldx (B) (which B has written into A's memory earlier) . B then writes the data followed by a new wri teldx (A) into A's memory.

The complete picture of the location of two FIFOs' components is shown in Figure 3.

All information (data and indexes) that should be read by the remote system must be written into that systems memory, but of course, a local copy of the indexes must also be maintained.

Since a FIFO pair is only a point to point communication mechanism, there must be one pair for each pair of communicating parties.

ADVANTAGES

Portability: It can be implemented in high level language without any platform specific assembly instruction or OS system calls.

The two communicating parties can be executing on the same processor or on two different processors with the same high level code for taking care of the communication. Bus load: The bus between the two CPUs will be busy for a shorter time since there will be only write transactions and only the net amount of needed data will be put onto the bus. The smaller the bursts of data are the more effective will the "write only" be compared to a read/write system. CPU load: Since data may be buffered at all bus interfaces down the transaction path, the operation will complete in less time and hence leave more time for other processing.

An important advantage of the invention is that it can be implemented in software only, i.e. without making changes in the hardware of the involved systems .

Claims

7P a t e n t c l a i m s

1. Arrangement in a multi master bus system for providing point to point communication between a first party and a second party using shared RAM to pass data, c h a r a c t e r i z e d i n that the arrangement comprises a first and a second FIFO memory arranged in said RAM, the first FIFO memory is arranged locally to said first party and the second FIFO memory is arranged locally to said second party, the first party is allowed to read from a data field of the first FIFO memory only and write to a data field of the second FIFO memory only.

2. Arrangement according to claim 1, c h a r a c t e r i z e d i n that the second party is allowed to read from a data field of the second FIFO memory only and write to a data field of the first FIFO memory only.

3. Arrangement according to claim 1 or 2 , c h a r a c t e r i z e d i n that each FIFO memory includes an write index for its own data field and a read index for the data field of the other FIFO memory, the indexes of the first FIFO memory are updated by the second party only and the indexes of the second FIFO memory is updated by the first party only.

4. Arrangement according to claim 3 , c h a r a c t e r i z e d i n that each FIFO memory includes a local copy of the indexes of the other FIFO memory.

5. Arrangement according to claim 1 or 4 , c h a r a c t e r i z e d i n that the communicating parties are bus-masters. 8

6. Arrangement according to claim 1 or , c h a r a c t e r i z e d i n that the communicating parties are SW processes.

7. Arrangement according to claim 1 or 4 , c h a r a c t e r i z e d i n that the communicating parties comprises one process and one interrupt routine.

8. Arrangement according to any one of the preceding claims, c h a r a c t e r i z e d i n that the bus system is a PCI bus .

9. Arrangement according to any one of the preceding claims, c h a r a c t e r i z e d i n that the bus system is a VME bus .