WO2001001386A1

WO2001001386A1 - Multistandard liquid crystal display with automatic adjustment of timing signals

Info

Publication number: WO2001001386A1
Application number: PCT/US2000/017494
Authority: WO
Inventors: Morgan Tang
Original assignee: Aurora Systems
Priority date: 1999-06-30
Filing date: 2000-06-21
Publication date: 2001-01-04
Also published as: WO2001001386A9; TW514858B

Abstract

A method and structure for allowing a liquid crystal device (LCD) display to be used in a computer running a variety of programs which may provide screen images of a variety of graphic modes, and which center the screen image in the LCD display without operator intervention or adjustment. The video mode of the video signal provided by the video driver is automatically detected without the need for specific instructions from the video driver. The active portion of the display signal is determined and appropriate offsets automatically provided in order to send a video signal to the LCD display having the proper horizontal and vertical frequencies, and a screen image which is centered on the LCD display. The optimum sampling phase is automatically determined by making a number of measurements at the different sampling phases and detecting which sampling phase provides the greatest contrast value, indicating that is the optimum sampling base to be used.

Description

MULTISTANDARD LIQUID CRYSTAL DISPLAY WITH AUTOMATIC ADJUSTMENT OF TIMING SIGNAL S

INTRODUCTION

Technical Field

This invention pertains to display devices, more particularly computer display devices including liquid crystal device (LCD) displays.

Background

Various types of displays or monitors are used in computer systems. These include cathode ray tubes (CRT) displays, as well as the lower power, lighter weight liquid crystal device (LCD) displays.

CRT displays use a raster based approach where a scan line is moved from left to right across the screen in a plurality of rows from top to bottom of the screen. As the electron beam moves in this raster pattern, its intensity is varied in order to create the screen image by varying the intensity of the light at each portion of the screen.

In liquid crystal displays, the raster approach is not used but rather an array of pixels is provided in the LCD screen. Each X Y coordinate on the screen corresponds to a unique pixel whose intensity can be altered as desired, in order to produce the desired screen image, pixel by pixel.

A variety of industry standards for screen image resolutions has evolved. Each of these standards has its own unique set of characteristics, including resolution (number of pixels per line and number of lines per screen), a corresponding horizontal scan frequency, and a corresponding vertical scan frequency. Table 1 below shows these parameters for a variety of popular industry standards.

Table 1

Resolution Horizontal Vertical Graphics Mode (dots x lines) Fre uenc Fre uenc

Modern displays allow for operation with a variety of the most popular industry standards. In CRT devices, automatic gain control (AGC) circuitry is included in order to provide the appropriate horizontal and vertical scan frequencies for different resolutions. Although the AGC circuitry does not center the screen perfectly in all modes, the whole display image is displayed because the CRT has a variable display area (when thought of in pixels), based on the horizontal and vertical scan frequencies. In order to get the screen centered perfectly, the user typically must adjust the screen manually.

With LCD devices, however, a different problem is encountered. Since the LCD display is a fixed resolution device, and it accepts only fixed horizontal and vertical frequencies, the LCD display cannot adapt to different horizontal and vertical scan frequencies for a variety of industry standard graphic modes. Centering is also a problem because the LCD screen is a fixed resolution display. If the horizontal centering is not done correctly, the data on either the left or the right side of the screen will be missing. If the vertical centering is not done correctly, the data on either the top or bottom of the screen will be missing. There is one other problem with driving the LCD display with a conventional analog monitor interface: the input analog data needs to be converted into digital form before driving the LCD display. However, the sampling clock information is not present in the analog monitor interface. The LCD display therefore needs to generate a clock with the correct frequency and phase to sample the analog image data correctly.

Prior art LCD displays provide manual adjustments for the user, which allows the user to press buttons in order to move the screen image left to right, and top to bottom, thereby allowing the user to manually center the image in the LCD screen. Prior art LCD displays perform pixel adjustment by delaying the input data on a clock by clock basis. The user setting can be saved in the EEPROM in the system, but when the display hardware board is changed the setting needs to be readjusted. Such prior art LCD displays only support a preset number of display resolutions.

Naturally, requiring users to manually make adjustments on modern computers is a significant drawback, particularly when computers are becoming much more sophisticated and great strides have been made in so called "user friendliness", including sophisticated techniques for allowing boards to be inserted into the motherboard without user concerns for bus contention, interrupt request, and other complexities.

One proposal made with respect to the VESA standard is to require eight additional bits to be added before, and eight additional bits to be added after, each horizontal sync pulse in order to define how this screen image is to be centered. This, however, will require a change in all graphics cards, software drivers, etc. currently in existence or to be manufactured, a considerable expense and inconvenience.

Summary

In accordance with the teachings of this invention a novel method and structure is taught for allowing a liquid crystal device (LCD) display to be used in a computer running a variety of programs which may provide screen images of a variety of graphic modes, and which center the screen image in the LCD display without operator intervention or adjustment. In accordance with the teachings of this invention, the video mode of the video signal provided by the video driver is automatically detected without the need for specific instructions from the video driver. The active portion of the display signal is determined and appropriate offsets automatically provided in order to send a video signal to the LCD display having the proper horizontal and vertical frequencies, and a screen image which is centered on the LCD display. The optimum sampling phase is automatically determined by making a number of measurements at different sampling phases and detecting which sampling phase provides the greatest contrast value, indicating that is the optimum sampling phase to be used.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a timing diagram showing the relationship between horizontal sync signals and RGB data signals;

Fig. 2 is a timing diagram showing the relationship between vertical sync signals and horizontaLsync signals;

Fig. 3 is a timing diagram depicting the relationship between horizontal sync signals, RGB data signals, and the extracted clock signal in accordance with this invention;

Fig 4. is a block diagram depicting one embodiment of a line locked PLL used in conjunction with the present invention;

Fig. 5 is a block diagram depicting a computer system of the present invention;

Fig. 6 is a block diagram depicting one embodiment of a screen control circuity 400 of the present invention;

Fig. 7 is a timing diagram depicting the position of the active RGB data signal with respect to horizontal sync pulse; Fig. 8 is a timing diagram depicting the determination of the active RGB data signal with respect to vertical sync signals;

Fig. 9 is a flowchart depicting the operation of one aspect of the present invention;

Fig. 10 is a flowchart depicting the operation of another aspect of the present invention;

Fig. 11 is a timing diagram depicting possible sampling points of a video signal;

Fig. 12 is a diagram depicting the relationship between image quality and sampling phase in accordance with one embodiment of the present invention; and

Fig. 13 is a diagram depicting the relationship between image quality and sampling phase in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

Fig. 1 is a timing diagram showing the relationship between horizontal sync pulses and RGB image data. Horizontal sync pulses indicate when a new line of the screen image is to start, and RGB data provides intensity information for each pixel within one line of the screen image. The horizontal sync appears on a different line as the RGB data. It defines when the CRT electron beam starts the horizontal sweep. As shown in Figure 1, the number of pixels (x) from the active edge of the horizontal signal to the valid data is fixed for a particular graphics mode, but the value of x is different for different graphics mode.

Fig. 2 is a timing diagram showing the relationship between horizontal sync pulses and vertical sync pulses. Vertical sync pulses define when a new screen image is to begin, and thus, following each vertical sync pulse there follows a plurality of horizontal sync pulses, one for each line in the screen image. Associated with each horizontal sync pulse is a corresponding RGB data stream, as discussed above with reference to Fig. 1.

In accordance with the teachings of this invention, a first step is to extract a clock from the signals driving the display. In this embodiment a fixed clock, or a set of fixed clocks useful for a variety of the most popular industry standards, is not used, because the horizontal clock providing the image signal may be off frequency, thus leading to an error in clock frequencies between that generating the image data and that being used to drive the LCD display. Thus, in accordance with one embodiment of this invention, a line locked phase lock loop (PLL) is used to extract a clock from the image signal.

Fig. 3 is a timing diagram depicting in more detail a horizontal sync signal, RGB data in the form of a plurality of pulses running at a predetermined clock frequency, and the extracted clock pulse derived from the line locked PLL driven by the horizontal sync signal and locked to the frequency of the analog RGB data.

As shown in Fig. 4, PLL 404 uses the horizontal sync signal as an input reference and divides the output signal F_cl0Ck by a certain value determined by the graphics mode. This is how PLL 404 provides F_clock at the RGB data rate.

Fig. 5 is a block diagram depicting a computer system constructed in accordance with the teachings of this invention. As shown in Fig. 5, computer system 40 includes computer 41 which provides, on its output bus, video signals of any convenient format. In prior art systems, computer 41 would directly drive a video display. Alternatively, in prior art systems, computer 41 would be required to output a standard video format for directly driving a LCD display. However, in accordance with the teachings of the present invention, a novel screen control circuitry 400 receives the video signals from computer 41 and in turn provides appropriate signals to control LCD display 42. Used in conjunction with screen control circuitry 400 is storage device 43 for storing one or more lines, or frames, of video display data as eight bit R, G, and B bytes per pixel, after manipulation by screen control circuitry 400 and prior to that video data stored in storage in 43 being sent to LCD display 42 under the control of screen control circuitry 400. Screen control circuity 400 controls the output of digital RGB data from storage device 43 to LCD display 42, and provides horizontal and vertical sync signals H,^- and V^. to control LDC display 42.

In one embodiment, storage device 43 is contained on the same circuit as screen control circuity 400. In one embodiment, storage device 43 allows for storage of two lines of pixel information, one being written to by screen control circuity 400 while the other, previously stored, is being read out from storage device 43 to provide a line of pixel data to LCD display 42, in a ping pong fashion.

In an alternative embodiment, storage device 43 contains sufficient memory to allow two entire video frames to be stored, again in a ping pong fashion, one frame being written into storage device 43 by screen control circuity 400 while the other, previously stored video frame, is being read out from storage device 43 to provide video information to LCD display 42. In this embodiment, where two frames are stored within storage device 43 in a ping pong fashion, different vertical frequencies are capable of being achieved between that vertical frequency sent by computer 41 and that vertical frequency required by LCD display 42.

Fig. 6 is a block diagram depicting one embodiment of a structure suitable for use as screen control circuity 400 of Fig. 5. In one embodiment of this invention, the overhead operations described below with respect to determining the video mode and performing the screen image centering operation is performed upon boot-up and when there is a video mode change, for example, when there is a change in Y_VΏC and/or H,^. Screen control circuity 400 receives horizontal sync signal H^ on line 401, vertical sync signal V^_^ on line 402, and analog image information, in RGB format (typically) on three line bus 403, on which are provided horizontal sync, vertical sync, and analog RBG signals, respectively. As shown in Fig. 6, the horizontal sync signal received on 401 is applied to

line locked PLL 404 and a clock CLK is extracted from the horizontal sync signal. This clock signal will have a frequency:

number of pixels in Horizontal direction clock H period (in seconds)

Horizontal sync signal H^_^ received on lead 401 is also applied to horizontal period counter 405. Horizontal period counter 405 determines the time period between successive horizontal sync signals, thus determining the horizontal frequency associated with the screen image mode. (Refer to Table 1). Similarly, the vertical sync signal V,^ received on lead 402 is applied to vertical period counter 406 which determines the period between successive W_tyoe signals, thus establishing the vertical frequency for the screen image. (Refer to Table 1). Referring to the flowchart of Figure 9, the node information is derived in steps 91 and 92 as a result of the output signals from horizontal period counter 405 and vertical period counter 406 being applied to incoming display mode detection circuitry for 407 which establishes certain parameters based upon the detected graphics mode. Thus, by way of example, when horizontal period counter 405 detects a period equivalent to a horizontal sync signal frequency of 37.9 kHz and vertical period counter 406 detects a period equivalent to a vertical sync signal frequency of 60 Hz, incoming display mode detection circuity 407 determines that the graphics mode of the image being sent to the LCD display is SVGA and thus, the display image is 800 x 600 pixels. In one embodiment, incoming display mode detection circuitry 407 provides as output data horizontal count information, associated with the horizontal frequency for storage into a horizontal count register, and vertical count information, associated with the vertical frequency, for storage in a vertical count register.

In one embodiment, incoming display mode detection circuity 407 is conveniently implemented as a table look up. In alternative embodiments, circuity 407 is implemented in software, or hardware, or a combination of both, as will be readily appreciated by those of ordinary skill in the art in light of the teachings of this invention.

The analog RGB signals are applied on bus 403 to analog to digital converters

408-R, 408-G, and 408-B. The digital outputs (eight bits each, in one embodiment) of these~analog o digitaLconverters-are-stored in storage unit 43 (Fig. 5) for later application to LCD display 42 (Fig. 5). The digital outputs of analog to digital converters 408-R, 408- G, and 408-B are also applied to horizontal and vertical active/inactive detection circuity 409, which determines the position of the active RGB data signal with respect to the horizontal sync signals, as shown in step 93 of Fig. 9. This is done by counting the number of extracted clock CLK cycles from the start of the horizontal sync pulse to the beginning of the active data portion of the RGB signal to derive

and the number of clock cycles from the start of the horizontal pulse signal to the end of the active portion of the RGB data signal to derive H_count2, as shown in Fig. 7. This results in a first count H_^u indicating the number of clock cycles to the beginning of the active RGB data portion, and a second count H_count2 indicating the number of clock cycles to the end of the active portion of the RGB data signal. This now defines precisely the active data portion of a horizontal line, as reflected in output signals from Horizontal and Vertical Active/Inactive Detection Circuity 409, and thus the position of the data to be stored in storage unit 43 (Fig. 5).

The difference between these two horizontal counts is equal to the number of horizontal active data pixels. In the example given above, for SVGA mode, this number should equal 800. If the difference between these two counts does not equal 800, this means that the extracted clock CLK is not accurately matched to the clock used to generate the video signal being received. In this event, line locked PLL 404 is adjusted as necessary so that the difference between the first and the second count is equal to the expected horizontal resolution for the detected graphics mode. The internal counter of the line locked PLL is incremented/decremented to adjust the sample clock frequency in such a way that the count is set to 800, for this example.

In a similar fashion, horizontal and vertical active/inactive detection circuity 409 detects the active and inactive vertical positions by counting the number of H,^ pluses from the start of the vertical sync pulse to the beginning of the active data portion of the RGB signal to derive V,^,,, and the number of lines (H,^ pulses) to the end of the active portion of the RGB data signal to derive V_^,^, as depicted in Fig. 8. This results in a first count V.^, indicating the number of scan lines to the beginning of the active RGB data portion, and a second count V_couat2 indicating the number of scan lines to the end of the active portion of the RGB data signal. This now defines precisely the active data portion in the vertical direction of the screen as reflected in output signals from Horizontal and Vertical Active/Inactive Detection Circuity 409.

Horizontal and Vertical Active/Inactive Detection Circuity 409 stores the horizontal active position H_countl, horizontal inactive position H_^^, vertical active position V,^,, and vertical inactive position V,,^ data in registers for the firmware to process.

The difference between these two vertical counts is equal to the number of vertical active lines. In the example given above, for SVGA mode, this number should equal 600. If the difference between these two counts does not equal 600, the current graphics mode is a standard graphics mode. A non-standard mode of operation refers to mode that deviates from the standard mode table, for example that of Table 1. For example, the standard 1024x768 60Hz XGA mode has a pixel (horizontal) rate of 65Mhz. In a non-standard mode, the frequency may be at, for example, 65.5Mhz. In the 65.5 Mhz example, the number of pixels per active display width will not be equal to 1024 using the standard XGA mode setting. In one embodiment, in this case the firmware adjusts the period of line locked PLL 404 such that the number of pixels per active display width is equal to 1024. If adjusting line locked PLL 404 within a predefined margin does not yield the correct number of pixels per display width (in this case 1024), the firmware defaults the setting back to the standard XGA setting, otherwise, the new PLL clock period is used.

By continuously monitoring incoming RGB data received from analog to digital converters 408-R, 408-G, and 408-B, horizontal and vertical active/inactive detection circuity 409 is able to, for a plurality of horizontal lines, determine the smallest counter value after the start of the horizontal sync pulse to RGB data in order to determine the start of the RGB active data portion-of the signal, and the largest counter value of valid RGB data in order to determine the end of the active data portion of the RGB signal. By monitoring a plurality of horizontal lines (for example all lines in one frame) in this manner, you are assured (or at least very likely) to have a line were there is valid data in its left-most pixel, and a valid line were there is valid data in its right-most pixel, thereby making a valid determination of the full width of the active RGB data portion. In a similar manner, by monitoring a plurality of one or more screen images, you are assured (or at least very likely) to receive a first line in an image having at least one active pixel and a last line in an image having at least one active pixel, thereby determining the full extent of the vertical active portion.

As shown in steps 96 and 97 of Fig. 9, with the active and inactive portions of the horizontal and vertical extent of the screen image now determined, the screen image can be automatically centered. This is accomplished by sending the valid screen image to the display controller, with appropriate leading blank rows per frame and appropriate leading blank pixels per row. Given the fact that, as discussed above, line locked PLL 404 is being used to extract a clock from a horizontal sync signal having a frequency equal to the clock used by the graphics card (not shown) to send the screen image information, clock signal CLK can be of the same frequency but out of phase with that clock used by the graphics card. If this out of phase condition exists, the RGB data will not be sampled properly by analog to digital converters 408-R, 408-G, and 408-B, resulting in improper screen imagery.

Accordingly, as one feature of this invention, line locked PLL 404 is provided with the ability to phase adjust its output clock signal CLK. In one embodiment, the method used to automatically adjust the phase of line locked PLL clock signal CLK is shown in the flow chart of Fig. 10. A first step is to select a line in a display image having the highest changes of intensity, as depicted in step 101 of the flowchart of Fig. 10. This is done in order to avoid using blank lines or solid white lines, for example, during this process, as that would yield very poor results. In-on&embodiment, in order to determine which line has the highest change in intensity, a comparison between adjacent pixels is made and a sum tabulated. Thus, for each line in a frame, the following value is calculated: n

^Intensi ty = ∑ |i^> _i - P_i I²

where n = number of pixels in a line,

Pi = pixel intensity

This is a significant improvement over the prior art which provides on the LCD display a button to manually manipulated by a user to adjust the phase of the sampling clock CLK to a point where the user thinks the picture "looks good".

This determination of which line has the highest change in intensity is performed simultaneously on a plurality of, or each line of a frame, or alternatively, is performed sequentially one line per frame until the entire frame (or a desired portion thereof) has had its line intensity variations detected. If desired, the video driver being run by computer 41 (Fig. 5) can provide a specific image to the screen for this purpose, although it has been found that this usually not necessary because when a computer boots up, an image is sent to the screen which remains static for a significant period of time to allow this operation to take place. Furthermore, preferably the screen image during this time is not seen because LCD display 42 (Fig. 5) is not sent signals from screen control circuity 400 to allow LCD display 42 to become active during this time, although computer 41 is providing video signals to screen control circuity 400. In this embodiment, only after this activity by screen control circuity 400 does screen control circuity 400 provide active video signals to LCD display 42.

Fig. 11 depicts a greatly enlarged portion of the RGB signal, showing the analog signal corresponding to several sequential pixels. Since this is an analog signal, the point at which the-sample is taken Js of Jπψortance. For example, possible sample points S, and S₂ would yield incorrect data, while sample point S₃ would yield correct data, and thereby provide the greatest screen image contrast. Once a line has been selected having greatest intensity variations, that line is sampled a plurality of times, each with a different phase for sampling the analog RGB data by analog to digital converters 408-R, 408-G, and 408-B. The Δlntensity values for the line is stored for each variation in sampling phase, with a resulting curve shown in Fig. 12. The greatest Δlntensity value is used to select the best phase for sampling, and it is this phase to which line locked PLL 404 is adjusted in order to provide clock signal CLK to have this best phase for sampling.

In an alternative embodiment, sampling phase detection is performed by comparing the intensity of sampled pixels in different frames. By using storage device 43 in Fig. 5 or internal storage within screen control circuity 400 of Fig. 5, the previous frame pixel intensity is stored and is compared to the current frame pixel intensity. If the sampling phase is correct, the intensity difference (Δlntensity) is minimal. Similar to the previous phase detection method, once a line has been selected having greatest intensity variations, that line is sampled a plurality of times, each with a different phase for sampling RGB data. For each sampling phase, the sum of the difference of the pixel intensity between frame for the selected lines calculated:

Δlntensity = ∑ ΪP - P_±

where n = number of pixels in a line,

Pj' = pixel intensity of previous frame, P_; = pixel intensity of current frame Δlntensity values are stored for each variation in sampling phase, with resulting curve shown in Fig. 13. The smallest Δlntensity value provides the best sampling phase.

In one embodiment of this invention, the phase of line locked PLL 404 is changed in increments of 1/10, providing a selection of ten phases for sampling, the best of which is selected, as shown in steps 102, 103, and 104 of Fig. 10. With ten phases being considered, ten frames are required in order to sequentially make the phase/Δlntensity measurements, which for a 60 Hz mode requires only l/6th of a second. During boot-up, it is highly likely that during the short period of time, the same image information will be sent to the screen (although the screen is preferably blanked by screen control circuity 400, as previously described) and thus an accurate determination can be made (step 105 of Fig. 10) and the associated phase angle selected for sampling (step 106 of Fig. 10).

In an alternative embodiment, a plurality of phase delay clocks are used for the simultaneous sampling of the analog RGB signal, allowing the best phase for sampling to be determined even more quickly. However, this requires greater hardware and is not generally required.

All publications and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the appended claims.

Claims

WHAT TS CLAIMED TS

1. A method for generating an image on an LCD display comprising the steps of: receiving a video signal; analyzing said video signal to detect the video mode of said video signal, comprising the steps of: extracting a clock signal from the video data portion of said video signal; determining the time period between successive horizontal sync signals, thereby determining the horizontal frequency associated with said video mode; and determining the time period between successive vertical sync signals, thereby determining the vertical frequency associated with said video mode; storing pixel information from said video signal, said pixel information being sampled from said video-signal based oirsaid extracted clock signal^~and^~said determined horizontal frequency and vertical frequency of said video mode; and providing a modified video signal to said LCD display, having a second video mode suitable for driving said LCD display, from said stored pixel information.

2. A method as in claim 1 wherein said step of extracting said clock signal comprises the step of operating a line locked phase lock loop which receives as one input signal said horizontal sync signal, and as a second input signal a divided extracted clock signal.

3. A method as in claim 1 wherein said step of storing comprises: storing in a memory device capable of storing two lines of video information, one line of video information and reading a previously stored line of video information to provide said modified video signal, in a ping-pong fashion.

4. A method as in claim 1 wherein said step of storing comprises: storing in a memory device capable of storing two frames of video information, one frame of video information while reading a previously stored frame of video information to provide said modified video signal, in a ping-pong fashion.

5. A method as in claim 2 wherein said division factor is based upon said video mode.

6. A method as in claim 1 which further comprises the step of analyzing said video signal to determine the extent of said active portion of said video signal, and providing said modified video signal as a centered image on said LCD display.

7. A method as in claim 6 wherein said step of analyzing said video signal to

sai Lactive-portion ofsaid-video signal comprises the steps of: counting the number of said extracted clock cycles from the start of a horizontal sync pulse to the beginning of the active portion of the RGB portion of said video signal; counting the number of said extracted clock cycles from the start of said horizontal sync pulse to the end of the active portion of the RGB portion of said video signal; and storing said pixel information with leading and trailing blank pixels in each row of said video image, so that said row is centered on said LCD display.

8. A method as in claim 6 wherein said step of analyzing said video signal to determine the extent of said active portion of said video signal comprises the steps of: counting the number of said horizontal sync pulses from a vertical sync pulse to the beginning of the active portion of the RGB portion of said video signal; counting the number of horizontal sync pulses from said vertical sync pulse from the start of said horizontal sync pulse to the end of the active portion of the RGB portion of said video signal; and storing said pixel information with top and bottom blank rows of pixels in each frame of said video image, so that said frame is centered on said LCD display.

9. A method as in claim 1 wherein said step of storing pixel information comprises the steps of: determining a desired phase of said extracted clock signal for sampling said video signal; and sampling said video signal based upon said selected phase of said extracted clock signal.

10. A method as in claim 9 wherein said step of determining a desired phase of said extracted clock signal comprises the steps of: selecting a line of said video-signal; sampling said selected line using a plurality of different phases of said extracted clock signal; and determining which of said plurality of different phases of said extracted clock signal provides the greatest change in intensity between adjacent pixels in said selected line.

11. A method as in claim 10 wherein said selected line is chosen from a plurality of lines of said video signal based upon which of said plurality of lines has the greatest change in intensity between adjacent pixels when sampled using a selected phase of said extracted clock signal.

12. A method as in claim 10 wherein said sampling using different phases of said extracted clock signal is performed sequentially for said different phases.

13. A method as in claim 10 wherein said sampling using different phases of said extracted clock signal is performed simultaneously.

14. A method as in claim 9 wherein said step of determining a desired phase of said extracted clock signal comprises the steps of: selecting a line of said video signal; for each of a plurality of frames, sampling said selected line using one of a plurality of different phase of said extracted clock signal; and determining which of said plurality of different phases of said extracted clock signal provides the smallest change in intensity between adjacent pixels in said selected line.

15. A method as in claim 14 wherein said selected line is chosen from a plurality of lines of said video signal based upon which of said plurality of lines has the greatest change in intensity between adjacent pixels when sampled using a selected phase of said extracted clock signal.