WO2000070733A1

WO2000070733A1 - Method and system for controlling ac current supplied to an inductive load from an ac powerline

Info

Publication number: WO2000070733A1
Application number: PCT/US2000/011299
Authority: WO
Inventors: John F. Farrow
Original assignee: Medar, Inc.
Priority date: 1999-05-12
Filing date: 2000-04-26
Publication date: 2000-11-23

Abstract

A method and system are disclosed for controlling AC current supplied to an inductive load (LOAD) from an AC powerline (50/60 HZ POWER INPUT) using an SPDT switch (SPDT SWITCH) or its electronic equivalent. The switch alternately either connects the inductive load (LOAD) to the AC powerline (50/60 HZ POWER INPUT) or short-circuits its terminals. Rapid switching between those two states is used to control the current to inductive load (LOAD). Using the method and system, correction of lagging power factor, control of current waveshape, control of load current waveshape and a very precise control of current in the load are all possible.

Description

METHOD AND SYSTEM FOR CONTROLLING AC CURRENT SUPPLIED TO AN INDUCTIVE LOAD FROM AN AC POWERLINE

TECHNICAL FIELD

This invention relates to methods and systems for controlling AC current supplied to an inductive load from an AC powerline and, in particular, to methods and systems for controlling current supplied to circuitry operated off of a powerline having a predetermined frequency, such as 50 to 60 HZ.

BACKGROUND ART

In the prior art, a pair of SCRs connected in inverse parallel are connected between the powerline and the load to be controlled. Such a circuit is illustrated in Figure 1. Normally, the SCRs are OFF to block power from the load.

When it is desired to apply power to the load, the SCRs are triggered on at a particular time interval after the beginning of each half-cycle of the powerline AC voltage. This time interval is illustrated in Figure 2. Once triggered, the latching nature of the SCRs causes them to conduct for the remaining duration of the powerline half-cycle, until the current through the SCRs returns to zero. The amount of power (or current) supplied to the load is regulated by the time interval Tl, shown in Figure 2. At larger values of Tl , most of incoming powerline voltage is blocked from the load and the resulting current delivered to the load is relatively low. At smaller values of Tl, most of the powerline voltage is applied to the load and the resulting current is relatively high. A more complete explanation of the structure and methods associated with this area of the prior art are disclosed in U.S. Patents Nos.

4,851,635; 3,832,518; 4,239,948; and 4,289,951.

Although the prior art methods are very efficient power-wise, they can result in very poor apparent power factor reflected back into the powerlines. The switching action of the SCRs and the inductive nature of the load result in a current waveform which is very different in waveshape from and out-of-phase with the powerline voltage. A typical current waveform for a high value of Tl (lower current) is illustrated together with the powerline voltage in Figure 3. This results in inefficiencies in the power system.

Also, the latching nature of the SCRs makes it difficult to control the current to a high degree of accuracy. In a typical industrial plant, the voltage of the powerline is constantly changing up and down as various devices in the plant turn ON and OFF. Changes of 20% in powerline voltage from one half-cycle to the next are not uncommon. These changes in powerline voltage are not predictable in any deterministic way. The result is that when an SCR is triggered ON during a powerline half-cycle, particularly early in the half-cycle (small value of Tl in Figure 2), there is no way to know exactly what the powerline voltage will be and exactly what current will result.

Changes in the load impedance cause a similar problem, particularly at the very beginning of the interval when power is applied to the load and the impedance of the load is not yet known. Once the SCR is triggered ON, the current in the load will be a function of the powerline voltage and the load impedance. If the current is not at the desired value, nothing can be done until the end of the powerline half-cycle when the SCR shuts OFF.

Another approach to the problem of controlling AC current in an inductive load is disclosed in U.S. Patent No. 5,519,311, however this patent lacks many of the features of this invention.

DISCLOSURE OF INVENTION

An object of the present invention is to provide a method and system for controlling AC current supplied to an inductive load from an AC powerline wherein the method and system precisely control load current.

Another object of the present invention is to provide a method and system for controlling AC current supplied to an inductive load from an AC powerline wherein apparent power factor is improved thereby resulting in efficiencies in the power system.

In carrying out the above objects and other objects of the present invention a method is provided for controlling AC current supplied to an inductive load having first and second terminals from an AC powerline having a third terminal and current and voltage waveforms having a common frequency. The method includes the steps of: (a) electrically connecting the first terminal to the third terminal but not to the second terminal so that at no time is the first terminal electrically connected to both the second and third terminals wherein the inductive load is electrically connected to the powerline. The method also includes the step of:

(b) electrically disconnecting the first terminal from the third terminal and electrically connecting the first terminal to the second terminal so that at no time is the first terminal disconnected from both the second and third terminals wherein the first and second terminals of the load are short-circuited. The method further includes a step

(c) of alternatively performing steps (a) and (b) to control the AC current supplied to the inductive load from the AC powerline.

In one embodiment of the invention, the powerline has a half-cycle and wherein step (c) is performed so that the amount of time that the first terminal is connected to the third terminal is greater than the amount of time that the first terminal is connected to the second terminal during a beginning part of the half-cycle than during a latter part of the half-cycle to reduce any phase difference between the current and voltage waveforms of the powerline. In this embodiment, the current and voltage waveforms may be substantially in phase. In another embodiment of the invention, step (c) is performed so that the AC current supplied to the inductive load has a non-sinusoidal current waveform. In this embodiment, the non-sinusoidal current waveform may be a substantially square current waveform.

In yet another embodiment of the present invention, step (c) may be performed so that the current supplied to the inductive load has a substantially sinusoidal current waveform.

Yet, in still another embodiment of the present invention, step (c) may be performed so that the AC current supplied to the inductive load has a desired frequency less than the common frequency. In this embodiment, the desired frequency may be a sub-multiple of the common frequency.

Preferably, the frequency at which step (c) is performed is greater than the common frequency of the powerline.

Yet, still further in carrying out the above objects and other objects of the present invention, a system is provided for controlling the AC current supplied to the inductive load from an AC powerline in accordance with the above method steps.

The above objects and other objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 is a schematic view of a pair of SCRs to control the current through an inductive load; Figure 2 is a graph illustrating voltage and current waveforms and switching time relationships of the operation of the circuit shown in Figure 1 ;

Figure 3 is a graph illustrating the voltage and current waveforms which result from operating the circuit of Figure 1 under certain specific conditions;

Figure 4 is a schematic view of a circuit which performs the methods of this invention;

Figures 5a and 5b are graphs of the voltage and current waveforms, respectively, which result from using the methods of this invention with the circuitry of Figure 4;

Figure 6 is a graph illustrating the voltage and current waveforms which occur in a circuit with a power factor of 70.7% ;

Figures 7a and 7b illustrate the voltage and current waveforms, respectively, with the circuitry in Figure 4 to reduce or remove the phase difference between the voltage and current waveforms illustrated in Figure 6;

Figure 8 is a schematic view of an electronic switching circuit which provides the same functions as the circuit of Figure 4;

Figures 9a and 9b show the waveforms of voltage and current, respectively, associated with the operation of the circuit of Figure 8 during a positive half-cycle of the powerline voltage;

Figure 10 is a schematic view of circuitry to use the methods of this invention in a three-phase system; and .

Figure 11 is a graph illustrating voltage and current waveforms resulting from the operation of the circuitry in Figure 10 in accordance with the methods of this invention. BEST MODE FOR CARRYING OUT THE INVENTION

The basic idea of this invention is illustrated in Figure 4. A SPDT (Single Pole Double Throw) switch is used to either connect the inductive load to the incoming powerline or short-circuit the terminals of the load. The SPDT switch is designed to switch at frequencies above the frequency of the incoming powerline. For a 60 HZ powerline, typical switching speeds would be 0.5-10 kilohertz. Also, the SPDT switch is designed so that there is no "dead time" between its two positions. A connection always exists either between terminals 1 and 2 or between terminals 1 and 3. There is never a time when terminal 1 is disconnected and there is never a time when terminals 1, 2, and 3 are all connected together.

In the quiescent or OFF state, the SPDT switch is in the position to connect terminal 1 to terminal 2; the load is disconnected from the powerline and its terminals are shorted together.

When it is desired to apply power to the load, the switch is moved by a controller so that terminals 1 and 3 are connected. In this position, the incoming powerline voltage is applied to the load. The switch is left in the position to connect terminals 1 and 3 until the current, i, to the load reaches the desired value. When the current reaches a desired value, the switch is moved to the position to connect terminals 1 and 2, which short-circuits the load. Due to the inductive nature of the load, the current, i, will continue to flow in the same direction. Due to resistance in the circuit the current will decay at a rate determined by the inductance and resistance. When the current decreases to a certain value, the switch is moved to connect terminals 1 and 3 to cause the current to increase back to the desired value.

An example of the resulting voltage and current waveforms applied to the load is illustrated in Figure 5.

Any of a number of voltage and current sensors, as shown in Figure 4, can be used to measure the voltage and current in the load and the incoming powerline. Since these sensors are very well known in the prior art and the techniques of voltage and current measurement are not an object of this invention, this disclosure has been simplified by the omission of any discussion of sensors or measurement techniques.

As it can be seen in Figures 5a and b, the resulting waveform of the current in the load has a distinctly sawtooth-like shape. Operating the switch at a faster rate and making the current levels which determine switch actuation closer together will result in a "smoother" waveform. Using an electronic switch as illustrated in Figure 8 and a switching frequency of several kilohertz, the current waveform can be made quite smooth.

The advantage of using a switch to control the current through the load, rather than a latching device such as an SCR is that much more precise control of the load current is possible. The switch is manipulated as needed to achieve the desired current and with the speed of an electronic switch, corrections to the current can be made in less than a millisecond. Also the waveform of the current can be made nearly continuous, which has benefits in many applications.

Normally, an inductive load connected to the powerline will cause the load current to lag the applied voltage, resulting in a lower power factor reflected back to the powerline. The lag between voltage and current for an inductive power factor of 0.707 (70.7%) is illustrated in Figure 6. However, the switch may be manipulated in such a way as to partially or completely reduce this effect. This is accomplished by placing the switch into the position to connect terminals 1 and 3 for a greater proportion of time during the early part of a powerline half-cycle than during the latter part, as illustrated in Figures 7a and b. This has the effect of increasing the current early in the half-cycle and reducing it later in the half-cycle, thus bringing it back to being more in-phase with the powerline voltage waveform. If the combination of powerline voltage, desired current, and load impedance permit, it is possible to make the voltage and current waveforms very close to being in-phase which results in an improved power factor and more efficient operation of the power system. The switch can also be manipulated to generate non-sinusoidal current waveforms in the load. For example, an approximation to a square wave can be generated which is useful in some applications. With a single-phase powerline, the only limitation on the waveforms so generated is that their fundamental frequency must be the same as the powerline frequency or some integer multiple or sub-multiple of the powerline frequency.

In order to achieve fast switching speeds, electronic circuitry is used to implement the SPDT switch shown in Figure 4. Figure 8 shows one of a number of different circuits which could be used.

In Figure 8, transistors Ql and Q2, together with diodes Dl and D2 are used to implement the connection between terminals 1 and 3 of the SPDT switch shown in Figure 4. SCR1 and SCR2 are used to implement the connection between terminals 1 and 2 of the SPDT switch shown in Figure 1.

Capacitor Cl, shown as optional, may be needed to suppress voltage spikes and other switching noise due to the switching action of transistors Ql and Q2. If the inductance value of the load is known and stable, capacitor Cl can be sized to correct the power factor of the load to 100% .

The load, shown as an inductor and resistor in series can be any sort of transformer, motor, lighting ballast or other device which exhibits an inductive (lagging) power factor.

For simplicity, the driving circuitry for the transistors, the triggering circuitry for the SCRs, the sensors and any snubber circuitry is not shown in Figure

8. These circuits are well-known in the prior art, they are not the object of this invention and an understanding of their operation is not necessary to understand the inventive aspects of this invention.

In operation, diode Dl, transistor Ql and SCR SCR1 are used to conduct current during the powerline positive half-cycles, when terminal LI is positive in relation to L2. Diode D2, transistor Q2, and SCR SCR2 are used to conduct current during the powerline negative half-cycles, when terminal LI is negative in relation to L2.

The operation of the circuit of Figure 8 can be understood by looking at the diagram in Figures 9a and b. The voltage applied to the load, labeled V, is shown. The desired current is indicated by the dotted line and the current actually applied to the load is the jagged-appearing line. Both of these lines are collectively labeled I. In Figures 9a and b, the circuit is being operated to make the current waveform approximately sinusoidal and in-phase with the applied powerline voltage, in an effort to make the power factor of the resulting load on the powerline as close to 100% as possible.

In Figure 9a, transistor Ql is turned ON at the beginning of the half-cycle, indicated by Point 1 to bring the current up to the desired value indicated by the dotted line which approximates a sine wave. Once the desired current is reached, transistor Ql is shut off and at the same time SCRl is turned ON to provide a short-circuit across the load. This causes the voltage across the load to go to zero at Point 2 in Figure 9a. When the current in the load decays to a value slightly below the desired one, transistor Ql is turned again to apply voltage to the load and bring the current up to slightly above the desired value. When current rises slightly above the desired value, Ql is turned OFF and SCRl is turned ON. Transistor Ql and SCRl are switched as necessary to either apply voltage to the load or short-circuit it in order to make the current rise and fall to follow the general shape of a sinusoidal waveform.

Near the end of a positive voltage half-cycle where current is applied to the load, indicated by Point 3 in Figure 9a, Ql is always turned ON to reverse-bias SCRl and make sure it is OFF before the following negative half-cycle. This is necessary because if SCRl were to remain ON during the following negative voltage half-cycle, it would cause a short-circuit across the load when transistor Q2 was turned ON during the negative half-cycle. For a negative voltage half-cycle, exactly the same process described above is used except that transistor Q2 and SCR SCR2 are used to switch the current.

In addition to the approximation to the sine wave shown in Figure 9b, the current through the load can be manipulated to any of a number different waveforms. It is within the scope of this invention to provide a variety of waveforms of current to the load.

Although this invention is designed for use on a single-phase powerline, it can also be used in certain three-phase applications where special waveforms are required. These applications fall into a category where it is desired to generate an AC waveform of a frequency which is some sub-multiple of the powerline frequency. These are called frequency converter circuits. Such circuits are commonly used where it is desired to provide very large currents (100,000 amps or more) to loads which are mostly inductive. By generating a frequency lower that the powerline frequency, less voltage is needed, a transformer with a higher primary-to-secondary ratio can be used and power demand is reduced.

The circuitry used to perform the frequency converter function according to the methods of this invention is shown in Figure 10, again without the required controller or sensor(s). The transformer which feeds power to the load has three primary windings wound on a common core, one for each phase. The circuitry connecting the transformer primaries to the incoming powerline on each phase is similar to the single-phase case except that three pairs of SCRs, one across each winding are not required. Due to the cross-coupling of the primary windings all on the same core, only one pair of SCRs across one of the windings (it doesn't matter which one) is required.

To generate current in the load, transistors Ql through Q6 in Figure

10 are turned on at specific times in synchronism with the three phases of the incoming powerline. To illustrate this, the graph of signals in Figure 11 is used. In Figure 11 , the transistors are switched in the pattern necessary to generate a signal cycle of an output frequency of 15 HZ with an incoming three-phase powerline frequency of 60 HZ. Although a particular output frequency has been selected for this example, many other frequencies are possible.

The example illustrated in Figure 11 starts with a positive-going voltage at the output of the transformer in Figure 10. In order to accomplish this, transistor Ql in Figure 10 is turned ON near the beginning of the positive half-cycle of phase A, identified as point 1 in Figure 11. During the positive half-cycle of Phase A, Transistor Ql and SCRl in Figure 10 are turned ON and OFF as necessary to achieve the desired current into the load.

At a point about 30 degrees before the end of the phase A positive half-cycle, identified as point 2 in Figure 11, transistor Ql in Figure 10 is turned OFF and transistor Q3 in Figure 10 is used instead to control the current applied to the load from the positive half-cycle of phase B. Just as Ql was turned ON and OFF as necessary to control current during the Phase A positive half-cycle, transistor Q3 is turned ON and OFF, together with SCRl in Figure 10 during the Phase B positive half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase B positive half-cycle, identified as point 3 in Figure 11 , transistor Q3 in Figure 10 is turned OFF and transistor Q5 in Figure 10 is used instead to control the current applied to the load from the positive half-cycle of phase C. Just as Q3 was turned ON and OFF as necessary to control current during the Phase B positive half-cycle, transistor Q5 is turned ON and OFF, together with SCRl in Figure 10 during the Phase C positive half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase C positive half-cycle, identified as point 4 in Figure 11, transistor Q5 in Figure 10 is turned OFF and transistor Ql in Figure 10 is used instead to control the current applied to the load from the positive half-cycle of phase A. Just as Q5 was turned ON and OFF as necessary to control current during the Phase C positive half-cycle, transistor Ql is turned ON and OFF, together with SCRl in Figure 10 during the Phase A positive half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase A positive half-cycle, identified as point 5 in Figure 11, transistor Ql in Figure 10 is turned OFF and transistor Q3 in Figure 10 is used instead to control the current applied to the load from the positive half-cycle of phase B. Just as Ql was turned ON and OFF as necessary to control current during the Phase A positive half-cycle, transistor Q3 is turned ON and OFF, together with SCRl in Figure 10 during the Phase B positive half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase B positive half-cycle, identified as point 6 in Figure 11 , transistor Q3 in Figure 10 is turned OFF and transistor Q5 in Figure 10 is used instead to control the current applied to the load from the positive half-cycle of phase B. Just as Q3 was turned ON and OFF as necessary to control current during the Phase B positive half-cycle, transistor Q5 is turned ON and OFF, together with SCRl in Figure 10 during the Phase C positive half-cycle to control current to the load.

At a point about 5 degrees before the end of Phase C positive half-cycle, identified as point 7 in Figure 11, transistor Q5 in Figure 10 is turned ON and left ON through the voltage zero-crossing and partway into the negative half-cycle of Phase C until the current through the load is brought back to zero. If SCRl in Figure 10 was ON at the point where Q5 was turned ON, it will be commutated OFF by the reverse-bias voltage across it.

At some time during the Phase C negative half-cycle, the current through the load will go to zero and at the same time transistor Q6 in Figure 10 will be turned ON to start supplying negative-polarity voltage to the load. This is identified as Point 8 in Figure 11. Q6 and SCR2 in Figure 10 are then turned ON and OFF as needed according to the methods of this invention during the Phase C negative half-cycle to drive the current through the load to the desired value. At a point about 30 degrees before the end of the phase C negative half-cycle, identified as point 9 in Figure 11, transistor Q6 in Figure 10 is turned OFF and transistor Q2 in Figure 10 is used instead to control the current applied to the load from the negative half-cycle of phase A. Just as Q6 was turned ON and OFF as necessary to control current during the Phase C negative half-cycle, transistor Q2 is turned ON and OFF, together with SCR2 in Figure 10 during the Phase A negative half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase A negative half-cycle, identified as point 10 in Figure 11 , transistor Q2 in Figure 10 is turned OFF and transistor Q4 in Figure 10 is used instead to control the current applied to the load from the negative half-cycle of phase B. Just as Q2 was turned ON and OFF as necessary to control current during the Phase A negative half-cycle, transistor Q4 is turned ON and OFF, together with SCR2 in Figure 10 during the Phase B negative half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase B negative half-cycle, identified as point 11 in Figure 11 , transistor Q4 in Figure 10 is turned OFF and transistor Q6 in Figure 10 is used instead to control the current applied to the load from the negative half-cycle of phase C. Just as Q4 was turned ON and OFF as necessary to control current during the Phase B negative half-cycle, transistor Q6 is turned ON and OFF, together with SCR2 in Figure 10 during the Phase C negative half-cycle to control current to the load.

At a point about 30 degrees before the end of the phase C negative half-cycle, identified as point 12 in Figure 11, transistor Q6 in Figure 10 is turned OFF and transistor Q2 in Figure 10 is used instead to control the current applied to the load from the negative half-cycle of phase A. Just as Q6 was turned ON and OFF as necessary to control current during the Phase C negative half-cycle, transistor Q2 is turned ON and OFF, together with SCR2 in Figure 10 during the Phase A negative half-cycle to control current to the load. At a point about 30 degrees before the end of the phase A negative half-cycle, identified as point 13 in Figure 11 , transistor Q2 in Figure 10 is turned OFF and transistor Q4 in Figure 10 is used instead to control the current applied to the load from the negative half-cycle of phase B. Just as Q2 was turned ON and OFF as necessary to control current during the Phase A negative half-cycle, transistor Q4 is turned ON and OFF, together with SCR2 in Figure 10 during the Phase B negative half-cycle to control current to the load.

At a point about 5 degrees before the end of the phase B negative half-cycle, identified as point 14 in Figure 11, transistor, Q6 in Figure 10 is turned ON and left ON through the voltage zero-crossing and partway into the negative half-cycle of Phase C until the current through the load is brought back to zero at point 15 in Figure 11. If SCR2 in Figure 10 was ON at the point where Q6 was turned ON, it will be commutated OFF by the reverse-bias voltage across it.

If no more current is desired through the load at this time, all six transistors are left in the OFF state.

Although several structures and methods to control AC current through an inductive load using a SPDT switch or its electronic equivalent have been disclosed, many more variations are possible and are considered to be within the scope of this invention.

While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. Method for controlling AC current supplied to an inductive load having first and second terminals from an AC powerline having a third terminal and current and voltage waveforms having a common frequency, the method comprising the steps of:

(a) electrically connecting the first terminal to the third terminal but not to the second terminal so that at no time is the first terminal electrically connected to both the second and third terminals wherein the inductive load is electrically connected to the powerline; (b) electrically disconnecting the first terminal from the third terminal and electrically connecting the first terminal to the second terminal so that at no time is the first terminal disconnected from both the second and third terminals wherein the first and second terminals of the load are short-circuited; and

(c) alternately performing steps (a) and (b) to control the AC current supplied to the inductive load from the AC powerline.

2. The method as claimed in claim 1 , wherein the powerline has a half-cycle and wherein step (c) is performed so that the amount of time that the first terminal is connected to the third terminal is greater than the amount of time that the first terminal is connected to the second terminal during a beginning part of the half- cycle than during a latter part of the half-cycle to reduce phase difference between the current and voltage waveforms of the powerline.

3. The method as claimed in claim 2, wherein the current and voltage waveforms of the powerline are substantially in phase.

4. The method as claimed in claim 1 , wherein step (c) is performed so that the AC current supplied to the inductive load has a non-sinusoidal current waveform.

5. The method as claimed in claim 4, wherein the non-sinusoidal current waveform is a substantially square current waveform.

6. The method as claimed in claim 1 , wherein step (c) is performed so that the current supplied to the inductive load has a substantially sinusoidal current waveform.

7. The method as claimed in claim 1 , wherein step (c) is performed so that the AC current supplied to the inductive load has a desired frequency less than the common frequency.

8. The method as claimed in claim 7, wherein the desired frequency is a sub-multiple of the common frequency.

9. The method as claimed in claim 1, wherein step (c) is performed at frequency greater than the common frequency of the powerline.

10. A system for controlling AC current supplied to an inductive load having first and second terminals from an AC powerline having a third terminal and current and voltage waveforms having a common frequency, the system comprising: a switch; and a controller for controlling the switch so that the switch:

(a) electrically connects the first terminal to the third terminal but not to the second terminal so that at no time is the first terminal electrically connected to both the second and third terminals wherein the inductive load is electrically connected to the powerline;

(b) electrically connects the first terminal to the third terminal and electrically connects the first terminal to the second terminal so that at no time is the first terminal disconnected from both the second and third terminals wherein the first and second terminals of the load are short- circuited; and

(c) alternately performs steps (a) and (b) to control the AC current supplied to the inductive load from the AC powerline.

11. The system as claimed in claim 10, wherein the powerline has a half-cycle and wherein the controller controls the switch so that the amount of time that the first terminal is connected to the third terminal is greater than the amount of time that the first terminal is connected to the second terminal during a beginning part of the half-cycle than during a latter part of the half-cycle to reduce phase difference between the current and voltage waveforms of the powerline.

12. The system as claimed in claim 11, wherein current and voltage waveforms of the powerline are substantially in phase.

13. The system as claimed in claim 10, wherein the controller controls the switch so that the AC current supplied to the inductive load has a non- sinusoidal current waveform.

14. The system as claimed in claim 13, wherein the non-sinusoidal current waveform is a substantially square current waveform.

15. The system as claimed in claim 10, wherein the controller controls the switch so that the current supplied to the inductive load has a substantially sinusoidal current waveform.

16. The system as claimed in claim 10, wherein the controller controls the switch so that the AC current supplied to the inductive load has a desired frequency less than the common frequency.

17. The system as claimed in claim 16, wherein the desired frequency is a sub-multiple of the common frequency.

18. The system as claimed in claim 10, wherein the controller controls the switch at a frequency greater than the common frequency of the powerline.

19. The system as claimed in claim 10, wherein the switch is an electronic device.

20. The system as claimed in claim 19, wherein the electronic device is an equivalent to an SPDT switch.