WO2000033188A3 - Efficient handling of a large register file for context switching and function calls and returns - Google Patents
Efficient handling of a large register file for context switching and function calls and returns Download PDFInfo
- Publication number
- WO2000033188A3 WO2000033188A3 PCT/US1999/028470 US9928470W WO0033188A3 WO 2000033188 A3 WO2000033188 A3 WO 2000033188A3 US 9928470 W US9928470 W US 9928470W WO 0033188 A3 WO0033188 A3 WO 0033188A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- register
- dirty bit
- registers
- group
- written
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/462—Saving or restoring of program or task context with multiple register sets
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/463—Program control block organisation
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/204,586 US6205543B1 (en) | 1998-12-03 | 1998-12-03 | Efficient handling of a large register file for context switching |
US09/204,586 | 1998-12-03 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2000033188A2 WO2000033188A2 (en) | 2000-06-08 |
WO2000033188A3 true WO2000033188A3 (en) | 2000-10-19 |
WO2000033188A9 WO2000033188A9 (en) | 2001-04-12 |
Family
ID=22758544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/028470 WO2000033188A2 (en) | 1998-12-03 | 1999-12-02 | Efficient handling of a large register file for context switching and function calls and returns |
Country Status (2)
Country | Link |
---|---|
US (3) | US6205543B1 (en) |
WO (1) | WO2000033188A2 (en) |
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CN1214321C (en) * | 2000-12-11 | 2005-08-10 | 皇家菲利浦电子有限公司 | Signal processing device and method for supplying a signal processing results to a plurality of registers |
US7327759B2 (en) * | 2001-07-25 | 2008-02-05 | International Business Machines Corporation | Sequence-preserving deep-packet processing in a multiprocessor system |
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US20050138233A1 (en) * | 2003-12-23 | 2005-06-23 | Intel Corporation | Direct memory access control |
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KR100636596B1 (en) * | 2004-11-25 | 2006-10-23 | 한국전자통신연구원 | Parallel Data Path Architecture for High Energy Efficient |
US20060149940A1 (en) * | 2004-12-27 | 2006-07-06 | Intel Corporation | Implementation to save and restore processor registers on a context switch |
US8171268B2 (en) * | 2005-09-19 | 2012-05-01 | Intel Corporation | Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors |
US7865873B1 (en) | 2005-09-21 | 2011-01-04 | Stored IQ | Browser-based system and method for defining and manipulating expressions |
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US8407715B2 (en) * | 2007-04-30 | 2013-03-26 | National Tsing Hua University | Live range sensitive context switch procedure comprising a plurality of register sets associated with usage frequencies and live set information of tasks |
GB2451845B (en) * | 2007-08-14 | 2010-03-17 | Imagination Tech Ltd | Compound instructions in a multi-threaded processor |
US8762692B2 (en) * | 2007-09-27 | 2014-06-24 | Intel Corporation | Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode |
US8631261B2 (en) | 2007-12-31 | 2014-01-14 | Intel Corporation | Context state management for processor feature sets |
CN101819518B (en) * | 2009-02-26 | 2013-09-11 | 国际商业机器公司 | Method and device for quickly saving context in transactional memory |
US8769498B2 (en) | 2011-12-07 | 2014-07-01 | International Business Machines Corporation | Warning of register and storage area assignment errors |
CN102707990B (en) * | 2012-05-14 | 2015-04-08 | 华为技术有限公司 | Container based processing method and device |
US9898330B2 (en) * | 2013-11-11 | 2018-02-20 | Intel Corporation | Compacted context state management |
US10019283B2 (en) * | 2015-06-22 | 2018-07-10 | Advanced Micro Devices, Inc. | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread |
KR20170065845A (en) * | 2015-12-04 | 2017-06-14 | 삼성전자주식회사 | Processor and controlling method thereof |
US10628320B2 (en) | 2016-06-03 | 2020-04-21 | Synopsys, Inc. | Modulization of cache structure utilizing independent tag array and data array in microprocessor |
US10558463B2 (en) | 2016-06-03 | 2020-02-11 | Synopsys, Inc. | Communication between threads of multi-thread processor |
US10318302B2 (en) * | 2016-06-03 | 2019-06-11 | Synopsys, Inc. | Thread switching in microprocessor without full save and restore of register file |
US10613859B2 (en) | 2016-08-18 | 2020-04-07 | Synopsys, Inc. | Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions |
US10552158B2 (en) | 2016-08-18 | 2020-02-04 | Synopsys, Inc. | Reorder buffer scoreboard having multiple valid bits to indicate a location of data |
US10403351B1 (en) * | 2018-02-22 | 2019-09-03 | Advanced Micro Devices, Inc. | Save and restore scoreboard |
US10423218B1 (en) | 2018-03-12 | 2019-09-24 | Micron Technology, Inc. | Power management integrated circuit with in situ non-volatile programmability |
US10802754B2 (en) * | 2018-03-12 | 2020-10-13 | Micron Technology, Inc. | Hardware-based power management integrated circuit register file write protection |
US10664287B2 (en) | 2018-03-30 | 2020-05-26 | Intel Corporation | Systems and methods for implementing chained tile operations |
US11163568B2 (en) * | 2018-09-06 | 2021-11-02 | International Business Machines Corporation | Implementing write ports in register-file array cell |
KR20210108788A (en) | 2020-02-26 | 2021-09-03 | 삼성전자주식회사 | Apparatus and method for controlling power consumption in wireless communicaiton |
Citations (3)
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EP0213843A2 (en) * | 1985-08-30 | 1987-03-11 | Advanced Micro Devices, Inc. | Digital processor control |
EP0272150A2 (en) * | 1986-12-19 | 1988-06-22 | Kabushiki Kaisha Toshiba | Register device |
US5530817A (en) * | 1992-02-21 | 1996-06-25 | Kabushiki Kaisha Toshiba | Very large instruction word type computer for performing a data transfer between register files through a signal line path |
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1998
- 1998-12-03 US US09/204,586 patent/US6205543B1/en not_active Expired - Lifetime
-
1999
- 1999-12-02 WO PCT/US1999/028470 patent/WO2000033188A2/en active Application Filing
-
2001
- 2001-03-19 US US09/812,733 patent/US7010674B2/en not_active Expired - Lifetime
-
2006
- 2006-03-06 US US11/369,212 patent/US7490228B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0213843A2 (en) * | 1985-08-30 | 1987-03-11 | Advanced Micro Devices, Inc. | Digital processor control |
EP0272150A2 (en) * | 1986-12-19 | 1988-06-22 | Kabushiki Kaisha Toshiba | Register device |
US5530817A (en) * | 1992-02-21 | 1996-06-25 | Kabushiki Kaisha Toshiba | Very large instruction word type computer for performing a data transfer between register files through a signal line path |
Non-Patent Citations (3)
Title |
---|
"ALLOCATED BITS FOR MACHINES WITH VECTOR REGISTERS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 3A, August 1990 (1990-08-01), US,IBM CORP. NEW YORK, pages 310 - 314, XP000123953, ISSN: 0018-8689 * |
"TECHNIQUE FOR REDUCING THE NUMBER OF REGISTERS SAVED AT A CONTEXT SWAP", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 3A, August 1990 (1990-08-01), US,IBM CORP. NEW YORK, pages 234 - 235, XP000123918, ISSN: 0018-8689 * |
"TECHNIQUE TO IMPROVE CONTEXT SWITCHING PERFORMANCE IN A CPU", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 3B, August 1990 (1990-08-01), US,IBM CORP. NEW YORK, pages 472 - 473, XP000124425, ISSN: 0018-8689 * |
Also Published As
Publication number | Publication date |
---|---|
WO2000033188A2 (en) | 2000-06-08 |
US6205543B1 (en) | 2001-03-20 |
US7010674B2 (en) | 2006-03-07 |
WO2000033188A9 (en) | 2001-04-12 |
US20060242388A1 (en) | 2006-10-26 |
US7490228B2 (en) | 2009-02-10 |
US20010010075A1 (en) | 2001-07-26 |
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