WO2000028683A3 - Emulation for synchronous behavior in a plesiosynchronous environment - Google Patents

Emulation for synchronous behavior in a plesiosynchronous environment Download PDF

Info

Publication number
WO2000028683A3
WO2000028683A3 PCT/US1999/026486 US9926486W WO0028683A3 WO 2000028683 A3 WO2000028683 A3 WO 2000028683A3 US 9926486 W US9926486 W US 9926486W WO 0028683 A3 WO0028683 A3 WO 0028683A3
Authority
WO
WIPO (PCT)
Prior art keywords
mark
node
isochronous
destination
payload
Prior art date
Application number
PCT/US1999/026486
Other languages
French (fr)
Other versions
WO2000028683A9 (en
WO2000028683A2 (en
Inventor
Paul M Sweazey
Original Assignee
Intera Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intera Systems Inc filed Critical Intera Systems Inc
Priority to AU21469/00A priority Critical patent/AU2146900A/en
Publication of WO2000028683A2 publication Critical patent/WO2000028683A2/en
Publication of WO2000028683A3 publication Critical patent/WO2000028683A3/en
Publication of WO2000028683A9 publication Critical patent/WO2000028683A9/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0421—Circuit arrangements therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

A switch fabric (100) is disclosed in which a cycle master node (104) is coupled to destination nodes (108) to distribute isochronous payload among nodes (104, 108). Precise temporal information is distributed throughout the fabric (100) in slots (312) to identify isochronous payload by the payload"s occurrence in a particular place and time. The cycle master (104) distributes a unique symbol called a mark (304) to each destination node (108). The mark (304) identifies the beginning of an isochronous cycle (300) to each destination node (108) which receives the mark (304). The cycle master (104) distributes isochronous symbols (312) which provides the isochronous payload information to the destination node (108). The distribution of slots (312) in combination with a mark symbol (304) allows each node to determine the local time at any given time by counting the number of slots (312) received after the last mark (304) received. The cycle master (104) also distributes gap symbols (320) to the destination nodes (108), which allow the destination nodes (108) to maintain a uniform throughput throughout the fabric (100) regardless of the transmission capacity of each node (104, 108).
PCT/US1999/026486 1998-11-09 1999-11-09 Emulation for synchronous behavior in a plesiosynchronous environment WO2000028683A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU21469/00A AU2146900A (en) 1998-11-09 1999-11-09 Emulation for synchronous behavior in a plesiosynchronous environment

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US10773298P 1998-11-09 1998-11-09
US60/107,732 1998-11-09
US12458199P 1999-03-16 1999-03-16
US60/124,581 1999-03-16
US12726299P 1999-03-31 1999-03-31
US60/127,262 1999-03-31

Publications (3)

Publication Number Publication Date
WO2000028683A2 WO2000028683A2 (en) 2000-05-18
WO2000028683A3 true WO2000028683A3 (en) 2000-11-09
WO2000028683A9 WO2000028683A9 (en) 2002-08-22

Family

ID=27380349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/026486 WO2000028683A2 (en) 1998-11-09 1999-11-09 Emulation for synchronous behavior in a plesiosynchronous environment

Country Status (2)

Country Link
AU (1) AU2146900A (en)
WO (1) WO2000028683A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004055105A1 (en) * 2004-11-15 2006-05-24 Bosch Rexroth Aktiengesellschaft Method for time synchronization in a cyclic communication system
US20080198877A1 (en) * 2005-06-13 2008-08-21 Nxp B.V. Electronic Device, Method for Frame Synchronization, and Mobile Device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3511352A1 (en) * 1985-03-28 1986-10-09 Siemens AG, 1000 Berlin und 8000 München Method and coupling device for distribution of plesiochronous broadband digital signals
DE3619371A1 (en) * 1986-06-09 1987-12-10 Siemens Ag Method for multiplexing and demultiplexing plesiochronous digital signals
EP0404423A2 (en) * 1989-06-22 1990-12-27 Digital Equipment Corporation Reconfiguration system and method for high-speed mesh connected local area network
EP0522607A1 (en) * 1991-05-29 1993-01-13 Telefonaktiebolaget L M Ericsson A method and an arrangement for synchronizing two or more communication networks of the time multiplex type
US5754789A (en) * 1993-08-04 1998-05-19 Sun Microsystems, Inc. Apparatus and method for controlling point-to-point interconnect communications between nodes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3511352A1 (en) * 1985-03-28 1986-10-09 Siemens AG, 1000 Berlin und 8000 München Method and coupling device for distribution of plesiochronous broadband digital signals
DE3619371A1 (en) * 1986-06-09 1987-12-10 Siemens Ag Method for multiplexing and demultiplexing plesiochronous digital signals
EP0404423A2 (en) * 1989-06-22 1990-12-27 Digital Equipment Corporation Reconfiguration system and method for high-speed mesh connected local area network
EP0522607A1 (en) * 1991-05-29 1993-01-13 Telefonaktiebolaget L M Ericsson A method and an arrangement for synchronizing two or more communication networks of the time multiplex type
US5754789A (en) * 1993-08-04 1998-05-19 Sun Microsystems, Inc. Apparatus and method for controlling point-to-point interconnect communications between nodes

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DALLY W J ET AL: "DESIGN OF A SELF-TIMED VLSI MULTICOMPUTER COMMUNICATION CONTROLLER", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS. (ICCD),US,WASHINGTON, IEEE COMP. SOC. PRESS, vol. -, 1987, pages 230 - 234, XP000012145, ISBN: 0-8186-0802-1 *
YORAM OFEK ET AL: "THE INTEGRATED METANET ARCHITECTURE: A SWITCH-BASED MULTIMEDIA LAN FOR PARALLEL COMPUTING AND REAL-TIME TRAFFIC", PROCEEDINGS OF THE CONFERENCE ON COMPUTER COMMUNICATIONS (INFOCOM),US,LOS ALAMITOS, IEEE COMP. SOC. PRESS, 1994, pages 802 - 811, XP000496538, ISBN: 0-8186-5572-0 *

Also Published As

Publication number Publication date
WO2000028683A9 (en) 2002-08-22
AU2146900A (en) 2000-05-29
WO2000028683A2 (en) 2000-05-18

Similar Documents

Publication Publication Date Title
WO1999053647A3 (en) System and process for flexible queueing of data packets in network switching
US5812547A (en) System and method for dynamic time division access
EP0432800A3 (en) High-speed asynchronous transfer mode packet switching network system having time slot scheduling unit
DK0461279T3 (en) Procedure for routing suppressed propagation packages
EP1093646A4 (en) Method and apparatus for gap count determination
HU9602423D0 (en) Expandable telecommunications system
WO2001028170A3 (en) A protocol for neighborhood-established transmission scheduling
FI971094A (en) Transmission of control signals in digital radiotelephone traffic
JPH0498940A (en) Method for revising virtual path capacity
ATE322130T1 (en) NETWORK IDENTITY INSERT ARCHITECTURE FOR ROMBABLE MESSAGE SYSTEM
CA2036756C (en) High-speed time-division switching system
EP0829153A4 (en) Virtual path-based static routing
CA2334972A1 (en) Method and apparatus for non-disruptive addition of a new node to an inter-nodal network
ES2188626T3 (en) CIRCUIT PROCEDURE AND PROVISION FOR THE SYNCHRONIZATION OF CURRENTS OF INFORMATION CELLS TRANSMITTED REDUNDANTLY.
NO992757L (en) Telecommunications System
AU6377099A (en) Methods for changing the bandwidth of a circuit switched channel
EP0797374A3 (en) Synchronous transmission system adapted to carry both synchronous and asynchronous traffic
CA2254582A1 (en) An improved network and method for atm network operations
EP0299749A3 (en) Multi-slot access system
EP1139242A3 (en) Non-synchronized multiplex data transport across synchronous systems
WO2000028683A3 (en) Emulation for synchronous behavior in a plesiosynchronous environment
WO1997033396A3 (en) Network synchronisation
SE9101635D0 (en) SETTING AND DEVICE TO SYNCHRONIZE TWO OR MULTIPLE MULTIPLE TYPE COMMUNICATIONS
SE9601133L (en) slave Nodes
EP0862288B1 (en) Clock signal supplying apparatus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

AK Designated states

Kind code of ref document: C2

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: C2

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

COP Corrected version of pamphlet

Free format text: PAGES 1/9-9/9, DRAWINGS, REPLACED BY NEW PAGES 1/9-9/9; DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE

122 Ep: pct application non-entry in european phase