WO2000020900A2 - Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method - Google Patents
Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method Download PDFInfo
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- WO2000020900A2 WO2000020900A2 PCT/US1999/022317 US9922317W WO0020900A2 WO 2000020900 A2 WO2000020900 A2 WO 2000020900A2 US 9922317 W US9922317 W US 9922317W WO 0020900 A2 WO0020900 A2 WO 0020900A2
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- substrate
- reflective coating
- dielectric layer
- silicon carbide
- thickness
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- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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Definitions
- the present invention relates generally to the fabrication of integrated circuits on substrates. More particularly, the invention relates to a low temperature method for producing a low dielectric constant (low K) silicon carbide film utilizing organosilanes under certain process regimes, which is useful as a low K anti-reflective coating.
- low K dielectric constant
- conductive materials having low resistivity and low K (dielectric constant less than 7.0) insulators to reduce the capacitive coupling between adjacent metal lines.
- low K materials extends to barrier layers, etch stops, and anti-reflective coatings used in photolithography.
- typical barrier layer, etch stop, and anti-reflective coating materials have dielectric constants that are significantly greater than 7.0 that result in a combined insulator that does not significantly reduce the dielectric constant.
- better materials are needed for barrier layers, etch stops, and anti-reflective coatings in the low K substrates.
- Photolithography is a technique used in making integrated circuits that uses light patterns and typically organic polymers (photoresist materials) to develop fine-scaled patterns on a substrate surface.
- Photoresist materials typically include, for example, naphthoquinone diazides.
- the high reflectivity of the layer to be patterned must be ameliorated so light ray reflection is reduced. Reflectivity is usually expressed as a percentage of a known standard, such as bare silicon, having a value of 100%.
- ARC anti- reflective coating
- ARC materials can be organic or inorganic, as described in U.S. Pat. No. 5,710,067, which is incorporated by reference herein.
- Organic ARCs include spin-on polyimides and polysulfones, among other materials, and are generally more expensive and require more complex processing than inorganic ARCs.
- Inorganic ARCs include silicon nitride, silicon oxynitride, ⁇ -carbon, titanium nitride, silicon carbide, and amorphous silicon. Prior to the present invention, inorganic ARCs typically were characterized by a high K value and were not compatible with low K structures.
- a high K ARC partially negates the advantage of changing to low K materials in that it adds a high K material to a stack of otherwise low K layers.
- the high K ARC can be removed from the substrate, but the removal adds complexity to the processing.
- Organic ARCs can be used, but they are generally more expensive and require additional processing.
- Figure 1 shows a representation of a substrate with a positive photoresist deposited over a dielectric, as part of the photolithography processing.
- a positive photoresist develops in the areas exposed to light, whereas a negative photoresist develops in the areas not exposed to light.
- the integrated circuit 10 includes an underlying substrate 12 having a feature 11, such as a contact, via, line, or trench.
- substrate is used to indicate an underlying material, and can be used to represent a series of underlying layers below the layer in question, such as a barrier layer.
- a barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14.
- the dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low K material.
- an ARC 15 is deposited the dielectric, followed by a photoresist layer 19.
- the purpose of the ARC is to reduce or eliminate any reflected light waves, typically, by adjusting three aspects of the ARC material ⁇ a refraction index (n), an absorption index (k, distinguished from the "K” of a “low K” dielectric), and the thickness (t) of the ARC to create a phase cancellation and absorption of reflected light.
- n refraction index
- k absorption index
- t thickness
- the required n, k, and t values depend on the thickness and properties of the underlying layer and need adjustment for each particular application.
- a computer simulation program such as one entitled “The Positive/Negative Resist Optical Lithography Model", v. 4.05, simulates the effect on the n, k, and t values and the reflectivity of the particular layers.
- n, k, and t are dependent on each application and each substrate thickness, the proper selection may be time consuming and onerous. In addition, the selection may be only applicable to narrow thickness ranges of the underlying layers which may cause additional difficulties in the repeatability of the deposition process from substrate to substrate.
- Figure 2 is a schematic of the photolithography process in which a light source 23 emits light, such as ultraviolet light, through a patterned template (mask) 21 that defines the pattern of light that will be projected onto the photoresist layer 19, ultimately resulting in a patterned substrate.
- the light causes the photoresist in the exposed area 25 to typically change its solubility to organic solvents, for instance, when exposed to violet light.
- the exposed areas can be removed by soaking or otherwise cleaning the exposed areas while retaining the unexposed areas.
- Figure 3 is a schematic of the substrate with the feature 27 formed thereon using the etching process. The remainder of the photoresist has been removed, the feature has been etched to the appropriate level, and the substrate is prepared for a subsequent process such as the deposition of a liner, dielectric, conductor, or other layer(s).
- Figure 4 shows one example of a dual damascene structure.
- Two predominate schemes currently are used to develop a dual damascene structure, where lines/trenches are filled concurrently with vias/contacts.
- the integrated circuit 10 includes an underlying substrate 12, which may include a series of layers deposited thereon and in which a feature 11 has been formed.
- a barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14.
- a liner 22 may be needed, which typically is Ta, TaN, Ti, TIN, and other materials.
- the dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low K material.
- a low K etch stop 16 such as ⁇ -C, ⁇ -FC, parylene, AF 4 , BCB, PAE, oxynitride or silicon carbide, is then deposited on the dielectric layer 14 to a thickness of about 200 A to about 1000 A.
- the etch stop material is typically a material that has a slower etching rate compared to the dielectric layer that is etched and allows some flexibility in the etching process in insuring that a predetermined depth is reached. In some well characterized etching processes, the etch stop may be unnecessary.
- Another dielectric layer 18 is deposited over etch stop 16 to a thickness of about 5,000 A to about 10,000 A.
- the photoresist layer is exposed to form a pattern for the via/contact 20a, using conventional photolithography.
- the layers are etched using conventional etch processes, such as using fluorine, carbon, and oxygen ions to form the via/contact 20a, and the photoresist layer is removed.
- Another photoresist layer is deposited and exposed to pattern the line/trench 20b, the layer(s) are etched to form the line/trench 20b, and the photoresist layer is removed.
- a conductive material 20 is then deposited simultaneously in both the via/contact 20a and the line/trench 20b. Once the conductive material 20 has filled the feature(s), another barrier layer 24 may be deposited to help prevent diffusion of the conductor, such as the copper, for the next series of layers, if applicable.
- the other predominate scheme for creating a dual damascene structure is known as a "self-aligning contact" (SAC) scheme.
- the SAC scheme is similar to the counterbore scheme, except that a photoresist layer is deposited over the etch stop 16 prior to the deposition of the dielectric layer 18.
- the etch stop 16 is etched to form a pattern for a via/contact 20a.
- the photoresist layer is removed and the dielectric layer 18 and ARC 15 are then deposited over the etch stop, followed by another photoresist layer deposited on the ARC 15.
- the photoresist is then exposed to form the pattern for the line/trench 20b, the line/trench 20b and the via/contact 20a are etched simultaneously, and the photoresist layer is removed.
- Conductive material 20, and if desired, another barrier layer 24, are then deposited.
- the reflectivity of such multilevel structures as a damascene structure has raised the needed level of performance of ARC materials.
- the layer to be etched was typically above a single metal layer which is not transparent to the light exposure.
- the unwanted photoresist exposure from underlying layers was substantially limited to the single metal layer under the photoresist.
- an increased number of layers above the conductor layer are now used with multilevel patterning.
- the dielectric layer(s) and other layers beside the conductor layer are comparatively transparent to the exposure light and thus more levels of reflections can hinder the photolithography processing of the upper layer. For instance, lines and vias/contacts may appear in the substrate at different levels. Light reflected from the different features at the different levels result in different reflected light patterns back to the photoresist layer and unless corrected may cause the unwanted exposure on the photoresist described above.
- Silicon nitride and oxynitride have been typical materials used for an ARC, but have a relatively high dielectric constant (dielectric constant greater than 7.0) and may significantly increase the capacitive coupling between interconnect lines.
- the capacitive coupling may lead to cross talk and/or resistance-capacitance (RC) delay, i.e., the time required to dissipate stored energy, that degrades the overall performance of the device.
- RC resistance-capacitance
- silicon nitride and oxynitride have relatively poor diffusion resistance compared to the material of the present invention.
- the present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications.
- the same material may also be used as a barrier layer and an etch stop, even in complex damascene structures and with high diffusion conductors such as copper.
- a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers.
- the thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to maintain a given reflectivity.
- a preferred process sequence for forming a silicon carbide anti-reflective coating on a substrate comprises introducing silicon, carbon, and a noble gas into a reaction zone of a process chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide anti- reflective coating on a substrate in the chamber.
- Another aspect of the invention includes a substrate having a silicon carbide anti- reflective coating, comprising a semiconductor substrate, a dielectric layer deposited on the substrate, and a silicon carbide anti-reflective coating having a dielectric constant of less than about 7.0 and preferably about 6.0 or less.
- Figure 1 is a schematic of photoresist material on an ARC in a substrate.
- Figure 2 is a schematic of a light exposing the photoresist of Figure 1.
- Figure 3 is a schematic of the substrate of Figures 1 and 2, etched and prepared for subsequent deposition in the feature.
- Figure 4 is a schematic of an exemplary damascene structure.
- Figure 5 is a FTIR of the SiC of the present invention, indicating a particular bonding structure.
- Figure 6 is a FTIR of a previous SiC, indicating a bonding structure different than the SiC of the present invention.
- Figure 7 is a graph of a dielectric constant compared to a refraction index for various materials.
- Figure 8 is a graph of the refraction index compared to the absorption index for two materials, showing that the SiC of the present invention can be tuned to different index values.
- Figure 9 is a schematic of a stack of layers using the SiC of the present invention as a barrier layer, an etch stop, and an ARC.
- Figure 10 is a simulation graph of reflectivity contours of the embodiment of Figure 9.
- Figure 11 is a line drawing of a scanning electron microscopy photograph, showing a patterned photoresist layer using the ARC of the present invention as an upper layer.
- Figure 12 are FTIR results of a moisture test of the SiC of the present invention, when the SiC ARC is also used as a moisture barrier.
- Figure 13 is an alternative embodiment of Figure 9, using the etch stop as the ARC without using an ARC upper layer.
- Figure 14 is a reflectivity map of the embodiment of Figure 13, showing the thicknesses of the upper dielectric layer compared to the etch stop.
- Figure 15 is a reflectivity map of the embodiment of Figure 13, showing the thicknesses of the etch stop compared to the lower dielectric layer under the etch stop.
- Figure 16 is an alternative embodiment of Figures 9 and 13, without the etch stop and using the barrier layer as the ARC.
- Figure 17 is a reflectivity map of the embodiment of Figure 16, showing the thicknesses of the dielectric layer above the barrier layer compared to the barrier layer, using the barrier layer as an ARC.
- Figure 18 is another embodiment similar to the embodiment of Figure 16 with the addition of a SiC ARC below the photoresist layer.
- Figure 19 is a reflectivity map of the embodiment of Figure 18, showing the thickness of the ARC compared to the thickness of the dielectric layer under the ARC.
- Figure 20 is a graph of copper diffusion into the SiC material of the present invention. Detailed Description of a Preferred Embodiment
- the present invention provides a SiC material, formed according to certain process regimes, useful as an ARC for an IC.
- the same material may also be used as a barrier layer and/or etch stop, and particularly for an IC using high diffusion copper as a conductive material.
- the invention also provides processing regimes that includes using an organosilane as a silicon and carbon source, perhaps independently of any other carbon source or hydrogen source necessary to produce the SiC and perhaps in the absence of a substantial amount of oxygen.
- the process regimes also include the presence of a noble gas, such as helium or argon, and certain temperatures, pressures, power outputs in a plasma enhanced chemical vapor deposition chamber to produce the SiC of the present invention.
- This particular SiC material may be especially useful in complex structures, such as a damascene structure.
- Table 1 below shows some of the general requirements for an ARC. Because the SiC, as explained below, may be used in multiple functions, Table 1 shows the desirable aspects of at least three of the uses of the SiC of the present invention as an ARC, a barrier layer, and an etch stop.
- the SiC is used as an ARC, desirable characteristics would include the low K aspect described above as well as a suitable refraction index "n” combined with an absorption index "k” and a thickness "t” of the ARC to obtain a low reflectivity below about 5%, although other values may be selected, so that the coating could be used in multiple applications without necessitating adjustments and variations for each application, as is typically needed, prior to the present invention.
- the process to produce the SiC should be stable and repeatable for manufacturing consistency.
- the ARC may remain on the substrate because of its low K attributes, it may also function as a barrier layer between, for instance, an underlying dielectric and a conductor material, such as copper. Thus, the barrier properties may be important in such instances. Adhesion between the layers is important to reduce delamination between the layers and, in some instances, to reduce capacitance and resistance between the layers.
- the material should also have no substantial diffusion at a substrate annealing temperature of, for example, 400°-450° C. The term "no substantial" diffusion is intended to be a functional term, such that any actual diffusion into the layer is less than would affect the ability of the layer to function as a barrier layer and/or etch stop.
- the SiC of the present invention limits the diffusion to about 250 A.
- the copper diffusion may impair the desired current and voltage paths and contribute to cross talk.
- the lower the dielectric constant preferably less than 7.0, the lower the probability for cross talk and RC delay which degrades the overall performance of the device.
- a low K material is defined herein as a material having a dielectric constant lower than that of silicon nitride (dielectric constant of greater than or equal to 7.0), which has traditionally been used as a barrier layer material.
- the "effective" dielectric constant is a composite dielectric constant of the substrate stack with multiple levels.
- the effective dielectric constant is based on such factors as the layer thicknesses, layer dielectric constants, spacing between features, and feature dimensions.
- Commercially available software such as "Rafael" by Avant Corporation may be used to calculate the predicted effective dielectric constant.
- a typical value of a low K dielectric layer is about 2.7.
- a SiN layer may have a K value of 7.0.
- Using the SiN material with the low K material would increase the effective K value of the composite and offset some of the advantage of using the low K dielectric material.
- using the SiC of the present invention with a K value of less than 5, preferably about 4.2 allows more benefit from using low K dielectric material to be obtained.
- a desirable effective dielectric constant value for the composite structure would be about 5.0 or less, most preferably 3.0 or less.
- the SiC may be used in a damascene structure and function as a dual purpose ARC and etch stop as discussed below in one embodiment, it would be beneficial to also have suitable etch stop characteristics, such as an etch selectivity ratio of 20 to 1 or greater with respect to USG, FSG, or other low K dielectric materials.
- the material should have a high breakdown voltage of 2 MV or more, i.e., the voltage gradient at which the molecules breakdown to allow harmful passage of electrical current.
- the SiC should also have a low leakage characteristic through the layer, i.e., a low stray direct current that capacitively flows through the material.
- the deposition of the material may be performed in situ, i.e., in a given chamber, such as in a plasma chamber, or in a system, such as an integrated cluster tool arrangement, without exposing the material to intermediate contamination environments.
- This aspect may be particularly important with a copper conductor, because of its rapid susceptibility to oxidation.
- Table 2 shows the process parameters of the present invention used in a 200 mm wafer deposition reactor that allows the SiC material to be used as an ARC, as well as a barrier layer and an etch stop.
- the silicon and carbon were derived from a common compound, such as a silane-based compound.
- the carbon could be supplemented with other compounds, such as methane.
- organosilane as used herein includes any silane-based compound having at least one carbon atom attached, including the preceding list, unless otherwise indicated.
- Table 2 the compounds used were trimethylsilane and methylsilane.
- a noble gas such as helium or argon, was present and may assist in stabilizing the process, although other gases could be used.
- the process regimes described below provide a SiC material that meets at least some of the characteristics of Table 1 of an ARC, as well as a barrier layer and/or etch stop.
- the SiC has a low dielectric constant of less than about 7.0 and preferably about 6.0 or less.
- the SiC properties described herein enable a thinner layer to be deposited.
- An effective substrate dielectric constant of the present invention may be about 5.0 or less. This effective dielectric constant meets the needs of a suitable copper-based IC and contrasts with silicon nitride material described above.
- the SiC in one embodiment allows a diverse range of underlying dielectric thicknesses without needing to adjust the SiC ARC thickness.
- the SiC of the present invention may be used as a combination etch stop and ARC, without needing the upper ARC layer, typical in photolithography.
- This particular SiC material also is suitable for use as a low K, etch stop material.
- a low K material is defined herein as a material having a dielectric constant lower than that of silicon nitride (dielectric constant of greater than or equal to 7.0).
- a low K etch stop material is defined herein as an etch stop material having a dielectric constant lower than that of silicon nitride and having a relative oxide to etch selectivity of 20 to 1 or greater relative to the dielectric material.
- the SiC material of the present invention has a high resistance to copper diffusion with test data showing that the copper diffusion limit is about 200 to 250 A deep in the barrier layer.
- the ARC may be the barrier layer functioning as the ARC without the etch stop.
- a silicon source such as trimethylsilane or methylsilane is supplied to a plasma reactor, specifically a reaction zone in the chamber that is typically between the substrate surface and the gas dispersion element, such as a "showerhead", commonly known to those with ordinary skill in the art.
- a plasma reactor specifically a reaction zone in the chamber that is typically between the substrate surface and the gas dispersion element, such as a "showerhead", commonly known to those with ordinary skill in the art.
- PECVD plasma enhanced chemical vapor deposition
- a silicon source flow rate of about 30 to 500 standard cubic centimeters (seem) is used.
- the sequence and operation of a commercial PECVD chamber are well known and need no explanation for the present invention process regimes.
- the carbon is derived from the trimethylsilane or methylsilane, independent of other carbon sources.
- the reaction occurs without a substantial source of oxygen introduced into the reaction zone.
- a noble gas such as helium or argon
- the chamber pressure is maintained between about 3 to 10 Torr.
- a single 13.56 MHz RF power source applies about 300 to 700 watts with a power density of about 0.67 to 1.55 watts/cm 2 to the anode and cathode to form the plasma in the chamber with the silane-based gas.
- the substrate surface temperature is maintained between about 200° to 400° C, during the deposition of the SiC.
- the gas dispersion from a gas dispersion element, such as a "showerhead" is dispersed at a showerhead to substrate spacing distance between about 300 to 600 mils.
- the trimethylsilane or methylsilane flow rate is adjusted to about 50 to 200 seem, the helium or argon flow rate to about 200 to 1000 seem, the chamber pressure to about 6 to 10 Torr, the RF power to about 400 to 600 watts with a power density of about 0.88 to 1.33 watts/cm 2 , the substrate surface temperature maintained between about 300° to 400° C, and a showerhead to substrate spacing of about 300 to 400 mils, as shown in Table 2.
- the characteristics developed by the preferred and most preferred process regimes differ from the generally accepted silicon carbide characteristics.
- a different bonding structure occurs in the SiC of the present invention, shown in Figure 5, compared to a prior SiC, shown in Figure 6, described below.
- the charts are Fourier Transform Infrared (FTIR) charts, one of the standard laboratory tests for indicating the bonding structure, as would be known to those with ordinary skill in the art and needs no detailed explanation.
- FTIR Fourier Transform Infrared
- Figure 5 shows a FTIR for the SiC of the present invention.
- the deposition resulted in a bonding structure containing CH 2 /CH 3 , SiH, SiCH 3 , Si-(CH 2 )n, and SiC.
- Figure 6 shows comparative results with a prior SiC material deposited using silane and methane. As can be seen, there is no corresponding peak for Si-(CH 2 )n and even the peak for SiCH 3 is not as noticeable.
- the SiC of the present invention has yielded these unexpected results in providing better ARC/barrier layer/etch stop performance than previous known depositions of SiC. These characteristics allow the SiC to be used in the multiple capacities disclosed herein.
- Figures 7-20 show various characteristics of the SiC ARC of the present invention.
- Figure 7 is a graph of test results, using a standard 633 nm wavelength of exposure light, comparing different materials and their dielectric constants versus the refraction index.
- the x-axis represents the refraction index, n, discussed above. A lower value on the x-axis is preferred and results in better optical quality and transparency.
- the y-axis represents the dielectric constant. A lower value on the y-axis is preferred to obtain a "low K" substrate stack.
- SiN typically has an n value of about 2.0 and a dielectric constant value of 7.3, unsuitable for the low K applications.
- a current state-of-the-art ARC is DARCTM, a type of silicon oxynitride, but the dielectric constant is about 8.5-9.0 with a n of about 2.2 at a 248 nm wavelength exposure.
- the preferred SiC of the present invention has a dielectric constant of about 4.2.
- the SiC#l corresponds to test results using the traditional chemistry for producing SiC such as is described in U.S. Pat. No. 5,591,566 to Ogawa, discussed above, particularly using a silane with a separate methane/ethane/propane and diatomic hydrogen.
- This SiC has an n value of about 2.4, and a dielectric constant of about 7.8, undesirable for deposition in low K devices.
- In-house test results that varied the process parameters of this traditional SiC chemistry still did not produce the results that were obtained by changing to the chemistry of the present invention, described herein.
- SiC#2 is one SiC deposited using the chemistry of the present invention.
- the n value is about 2.3 and the dielectric constant is about 5.1, which are much better than the SiC#l produced by traditional processing, above.
- the SiC#3 produced better optical characteristics, namely, an n value of about 1.9 at the 633 nm exposure wavelength of Figure 6 with a dielectric constant of about 4.2.
- the SiC of the present invention is suitable for the current emphasis on low K structures that can be used as an ARC as well as a barrier layer and an etch stop.
- the SiC of the present invention in contrast to the traditional high K SiC, need not be removed from the layer after the photoresist has been exposed and the substrate etched in order to preserve the low K characteristics of the stack of layers, resulting in less processing steps.
- Figure 8 is a graph of the refraction index n compared to the absorption index k for two materials, using a 248 nm exposure wavelength typically used in photolithography processing, showing that the SiC of the present invention can be tuned to different n and k values and is compared with a silicon oxynitride ARC.
- the silicon oxynitride ARC has a steep slope of about 70°, a high dielectric constant of about 9, and is difficult to control the respective n and k values because of the rapid increase in k with a small change in n.
- the SiC of the present invention with a dielectric constant of about 4.5 has a flatter curve, approximating a 35° upward slope of the line on the graph, so that an increase in n results in a comparative increase in k on the graph, and shows a more controllable process.
- a higher absorption index is desirable to better absorb the extraneous reflections, but in obtaining the higher absorption indexes, the dielectric constant increases as the line slopes upward.
- a suitable value for the SiC of the present invention and one that is most preferred, having a relatively low dielectric constant and a stable process regime is about 2.2 for an n value at the 248 nm exposure wavelength of Figure 8 and about 0.4 for a k value.
- the absorption index k may vary with a range of between about 0.2 to about 1.0, and generally may be between about 0.3 and 1.0 for commercial uses in photolithography.
- the above formula is representative of the n and k characteristics of the SiC of the present invention and can be readily converted for different exposure wavelengths. Beginning at the x-axis value in Figure 8, the slope of the SiC n and k relationship may vary from about 20° to about 60° with the slope shown as about 35°.
- the dielectric constant of the silicon oxynitride ARC is about double that of the SiC and yet the SiC has about the same n and k values. Stated differently, using the SiC of the present invention can approximate the optical qualities of the silicon oxynitride ARC and yet reduce the dielectric constant by about 50%>. In a low K stack of layers, that difference is important.
- Figure 9 is a schematic of a stack of layers using the SiC of the present invention as a barrier layer, an etch stop, and an ARC.
- the dielectric layer 60 has a contact 62, which may be a copper material.
- a barrier layer 64 of SiC having a thickness of about 500 A is deposited over the dielectric layer 60 and over the contact 62.
- a dielectric layer 66 such as an USG layer with a thickness of about 5000 A thick, is deposited over the barrier layer.
- An etch stop 68 again of about 500 A SiC material, is deposited over the dielectric USG layer, followed by another dielectric layer 70, which also may be an USG material having a thickness of about 7000 A.
- an ARC 72 of SiC having a thickness of about 600 A is deposited over the previous USG layer, and is followed by a photoresist layer 74.
- the photoresist is exposed through a mask, the unwanted portions washed away, the layers etched which produces features, and further layers deposited such as liner, barrier, and conductive layers.
- the thicknesses, number of layers, and arrangement could vary and the embodiment is exemplary.
- Figure 10 is a simulation graph of reflectivity contours for projecting reflectivity values of different combinations of layer thicknesses, using a computer simulation program, entitled “The Positive/Negative Resist Optical Lithography Model", v. 4.05.
- the simulation graph is used to predict the substrate reflectivity at incremental rates, resulting is a reflectivity topography that maps the effects on reflectivity of the thickness of one layer to the thickness of an adjacent layer.
- each contour is set to increment by 2% with the lowest being 2% reflectivity and the highest being 16% reflectivity.
- the x-axis is the thickness of the underlying layer, t.e., the dielectric layer 70 in Figure 9.
- the y-axis is the SiC thickness used as an ARC, corresponding to the ARC 72 of Figure 9.
- the goal of obtaining low reflectivity is to minimize the extraneous reflections from the substrate at the photoresist interface between, in this instance, the photoresist layer and the ARC.
- An optimal reflectivity value is 0%, but Applied engineers have learned that a reflectivity of less than about 1% provides commercially acceptable results with a goal of about 5% or less being preferred to insure repeatability of the photolithography processing. While in some embodiments a 10% reflectivity is acceptable, 10% reflectivity is typically a practical limit to the current size and density of features in the substrate.
- the corresponding preferred ARC thickness on the y-axis can be predicted by locating an ARC thickness having less than the chosen reflectivity, such as 5%.
- a dielectric thickness of about 6500 A to about 6750 A shown as range 76 in Figure 10 will predictably need about 200 A of ARC to meet the 5% or less reflectivity criteria.
- the 200 A layer may be insufficient as a barrier layer to copper if, for instance, copper was deposited on the ARC after etching.
- the ARC layer would be sufficient, other properties, such as described above, may need consideration.
- an ARC thickness of more than about 500 A results in less than 5% reflectivity across the range of dielectric layer thickness in the graph.
- the ARC layer thickness can be carefully controlled, then the ARC layer thickness can be varied or minimized. For instance, a dielectric thickness of about 6600 A, plus or minus about 100 A or about 1.5%, can have an ARC thickness of 50 A or more and meet the optical parameters of 5% or less reflectivity.
- the SiC of the present invention satisfies the desire for a multiple purpose material in providing a barrier layer, etch stop, and an ARC and satisfies the desire for a multiple application material in that a single ARC thickness can meet the optical needs of multiple dielectric thicknesses for a given reflectivity.
- a layer with a preferred thickness of about 600 A offers one of the lowest reflectivity values across the entire spectrum of the dielectric layer thicknesses, shown as value 78 in the graph.
- an ARC can be deposited that is substantially independent of the underlying layer thickness.
- the range may be about 500 A to about 1000 A or more, with a preferred thickness of about 600 A, having a predicted reflectivity of about 2% or less, below the preferred 5% range.
- This discovery contrasts with the typical need to adjust the n, k, and t characteristics of the ARC layer to the particular thickness of the underlying layer for each application.
- the ARC layer may simply be a consistent deposition thickness of about 600 A, regardless of the underlying layer thickness.
- the graph may be analyzed for other appropriate ranges, as the particular application may find useful.
- the SiC ARC 72 of the present invention may also be used as a polish stop. After the stack is etched and the features filled with conductive material, some processing methods polish the upper surface of the substrate surface to remove excess conductive material and planarize the upper surface to prepare for the next deposition, if applicable. Typically, the substrate is polished by a chemical mechanical polishing (CMP) process, well known to those in the field. The CMP process uses a difference in polishing rates between different materials to determine the limit of polishing, for instance, as the CMP process encounters a underlying polish resistant layer. With the present invention, the SiC ARC 72 may be used as a polish stop.
- CMP chemical mechanical polishing
- the ARC will typically remain on the substrate and need not be removed to maintain an effective low K substrate.
- conductive material may be deposited over the ARC, filling the features.
- the CMP process then is used to remove any extra conductive material or any other material above the SiC. As the CMP process determines a difference in the polishing rates when the process encounters the SiC ARC, then the CMP process may be discontinued.
- the SiC ARC material may be used as a moisture barrier.
- the CMP process is typically a wet process. Because moisture can corrupt a substrate circuit, some layer needs to be moisture resistant. If, for instance, the SiC ARC is used as a polish stop, then as an upper layer, the SiC ARC would desirably act as a moisture barrier.
- Figure 11 is a line drawing of a scanning electron microscopy photograph, showing a cross section of a patterned photoresist layer 74 deposited over a SiC ARC 72 of the present invention.
- Figure 11 shows the photolithography results of such embodiments as shown in Figure 9, where the ARC is considered the top layer of the substrate prior to the photoresist layer deposition and photolithography processing.
- the width of the line 80 in the photoresist layer 74 is about a quarter micron, representative of the current size of features.
- the patterning in the features was uniform and had straight, square sidewalls 84, i.e., no standing wave effects from extraneous light reflections, with a fully exposed bottom 86 and square corner 88 without a substantial rounded "footing" in the corner.
- the variation in minimum to maximum values of the photoresist width 90 between the lines is 5% or less, a standard acceptance range for processing.
- the repeatability from line to line is also shown.
- the uniformity of the patterned photoresist layer demonstrates that the SiC ARC of the present invention is able to produce a photolithography processed substrate with small features and still retain a low K value, in contrast to other ARC materials, such as the silicon oxynitride ARC, described above.
- Figure 12 shows the FTIR results of a moisture test of the SiC material exposed to boiling water for a 30 minute period.
- the upper line of the moisture results before the exposure is offset from the lower line of the moisture results after the exposure to view both lines on the same graph.
- Tests results show that the SiC of the present invention acts as a moisture barrier throughout the CMP process and thus satisfies the moisture barrier aspect, as well.
- the moisture level is particularly noted at wave number 1640, which is the H-OH peak, where the results are substantially the same, indicating substantially no moisture absorbed.
- Figure 13 is an alternative embodiment of Figure 9, without using a separate ARC, but relying on the properties of the SiC of the present invention between adjacent layers to function as an ARC, i.e., here the etch stop 68 between the dielectric layers 66 and 70.
- the layers and numbers correspond to the arrangement described in Figure 9, with the difference being no ARC 72 under the photoresist layer 74.
- the thickness of the dielectric layer 70 above the SiC etch stop 68 is adjusted in conjunction with the thickness of the SiC etch stop 68 between the dielectric layers 66 and 70 for a projected reflectivity.
- the thickness of the dielectric layer 66 is held constant.
- the photoresist layer 74 would be exposed as described above.
- the barrier layer 64 may be about 500 A.
- the substrate would rely on the reflective and absorptive characteristics of the SiC etch stop 68 below the upper dielectric layer 70.
- the thicknesses of the two layers are interdependent for a given projected reflectivity.
- a proper selection of the SiC etch stop thickness makes this arrangement suitable, as shown in Figure 14.
- Figure 14 is a reflectivity map of the embodiment of Figure 13, showing the thicknesses of the upper dielectric layer 70 compared to the etch stop 68.
- the y-axis is the thickness of the dielectric layer 70 and the x-axis is the thickness of the SiC etch stop 68.
- the axes are reversed from the reflectivity map of Figure 10, because in this embodiment the top layer is the dielectric layer 70.
- the appropriate thicknesses may be selected for given reflectivity ratios, such as below about 5%. For example, an etch stop thickness of about 150 A, plus or minus 50 A, would optically satisfy the requirements for all the graphed thicknesses in Figure 14 of the dielectric layer 70 and would have a reflectivity of less than about 5%.
- a 150 A SiC layer would be undesirably thin to also function as a copper barrier layer.
- Factors, such as control factors in etch processing, or barrier properties may ultimately determine the proper thickness for an etch stop and whether alternative thicknesses for the optical properties of an anti-reflective coating are needed.
- a SiC etch stop of about 720 A thick could be used with a top dielectric layer thickness of about 6500 A or about 7300 A. Because the reflectivity pattern repeats in this zone, other layer thicknesses not charted could be used and the thicknesses shown in Figure 14 and other similar figures are typical of the thicknesses used in commercial embodiments. If a higher level of reflectivity were allowed, for instance 6%, then an etch stop thickness of about 720 A would also satisfy the optical requirements for reflectivity for all the graphed thicknesses on Figure 14.
- a dielectric thickness of about 6600 A and about 7400 A with close tolerances could allow an etch stop thickness of about 100 A to about 350 A with a reflectivity of about 5% or less.
- Other values may be determined, using the contours of the figures.
- these examples show that the thickness of the etch stop and the thickness of the dielectric layer adjacent the etch stop are to be considered with respect to each other when the SiC, functioning as an ARC, is between the dielectrics for a projected or chosen reflectivity.
- Figure 15 is another reflectivity map of the embodiment of Figure 13, showing the thickness of the etch stop compared to the thickness of the lower dielectric layer under the etch stop, where the dielectric layer 66 below the etch stop 68 is adjusted in conjunction with the thickness of the etch stop 68 for a projected reflectivity.
- the dielectric layer 70 may remain a certain thickness, such as 7000 A, while the thicknesses of the etch stop 68 and dielectric layer 66 are determined for a particular reflectivity.
- the etch stop 68 is the upper layer relative to the dielectric layer 66
- the etch stop thickness is represented on the y-axis and the dielectric layer 66 thickness is represented on the x-axis.
- the thickness of the dielectric layer 66 could be about 4600 A or about 5400 A to maintain a 5% or less reflectivity.
- the thickness of the dielectric layer 66 may change for a different thickness of the dielectric layer 70.
- iterative solutions may be required to find a thickness for each dielectric layer that meets the various process requirements and still collectively satisfy a reflectivity goal, here of about 5% or less.
- Figure 16 is an alternative embodiment of Figures 9 and 13 without the etch stop, where the barrier layer 64 is used as the ARC.
- the upper layer ARC 72 of the embodiment of Figure 9 may not be used, as shown in Figure 13.
- the etch stop 68 of Figure 13 may also not be used, as shown in Figure 16. If the etch stop can be eliminated, then the substrate processing throughput may be increased with fewer steps and a lower effective dielectric constant of the substrate may be obtained.
- the difficulty with eliminating the etch stop is the repeatability of the etching process and the timing of the etching so that undesired etching through typically the dielectric layer(s) does not occur. However, if the process is well characterized and has sufficient control, then the etch stop may not be used.
- the layers and numbers correspond to the arrangement described in Figures 9 and 13, with the difference being no ARC 72 under the photoresist 74 and no etch stop 68.
- the thickness of the dielectric layer 66 is increased to compensate for the lack of the second dielectric layer 70 so that the circuit is electrically isolated and may be about 10,000 A to about 12,000 A thick.
- the dielectric layer 66 thickness is adjusted in conjunction with the thickness of the SiC barrier layer 64 between the dielectric layer 66 and the dielectric layer 60 for a projected reflectivity.
- the photoresist 74 would be exposed as described above.
- the substrate would rely on the reflective and absorptive characteristics of the SiC barrier layer 64 below the dielectric layer 66, where the thicknesses of the two layers are interdependent or independent, contingent upon the thickness(es) selected and the desired reflectivity.
- a proper selection of the SiC barrier layer thickness makes this arrangement suitable, as shown in Figure 17.
- Figure 17 is a reflectivity map of the embodiment of Figure 16, showing the thicknesses of the dielectric layer 66 compared to the SiC barrier layer 64, using the barrier layer as an ARC.
- the y-axis represents the dielectric layer thickness and the x-axis represents the barrier layer thickness. Because other parameters may be considered, such as the ability of the dielectric layer to electrically isolate the circuit, the dielectric layer thickness may be first selected and the barrier layer thickness determined from the graph for a given reflectivity.
- a preferred thickness of the SiC barrier layer when used as an ARC, in this embodiment without the intervening etch stop, is about 700 to about 800 A.
- the SiC of the present invention provides ARC optical results substantially independent of the dielectric layer thickness.
- Figure 18 is another embodiment similar to the embodiment of Figure 16 with the addition of a SiC ARC 72 below the photoresist layer 74.
- the etch stop 68 of Figure 9 is not used in the embodiment of Figure 18 and the dielectric layer 66 is typically thicker than the separate dielectric layers of Figure 9.
- the SiC barrier layer 64 is about 500 A thick, although the thickness could vary.
- the thickness of the dielectric layer 66 can vary without significantly affecting the reflectivity on the photoresist layer 74, when the SiC ARC 72 thickness is appropriately selected.
- a typical thickness of the dielectric layer 66 may be about 10,000 A to about 12,000 A.
- Figure 19 is a reflectivity map of the embodiment of Figure 18, showing the thickness of the ARC compared to the thickness of the dielectric layer under the ARC for a projected reflectivity.
- the ARC 72 thickness is represented on the x-axis and the dielectric layer 66 thickness is represented on the y-axis.
- the reflectivity map shows that with an ARC thickness of about 520 A or greater, any of the graphed thickness of the dielectric layer 66 may result in a reflectivity of about 5% or less.
- a preferred thickness of the SiC ARC is about 600 A.
- the pattern repeats, as in other reflectivity maps, and thus other thicknesses of the oxide and/or SiC layer could be determined by extrapolation.
- an ARC can be deposited that is substantially independent of the adjoining layer thickness, for a particular projected reflectivity.
- the ARC layer may be a deposition thickness of about 600 A, regardless of the underlying layer thickness to obtain a projected reflectivity of about 5% or less.
- the graph may be analyzed for other appropriate ranges, as the particular application may find useful.
- Figure 20 shows the test specimen diffusion results, where the lower curve shows the copper content, showing the diffusion resistance to copper of the SiC ARC material of the present invention.
- the test specimen was a substrate with a 200 A layer of copper, a 800 A layer of SiC deposited on the copper, and a 1000 A layer of oxide deposited on the SiC. Starting with the y-axis, Figure 20 shows a value 46 of approximately 3 x 10 17 atoms per cubic centimeter (atoms/cc) at a depth of 0 A from the surface of the 1000 A oxide layer.
- This value reduces to value 48 of about 1 x 10 16 atoms/cc through the oxide layer and into the 800 A SiC layer at a combined depth of about 1570 A, before the copper diffusion becomes noticeable.
- the copper diffusion level then rises logarithmically for the next 230 A to a value 50 of approximately 3 x 10 21 atoms/cc at the copper to copper barrier interface.
- the level of copper reduces by approximately four orders of magnitude, i.e., 1/10,000, within about 200 A to 250 A of the interface. This decrease in copper diffusion shows the effectiveness of the SiC material of the present invention.
- the present invention further provides a substrate processing system having a plasma reactor including a chamber, a reaction zone in the chamber, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system.
- the processing system further comprises a gas/liquid distribution system connecting the reaction zone of the vacuum chamber that supplies an silane-based compound, an inert gas, and an RF generator coupled to the gas distribution system for generating a plasma in the reaction zone.
- the processing system further includes a controller comprising a computer for controlling the plasma reactor, the gas distribution system, the RF generator, and a memory coupled to the controller, the memory comprising a computer usable medium including a computer readable program code for selecting the process steps for depositing a low dielectric constant film with a plasma of an silane-based compound.
- the processing system may further comprise in one embodiment computer readable program code for selecting the process steps for depositing a barrier layer and/or etch stop of the silane-based compound, depositing a different dielectric layer, and optionally depositing a capping passivation layer of the silane-based compound.
Abstract
Description
Claims
Priority Applications (2)
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EP99949892A EP1118025A2 (en) | 1998-10-01 | 1999-09-27 | Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method |
JP2000574964A JP4763131B2 (en) | 1998-10-01 | 1999-09-27 | Silicon carbide deposition for low dielectric constant antireflective coatings |
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US09/165,248 | 1998-10-01 | ||
US09/165,248 US20030089992A1 (en) | 1998-10-01 | 1998-10-01 | Silicon carbide deposition for use as a barrier layer and an etch stop |
US09/219,945 US6635583B2 (en) | 1998-10-01 | 1998-12-23 | Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating |
US09/219,945 | 1998-12-23 | ||
US09/270,039 | 1999-03-16 | ||
US09/270,039 US6974766B1 (en) | 1998-10-01 | 1999-03-16 | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
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PCT/US1999/022424 WO2000019498A1 (en) | 1998-10-01 | 1999-09-27 | In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications |
PCT/US1999/022425 WO2000019508A1 (en) | 1998-10-01 | 1999-09-27 | Silicon carbide deposition method and use as a barrier layer and passivation layer |
PCT/US1999/022317 WO2000020900A2 (en) | 1998-10-01 | 1999-09-27 | Silicon carbide for use as a low dielectric constant anti-reflective coating and its deposition method |
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PCT/US1999/022425 WO2000019508A1 (en) | 1998-10-01 | 1999-09-27 | Silicon carbide deposition method and use as a barrier layer and passivation layer |
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EP (3) | EP1118107A1 (en) |
JP (2) | JP2002526649A (en) |
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Also Published As
Publication number | Publication date |
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EP1118107A1 (en) | 2001-07-25 |
TW523803B (en) | 2003-03-11 |
KR20010075563A (en) | 2001-08-09 |
KR100650226B1 (en) | 2006-11-24 |
KR100716622B1 (en) | 2007-05-09 |
JP2002526649A (en) | 2002-08-20 |
US20060089007A1 (en) | 2006-04-27 |
US20090130837A1 (en) | 2009-05-21 |
WO2000019508A1 (en) | 2000-04-06 |
JP2002526916A (en) | 2002-08-20 |
EP1118025A2 (en) | 2001-07-25 |
WO2000019498A1 (en) | 2000-04-06 |
TW432476B (en) | 2001-05-01 |
KR20010079973A (en) | 2001-08-22 |
WO2000020900A3 (en) | 2000-09-08 |
US6974766B1 (en) | 2005-12-13 |
KR100696034B1 (en) | 2007-03-16 |
TW492138B (en) | 2002-06-21 |
EP1118109A1 (en) | 2001-07-25 |
KR20070005025A (en) | 2007-01-09 |
US7670945B2 (en) | 2010-03-02 |
US7470611B2 (en) | 2008-12-30 |
KR20010075561A (en) | 2001-08-09 |
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