WO2000007236A2 - Method and apparatus for forming improved metal interconnects - Google Patents
Method and apparatus for forming improved metal interconnects Download PDFInfo
- Publication number
- WO2000007236A2 WO2000007236A2 PCT/US1999/016887 US9916887W WO0007236A2 WO 2000007236 A2 WO2000007236 A2 WO 2000007236A2 US 9916887 W US9916887 W US 9916887W WO 0007236 A2 WO0007236 A2 WO 0007236A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- copper
- barrier layer
- dielectric layer
- depositing
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 118
- 239000002184 metal Substances 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 269
- 229910052802 copper Inorganic materials 0.000 claims abstract description 239
- 239000010949 copper Substances 0.000 claims abstract description 239
- 230000004888 barrier function Effects 0.000 claims abstract description 200
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims abstract description 91
- 239000005751 Copper oxide Substances 0.000 claims abstract description 91
- 229910000431 copper oxide Inorganic materials 0.000 claims abstract description 91
- 238000000992 sputter etching Methods 0.000 claims abstract description 57
- 238000000151 deposition Methods 0.000 claims description 160
- 235000012431 wafers Nutrition 0.000 claims description 115
- 230000008021 deposition Effects 0.000 claims description 90
- 238000012545 processing Methods 0.000 claims description 84
- 238000004544 sputter deposition Methods 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 44
- 230000015572 biosynthetic process Effects 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000012546 transfer Methods 0.000 claims description 23
- -1 tungsten nitride Chemical class 0.000 claims description 19
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- 239000010937 tungsten Substances 0.000 claims description 18
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052715 tantalum Inorganic materials 0.000 claims description 16
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 302
- 239000011229 interlayer Substances 0.000 abstract description 52
- 229960004643 cupric oxide Drugs 0.000 description 58
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 24
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 20
- 229910052786 argon Inorganic materials 0.000 description 16
- 238000005240 physical vapour deposition Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 239000001301 oxygen Substances 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000002294 plasma sputter deposition Methods 0.000 description 6
- 230000002939 deleterious effect Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000005477 sputtering target Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000593 degrading effect Effects 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to semiconductor device metal layer interconnects and more particularly to reducing the contact resistance of interconnects .
- a typical integrated circuit contains a plurality of metal pathways to provide electrical power for powering the various semiconductor devices comprising the integrated circuit, and to allow these semiconductor devices to share/exchange electrical information.
- metal layers are stacked on top of one another by using intermetal or "interlayer" dielectrics that insulate the metal layers from each other.
- intermetal or "interlayer” dielectrics that insulate the metal layers from each other.
- each metal layer must form electrical contact to an additional metal layer.
- Metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the first and second metal layers, and by filling the resulting hole or via with a metal to create an interconnect as described further below.
- copper in place of aluminum as the interconnect material for semiconductor devices has grown in popularity due to copper's lower resistivity. Unlike aluminum, however, copper is highly mobile in silicon dioxide and may, as a result of infiltration of copper atoms into the dielectric, create leakage paths through a device's various dielectric layers . Copper atoms also can cause electrical defects in silicon. Accordingly, as best understood with reference to FIGS. 1A-1C described below, a semiconductor device employing copper interconnects requires the creation of encapsulating barrier layers to prevent deleterious incorporation of copper atoms into the device's various material layers .
- FIGS. 1A-C show sequential cross-sectional views of the formation of a conventional copper interconnect 10 (FIG. 1C) through an aperture in a dielectric layer disposed between two copper layers, a first copper layer 11a disposed within a dielectric layer D and a second copper layer lib.
- a silicon dioxide interlayer dielectric 13 is deposited over the first copper layer 11a.
- a first via 15 then is etched in the interlayer dielectric 13 to expose the first copper layer 11a.
- Copper is highly reactive with oxygen and easily forms a surface layer of high resistivity copper oxide when exposed to an oxygen rich atmosphere. Because the first layer 11a is copper, a high resistance copper oxide layer 11a' can form on the top surface of the first copper layer 11a if the first copper layer 11a is exposed to oxygen or water vapor (e.g., air) . This oxidation can occur when the wafers, just having the vias etched therein, are moved from an etch tool to a metallization tool. The copper oxide layer 11a will complete formation once all exposed and unoxidized copper is converted to copper oxide. Accordingly, to minimize the resistance of the copper interconnect 10, the copper oxide layer 11a' must be removed.
- the copper oxide layer 11a' is removed by sputtering the copper oxide layer 11a' with ions generated within a plasma (i.e., sputter-etching), such as argon ions generated within an argon plasma.
- a plasma i.e., sputter-etching
- the argon ions are accelerated toward the wafer via a negative electric bias imposed on the wafer or on the wafer support .
- These ions strike the wafer and the copper oxide layer 11a' at the base of the unfilled via, and eject material from the copper oxide layer 11a' (including copper immediately beneath the copper oxide) due to momentum transfer between the accelerated argon ions and the copper oxide layer 11a' .
- the ejected material which includes copper atoms 11a'', coats the interlayer dielectric 13 as shown in FIG. 1A.
- the copper atoms 11a' ' contained in the ejected material can enter the interlayer dielectric 13 and drift therethrough under the influence of an applied electric field (e.g., a device voltage), causing deleterious interconnect-to-interconnect leakage currents (i.e., via-to- via leakage currents) .
- an applied electric field e.g., a device voltage
- Such deleterious via-to-via leakage currents cannot be avoided in conventional copper interconnects if the copper oxide layer 11a' is removed.
- conventional copper interconnects suffer from either a high resistance copper oxide layer 11a' which is left in place to prevent dielectric degradation induced by copper sputtered directly on the wall of the unfilled via, or copper atom induced degradation in the dielectric which leads to via-to-via leakage currents .
- a thin barrier layer 17 e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride
- the barrier layer 17 prevents copper atoms from a subsequently deposited copper layer (namely the second copper layer lib of FIG. 1C) from incorporating into, and thus degrading, the interlayer dielectric 13.
- the second copper layer lib is deposited over the barrier layer 17 either conformally or in the form of a copper plug lib', as shown in FIG. 1C.
- a copper "seed” layer (not shown) typically is deposited prior to deposition of the copper plug lib' .
- a conventional copper interconnect 10 consists of the first copper layer 11a "in contact” with the second copper layer lib through the barrier layer 17.
- the barrier layer 17 can have a resistivity up to 100 times greater than the resistivity of copper, the barrier layer 17 significantly increases the contact resistance of the interconnect 10 formed between the first copper layer 11a and the second copper layer lib. Therefore, the significant advantage of copper's lower resistivity is not fully realized due to the presence of barrier layers.
- the barrier layer 17, however, is required to prevent further incorporation of copper atoms within the interlayer dielectric 13.
- conventional copper interconnects suffer from high resistances due to the presence of barrier layers, and can suffer from via-to-via leakage currents due to sputtered copper atom incorporation in the interlayer dielectric 13 during interconnect formation. Accordingly, a need exists for an improved copper interconnect that does not suffer from either high resistance or via-to-via leakage currents .
- the present invention provides an inventive copper interconnect free from copper atom via-to-via leakage current paths and preferably having a significantly reduced resistance.
- a barrier layer e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride
- a barrier layer at the bottom of the interlayer dielectric's via, and the copper oxide layer thereunder, are sputter- etched.
- the barrier layer is deposited prior to sputter-etching, during sputter-etching copper atoms from the copper oxide layer redistribute on the barrier layer rather than on the interlayer dielectric.
- the copper atoms are not mobile within the barrier layer, and are prevented from diffusing to and contaminating the interlayer dielectric. Accordingly, no via-to-via leakage current paths are created during copper interconnection formation.
- the second copper layer is deposited over the barrier layer and the exposed first copper layer to complete copper interconnect formation. Because the first and second copper layers are in direct contact, the high resistivity of the barrier layer is eliminated. Accordingly, the inventive copper interconnect has low resistance in addition to no via-to-via leakage current paths .
- a capping dielectric barrier layer (e.g., silicon nitride) is deposited over the first copper layer prior to interlayer dielectric formation.
- the capping dielectric barrier layer is deposited before the first copper layer is exposed to oxygen (e.g., air) to prevent copper oxide formation on the first copper layer.
- oxygen e.g., air
- the capping dielectric barrier layer and any copper oxide formed on the first copper layer are sputter-etched. Because the capping dielectric barrier layer is sputter-etched first, it is redistributed on the sidewalls of the interlayer dielectric and serves as a diffusion barrier to any copper atoms (from the underlying copper oxide layer) that may redistribute on the sidewalls during sputter-etching.
- the redistributed capping dielectric barrier layer material thus prevents copper atoms from entering the interlayer dielectric and creating via-to- via current leakage paths therein.
- the copper interconnect is completed by depositing a barrier layer over the exposed first copper layer, and by depositing a second copper layer over the barrier layer.
- the presence of the barrier layer between the first and second copper layers increases the copper interconnect ' s resistance.
- the copper interconnect does not suffer from via-to-via leakage currents.
- the capping dielectric barrier layer may be used advantageously as an etch stop layer if so desired.
- a third aspect of the invention also employs the capping dielectric barrier layer.
- the barrier layer is deposited on the capping dielectric barrier layer and on the interlayer dielectric prior to sputter-etching. Thereafter, the barrier layer, the capping dielectric barrier layer, and any copper oxide formed on the first copper layer are etched, and the second copper layer is deposited directly on the exposed first copper layer, making direct contact therebetween.
- the inventive copper interconnect has low resistance.
- the capping dielectric barrier layer of the third aspect may serve as an etch stop layer and preferably is deposited prior to exposing the first copper layer to oxygen.
- the deposition of the barrier layer on the sidewalls of the interlayer dielectric is performed "simultaneously" with either the sputter-etching of the copper oxide layer (first aspect) or the capping dielectric barrier layer and the copper oxide layer (third aspect) .
- Simultaneous deposition/sputter-etching may be performed within a high density plasma (HDP) sputtering chamber by adjusting the chamber's RF coil power and RF wafer bias to achieve the desired deposition/sputter-etching ratio.
- HDP high density plasma
- deposition of the barrier layer and sputter-etching of the copper oxide layer and the capping dielectric barrier layer may be performed "sequentially" within the same chamber or by depositing the barrier layer within a first processing chamber (e.g., an HDP chamber) and by sputter-etching any copper oxide layer and any capping dielectric barrier layer within a separate processing chamber (e.g., a sputter- etching chamber such as Applied Materials' Preclean II chamber) .
- a first processing chamber e.g., an HDP chamber
- a separate processing chamber e.g., a sputter- etching chamber such as Applied Materials' Preclean II chamber
- deposition of the second copper layer preferably is performed prior to breaking vacuum so as to maintain a copper-oxide free interface between the first and second copper layers .
- FIGS. 1A-C are sequential cross sectional views of the formation of a conventional copper interconnect as previously described;
- FIG. 2 is a diagrammatic illustration, in section, of the pertinent portions of an high density plasma sputtering chamber for practicing the present invention
- FIGS. 3A-C are sequential cross sectional views of the formation of a copper interconnect in accordance with a first aspect of the present invention
- FIGS. 4A-D are sequential cross sectional views of the formation of a copper interconnect in accordance with a second aspect of the present invention.
- FIGS. 5A-C are sequential cross sectional views of the formation of a copper interconnect in accordance with a third aspect of the present invention.
- FIG. 6 is a top plan view of an automated semiconductor manufacturing tool useful for performing the inventive methods
- FIG. 7 is a flowchart of the operation, in pertinent part, of the automated semiconductor manufacturing tool of FIG. 6 as controlled by a controller during the formation of the inventive interconnects of FIGS. 3A-5C;
- FIG. 8 is a flow chart of a first interconnect subroutine of the flow chart of FIG. 7;
- FIG. 9 is a flow chart of a second interconnect subroutine of the flow chart of FIG. 7.
- FIG. 10 is a flow chart of a third interconnect subroutine of the flow chart of FIG. 7.
- copper interconnect formation is performed primarily within a high density plasma sputtering chamber (although interconnect vias may be filled by a process for filling vias, such as chemical vapor deposition (CVD) , physical vapor deposition (PVD) or electroplating as is known in the art) . Accordingly, before discussing the preferred aspects for copper interconnect formation, the operation of such a high density plasma sputtering chamber is described briefly with reference to FIG. 2.
- FIG. 2 is a side diagrammatic illustration, in section, of the pertinent portions of a high density plasma sputtering chamber 21 for practicing the present invention.
- the sputtering chamber 21 contains a wire coil 23 which is operatively coupled to a first RF power supply 25.
- the wire coil 23 may comprise a plurality of coils, a single turn coil as shown in FIG. 2, a single turn material strip, or any other similar configuration. As shown in FIG. 2, the wire coil 23 is positioned along the inner surface of the sputtering chamber 21, between a sputtering target 27 and a substrate support pedestal 29.
- the substrate support pedestal 29 is positioned in the lower portion of the sputtering chamber 21 and the sputtering target 27 is mounted in the upper portion of the sputtering chamber 21 and facing the substrate receiving surface of the support.
- the sputtering chamber 21 generally includes a vacuum chamber enclosure wall 31 having at least one gas inlet 33 and having an exhaust outlet 35 operatively coupled to an exhaust pump 37.
- the sputtering target 27 and the substrate support pedestal 29 are electrically isolated from the enclosure wall 31.
- the enclosure wall 31 preferably is grounded so that a negative voltage (with respect to grounded enclosure wall 31) may be applied to the sputtering target 27 via a DC power supply 39 operatively coupled between the target 27 and the enclosure wall 31, and a negative bias may be applied to the substrate support pedestal 29 via a second RF power supply 41 operatively coupled between the pedestal 29 and ground.
- a controller 42 is operatively coupled to the first RF power supply 25, the DC power supply 39, the second RF power supply 41, the gas inlet 33 and the exhaust outlet 35.
- a tantalum target 27 is employed.
- both argon and nitrogen gas are flowed into the sputtering chamber 21 through the gas inlet 33 (multiple inlets, one for each gas, may be used) , while a power signal is applied to the coil 23 via the first RF power supply 25, and a power signal is applied to the target 27 via the DC power supply 39.
- nitrogen may react with the tantalum target 27 to form a nitride film on the tantalum target 27 so that tantalum nitride is sputtered therefrom.
- non-nitrided tantalum atoms are also sputtered from the target, which atoms can combine with nitrogen to form tantalum nitride in flight or on a wafer (not shown) supported by the pedestal 29.
- a throttle valve (not shown) operatively coupled to the exhaust outlet 35 is placed in a mid-position in order to maintain the deposition chamber 21 at a desired low vacuum level of about lxlO "8 torr prior to introduction of the process gas(es) into the chamber.
- a mixture of argon and nitrogen gas is flowed into the sputtering chamber 21 via the gas inlet 33.
- DC power is applied to the tantalum target 27 via the DC power supply 39 and an RF power signal is applied to the coil 23 via the first RF power supply 25 (while the gas mixture continues to flow into the sputtering chamber 21 via the gas inlet 33 and is pumped therefrom via the pump 37) .
- the DC power applied to the target 27 and coil 23 causes the argon/nitrogen gas mixture to form a plasma and to generate argon and nitrogen ions which are attracted to, and strike the target 27 causing target material (e.g., tantalum and tantalum nitride) to be ejected therefrom.
- target material e.g., tantalum and tantalum nitride
- a negative bias can be created between the substrate support pedestal 29 and the plasma.
- the negative bias between the substrate support pedestal 29 and the plasma causes argon ions to accelerate toward the pedestal 29 and any wafer supported thereon. Accordingly, a wafer may be sputter-etched by the argon ions at the same time the tantalum nitride material from the target 27 deposits on the wafer (i.e., simultaneous deposition/sputter-etching), as is well known in the art.
- simultaneous deposition/sputter-etching within the chamber 21 may be advantageously employed for the inventive copper interconnect formation methods disclosed herein, as described below.
- FIGS. 3A-C show sequential cross-sectional views of the formation of a first copper interconnect 43 (FIG. 3C) in accordance with a first aspect of the present invention.
- an interlayer dielectric 45 e.g., silicon dioxide
- a first metal layer e.g., a first copper layer 47a
- a via 49 then is etched in the interlayer dielectric 45 to expose the first copper layer 47a.
- the first metal layer may be deposited using CVD, PVD, electroplating or other such well known metal deposition techniques, and it is connected, via contacts, through a dielectric layer, to devices formed in the underlying semiconductor wafer. If the first copper layer 47a is exposed to oxygen, such as when the wafer is moved from an etching chamber in which the oxide overlaying the first copper layer is etched to create apertures for creation of vias between the first copper layer and a second to be deposited metal layer, it will readily form an insulating/high resistance copper oxide layer 47a' thereon. Accordingly, to reduce the resistance of the copper interconnect 43, any copper oxide layer 47a' and any processing residue within the via 49 must be removed.
- a barrier layer 51 is deposited (e.g., within the sputtering chamber 21 of FIG. 2) over the interlayer dielectric 45 and over the exposed first copper layer 47a prior to removing the copper oxide layer 47a' .
- the barrier layer 51 preferably comprising tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride prevents subsequently deposited copper layers from incorporating in and degrading the interlayer dielectric 45 (as previously described) .
- the portion of the barrier layer 51 at the bottom of the via 49, and the copper oxide layer 47a' (and any processing residue) thereunder are sputter-etched via an argon plasma.
- the power applied to the target 27 is either removed or is reduced to a low level (e.g., 500 W) so as to prevent significant deposition.
- a low target power level rather than no target power, results in a more uniform plasma and is presently preferred.
- Argon ions are accelerated toward the barrier layer 51 via an electric field (e.g., the RF signal applied to the substrate support pedestal 29 via the second RF power supply 41 of FIG. 2 which causes a negative self bias to form on the pedestal) , strike the barrier layer 51, and, due to momentum transfer, sputter the barrier layer material from the base of the via aperture and redistribute it along the portion of the barrier layer 51 that coats the sidewalls of the via 49.
- the argon ions are attracted to the substrate in a direction substantially perpendicular thereto. As a result, little sputtering of the via sidewall, but substantial sputtering of the via base, occurs.
- the argon ions strike the copper oxide layer 47a' , and the oxide layer is sputtered to redistribute the copper oxide layer material from the via base, some or all of the sputtered material being deposited along the portion of the barrier layer 51 that coats the sidewalls of the via 49.
- Copper atoms 47a'' as well, coat the barrier layer 51 disposed on the sidewalls of the via 49.
- the copper atoms 47a' ' are immobile within the barrier layer 51 and cannot reach the interlayer dielectric 45.
- the copper atoms 47a' ' which are deposited onto the sidewall, therefore, do not generate via-to-via leakage currents as they would were they redistributed onto an uncoated sidewall.
- a second copper layer 47b is deposited (either conformally or so as to form a copper plug 47b' as shown in FIG. 3C) over the barrier layer 51 and over the portion of the first copper layer 47a exposed at the base of each via. Because the first and second copper layers 47a, 47b are in direct contact, rather than in contact through the barrier layer 51 as in conventional copper interconnects, the resistance of the copper interconnect 43 is much lower than that of conventional copper interconnects (in addition to the interconnect' s freedom from via-to-via leakage currents).
- deposition of the barrier layer 51 on the sidewalls of the via 49 and sputter-etching of the barrier layer 51 and the copper oxide layer 47a' at the bottom of the via 49 occur simultaneously.
- Simultaneous deposition/sputter-etching may be performed with the chamber 21 of FIG. 2 by adjusting the power signals applied to the wire coil 23, the target 27 and the pedestal 29, as previously described. Because the coil 23 can be used to maintain the plasma, the plasma can sputter a wafer with a low relative bias on the wafer (less than that needed to sustain the plasma) .
- the ratio of the RF power applied to the wire coil 23 ( “RF coil power”) as compared to the DC power applied to the target 27 (“DC target power”) dictates the relationship between sputter- etching and deposition. For instance, the higher the RF:DC power ratio the more sputtering will occur due to increased ionization and subsequent increased ion bombardment flux to the wafer.
- Increasing the wafer bias e.g., increasing the RF power supplied to the support pedestal 29
- both the voltage level and the duty cycle of the wafer bias can be adjusted to control sputtering rate.
- keeping the DC target power low will decrease the amount of barrier material available for deposition.
- a DC target power of zero will result in sputter-etching only.
- a low DC target power coupled with a high RF coil power and wafer bias will result in simultaneous via sidewall deposition and via bottom sputtering. Accordingly, the process must be tailored for the material and geometries in question.
- a DC target power of 500W to lkW, at an RF coil power of 2 to 3kW or greater, with a wafer bias of 250W to 400W or greater applied continuously (e.g., 100% duty cycle) will result in barrier deposition on the wafer sidewalls and removal of material from the via bottom.
- a 2 kW RF coil power level on the wire coil 23 and a 250 W RF wafer power level with 100% duty cycle on the pedestal 29 presently are preferred for simultaneous deposition/sputter-etching in connection with the first and third aspects (described below) of the present invention. It may be desirable to initially (e.g., for several seconds or more depending on the particular geometries/materials in question) apply no wafer bias during simultaneous deposition/sputter-etching to allow sufficient via sidewall coverage to prevent contamination of the sidewalls by material sputter-etched from the via bottom.
- initially applying no wafer bias during simultaneous deposition/sputter-etching of the via 49 ensures formation of an initial barrier layer on the sidewalls of the interlayer dielectric 45 that prevents sputtered copper atoms from contaminating the interlayer dielectric 45 during the remainder of the deposition/sputter-etching operation.
- deposition/sputter-etching may be performed "sequentially" within the same chamber or by depositing the barrier layer 51 within a first processing chamber and by sputter-etching the barrier layer 51 and copper oxide layer 47a' within a separate, second processing chamber (e.g., a sputter-etching chamber such as Applied Materials' Preclean II chamber).
- a separate, second processing chamber e.g., a sputter-etching chamber such as Applied Materials' Preclean II chamber.
- FIGS. 4A-D show sequential cross-sectional views of the formation of a second copper interconnect 53 (FIG. 4D) in accordance with a second aspect of the present invention.
- a capping dielectric barrier layer e.g., a silicon nitride layer 55
- first metal layer e.g., a first copper layer 57a
- the thickness of the silicon nitride layer 55 is selected to be compatible with chemical mechanical polishing processes while providing adequate barrier performance (e.g., 50 to 1000 Angstroms, more preferably 150 to 500 Angstroms, and most preferably 250-300 Angstroms) .
- first copper layer 57a is exposed to oxygen prior to depositing the silicon nitride layer 55, a copper oxide layer 57a' will form on the first copper layer 57a as shown in FIG. 4A (e.g., during dielectric deposition of dielectric layer D (FIG. 4A) , during etch of the dielectric layer D, during copper deposition and/or etch back to form the first copper layer 57a, or during chemical metal polish of the dielectric layer D) .
- the silicon nitride layer 55 preferably is deposited over the first copper layer 57a prior to exposing the first copper layer 57a to oxygen (e.g., within an automated vacuum wafer processing system which provides wafer transfer between processing chambers within a vacuum environment) so as to avoid formation of the copper oxide layer 57a' .
- oxygen e.g., within an automated vacuum wafer processing system which provides wafer transfer between processing chambers within a vacuum environment
- a thin native copper oxide layer forms on the first copper layer 57a.
- depositing the silicon nitride layer 55 shortly thereafter prevents further oxidation.
- An interlayer dielectric 59 is deposited over the silicon nitride layer 55, and a via 59' is etched in the interlayer dielectric 59 so as to expose the silicon nitride layer 55. But, if the first copper layer 57a is exposed to oxygen before the silicon nitride layer 55 is deposited, the inventive method will nonetheless avoid the deleterious effects of the copper oxide, as previously described.
- the silicon nitride layer 55 also serves to prevent the diffusion of copper atoms from the first copper layer 57a into the interlayer dielectric 59 during formation and patterning of the interlayer dielectric 59.
- the silicon nitride layer 55 (e.g., a high resistance layer), any copper oxide layer 57a' and any processing residue (e.g., left during the formation of the via 59') are sputter-etched via an argon plasma (as previously described) .
- silicon nitride layer 55 is sputter-etched, silicon nitride layer material is redistributed along the sidewalls of the via 59', forming a redistributed nitride layer 55' thereon.
- copper oxide layer material including copper atoms 57a'', redistributes along the sidewalls of the via 59' on top of the redistributed nitride layer 55'. Because copper atoms do not diffuse within silicon nitride, the copper atoms 57a' ' are immobile within the redistributed nitride layer 55'. Accordingly, the copper atoms 57a' ' cannot diffuse to the interlayer dielectric 59 and therefore cannot create via-to-via leakage currents.
- the copper interconnect 53 is completed by depositing a barrier layer 61 over the interlayer dielectric 59 and over the first copper layer 57a (exposed by sputter- etching the silicon nitride layer 55 and the copper oxide layer 57a' ) (FIG. 4C) , and by depositing a second copper layer 57b (either conformally or so as to form a copper plug 57b') over the barrier layer 61 (FIG. 4D) .
- the copper interconnect 53 of FIG. 4D has a higher resistance than the copper interconnect 43 of FIG. 3C. However, like the copper interconnect 43 of FIG. 3C, the copper interconnect 53 of FIG. 4D does not suffer from the via-to-via leakage currents present in conventional copper interconnects. Additionally, if so desired, the silicon nitride layer 55 may be used as an etch stop when selectively removing the interlayer dielectric 59, such as during the formation of the via 59 ' .
- FIGS. 5A-C show sequential cross-sectional views of the formation of a third copper interconnect 63 (FIG. 5C) in accordance with a third aspect of the present invention.
- a capping dielectric barrier layer e.g., a silicon nitride layer 65
- a first metal layer e.g., a first copper layer 67a. If the first copper layer 67a is exposed to oxygen prior to depositing the silicon nitride layer 65, a copper oxide layer 67a' will form on the first copper layer 67a as shown in FIG. 5A.
- the silicon nitride layer 65 preferably is deposited over the first copper layer 67a prior to exposing the first copper layer 67a to oxygen (e.g., without removing the wafer from the vacuum environment) so as to avoid formation of the copper oxide layer 67a' .
- An interlayer dielectric 69 is deposited over the silicon nitride layer 65, and a via 69' is formed in the interlayer dielectric 69 to expose the silicon nitride layer 65.
- a barrier layer 71 e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride
- a barrier layer 71 is deposited over the interlayer dielectric 69 and the exposed silicon nitride layer 65 so as to prevent subsequently deposited copper layers from incorporating in and degrading the interlayer dielectric 69.
- the barrier layer 71, the silicon nitride layer 65, and any copper oxide layer 67a' which may have formed, are sputter-etched (FIG. 5B) via an argon plasma as previously described.
- the barrier layer 71, the silicon nitride layer 65, and any copper oxide layer 67a' are sputter-etched, material from each layer is redistributed along the sidewalls of the via 69'.
- Copper atoms 67a'' which are sputter-etched from the copper oxide layer 67a' , deposit on the barrier layer 71 and the redistributed silicon nitride material that coats the sidewalls of the via 69'. Because both the barrier layer 71 and the silicon nitride layer 65 are diffusion barriers to copper atoms, the copper atoms 67a' ' cannot reach the interlayer dielectric 69, and do not generate via-to-via leakage currents.
- the copper interconnect 63 is completed by depositing a second copper layer 67b (either conformally or so as to form a copper plug 67b' ) over the barrier layer 71 and the exposed first copper layer 67a. Because the first and second metal layers 67a, 67b are in direct contact, the copper interconnect 63 has a much lower resistance than the conventional copper interconnect 10 of FIG. 1C, and the inventive copper interconnect 53 of FIG. 4D. Additionally, if so desired, the silicon nitride layer 65 may be used as an etch stop when selectively removing the interlayer dielectric 69, such as during the formation of the via 69'. As with the barrier layer 51 of the copper interconnect 43 of FIG.
- deposition of the barrier layer 71 (of the copper interconnect 63 of FIG. 5C) on the sidewalls of the via 69' and sputter etching of the barrier layer 71, the silicon nitride layer 65, and any copper oxide layer 67a' at the bottom of the via 69' preferably occur simultaneously (e.g., within a high density plasma sputtering chamber) .
- deposition/sputter- etching may be performed sequentially within the same chamber or within different chambers (as previously described) .
- Each inventive copper interconnect 43, 53 and 63 preferably is formed without breaking vacuum between exposure of the first copper layer and deposition of the second copper layer, so as to maintain a copper-oxide free interface between the various layers of each interconnect.
- the exposure of the first copper layer and the deposition of the second copper layer preferably are performed within various processing chambers of an automated vacuum processing system such as Applied Materials' Endura® which provides wafer transfer within a vacuum environment, as disclosed in United States Patent No. 5,186,718, the entirety of which is hereby incorporated by reference herein.
- FIG. 6 is a top plan view of an automated semiconductor manufacturing tool 81 useful for performing the inventive methods.
- the automated semiconductor manufacturing tool 81 comprises a pair of chambers, a buffer chamber 83 and a transfer chamber 85 which house a first and a second wafer handler 87, 89, respectively.
- the buffer chamber is operatively coupled to a pair of load locks 91, 93 and to a pair of pass-through chambers 95, 97.
- Other chambers such as degassing or cool- down chambers also may be coupled to the buffer chamber 83.
- the transfer chamber 85 is coupled to the pass- through chambers 95, 97, and to a plurality of processing chambers 99, 101, 103 and 105.
- the first processing chamber 99 is for depositing barrier layers, e.g., a PVD or an HDP sputtering chamber having a tantalum or other barrier layer material sputtering target mounted therein.
- the first processing chamber 99 comprises the high density plasma sputtering chamber 21 of FIG. 2.
- the second processing chamber 101 comprises an etch chamber such as an Applied Materials' Preclean II chamber.
- the third processing chamber 103 comprises a PVD, HDP or CVD chamber for depositing copper seed layers.
- the fourth processing chamber 105 comprises a copper fill chamber such as a CVD or PVD chamber. If desired, the fill process can be performed via electroplating outside the tool 81 (rather than within the fourth processing chamber 105) .
- a controller 107 comprising a microprocessor 109 and memory 111 is operatively coupled to the first and second wafer handlers 87, 89, to the load locks 91, 93, to the four processing chambers 99 - 105, and to the various slit valves (not shown) for selectively sealing the load locks, pass-through chambers and processing chambers.
- the memory 111 contains a program for performing each of the interconnect formation methods described above for inventive interconnects 43, 53 and 63. In the example of FIG. 7, it is assumed that for each interconnect 43 , 53 and 63 , the vias 49, 59' and 69', respectively, are already formed by methods well known in the art prior to entering the tool 81.
- FIG. 7 is a flowchart of the operation, in pertinent part, of the automated semiconductor manufacturing tool 81 as controlled by the controller 107 during the formation of interconnects 43 , 53 and 63.
- step 701 an interconnect program 700 within the memory 111 of the controller 107 is executed.
- step 702 a wafer 113 is loaded into the load lock 91 of the tool 81 and the load lock 91 is pumped to a desired pressure (e.g., the pressure within the buffer chamber 83 ) .
- a desired pressure e.g., the pressure within the buffer chamber 83
- step 703 the first wafer handler 87 transfers the wafer 113 from the first load lock 91 to the pass- through 95 .
- step 704 the controller 107 selects the processing sequences for forming either the interconnect 43, the interconnect 53 or the interconnect 63 based on a previous selection by a user of the tool 81. Thereafter, the controller 107 executes either the interconnect 43 subroutine (step 705 described with reference to FIG. 8) , the interconnect 53 subroutine (step 706 described with reference to FIG. 9) or the interconnect 63 subroutine (step 707 described with reference to FIG. 10) . As described below, following any of these subroutines, the wafer 113 is contained within the third processing chamber 103 where a copper seed layer is deposited on the wafer 113.
- the wafer 113 is transferred by the second wafer handler 89 from the third processing chamber 103 to the fourth processing chamber 105, as indicated by step 708.
- a copper fill process is performed on the wafer 113 to fill the via 49, 59' or 69' with copper so as to complete formation of the copper interconnect (either the interconnect 43 , 53 or 63 , respectively) .
- the fill process may be a conventional CVD or PVD fill process as is known in the art, or the fill process may be subsequently performed via electroplating outside the vacuum environment of the tool 81.
- the copper fill process comprises the fill process disclosed in United States patent application Serial No. 08/768,058, filed December 16, 1996, titled "Selective Physical Vapor Deposition Conductor Fill in IC Structures," the entirety of which is hereby incorporated by reference herein.
- step 710 the second wafer handler 89 transfers the wafer 113 from the fourth processing chamber 105 to the second pass-through 97.
- step 711 the first wafer handler 87 transfers the wafer 113 from the second pass-through 97 to the second load lock 93.
- the wafer 113 thereafter may be removed from the second load lock 93 for subsequent device processing.
- step 712 the controller 107 halts execution of the interconnect program 700 for formation of the interconnect 43, 53 or 63 on wafer 113.
- the tool 81 is preferred for formation of the inventive interconnects, other tools (e.g., tools having a single wafer handler chamber) may be employed.
- FIG. 8 is a flow chart of the interconnect 43 subroutine 705 of FIG. 7.
- step 800 the interconnect 43 subroutine is started.
- step 801 the second wafer handler 89 transfers the wafer 113 from the first pass-through 95 to the first processing chamber 99.
- step 802 the controller 107 selects the processing sequences for either sequential deposition/sputter-etching within separate processing chambers (e.g., the first and second processing chambers 99, 101) (steps 803-806) or simultaneous deposition/sputter- etching within a single processing chamber (e.g., the first processing chamber 99) (steps 807 and 808) based on a previous selection by a user of the tool 81.
- the interconnect program 700 also may comprise processing sequences for sequential deposition/sputter-etching within a single processing chamber (e.g., the first processing chamber 99) as previously described with reference to FIGS. 2, 3A-C, 4A-D and 5A-C.
- step 803 the barrier layer 51 is deposited over the interlayer dielectric 45, the sidewalls of the via 49 and the exposed first copper layer 47a (FIG. 3A) . This may be performed via PVD, HDP deposition or CVD.
- step 804 the second wafer handler 89 transfers the wafer 113 from the first processing chamber 99 to the second processing chamber 101.
- step 805 the barrier layer 51 and any copper oxide layer 47a' are sputter-etched to expose the first copper layer 47a (FIG. 3B) .
- this etching is performed within an Applied Materials' Preclean II chamber.
- step 806 the second wafer handler 89 transfers the wafer 113 from the second processing chamber 101 to the third processing chamber 103.
- step 807 the barrier layer 51 is deposited on the interlayer dielectric 45 and the sidewalls of the via 49 while the bottom of the via 49 and the copper oxide layer 47a' are simultaneously sputter etched to expose the first copper layer 47a.
- simultaneous deposition/sputter- etching is performed in an HDP chamber such as an Applied Materials' Vectra IMP chamber.
- simultaneous deposition/sputter- etching is achieved by adjusting the ratio of the RF power applied to both the substrate support pedestal 29 and to the wire coil 23 as compared to the DC power applied to the target 27.
- step 808 the second wafer handler 89 transfers the wafer 113 from the first processing chamber 99 to the third processing chamber 103 for copper seed layer deposition. No etching within the second processing chamber 101 is required as the first copper layer 47a is exposed in step 807. Therefore, if simultaneous deposition/sputter- etching is used, the second processing chamber 101 is not required.
- a copper seed layer is deposited on the barrier layer 51 and on the exposed first copper layer 47a. Because the wafer 113 is maintained in a vacuum environment while within the tool 81, essentially no copper oxide reforms on the exposed first copper layer 47a prior to formation of the copper seed layer. An essentially oxide free, low resistance contact thereby is formed between the copper seed layer and the first copper layer 47a.
- the seed layer may be deposited using PVD, HDP deposition or CVD techniques.
- step 810 the subroutine 705 ends and the program returns to steps 708-712 wherein the via 49 is filled with copper to complete the interconnect 43 , and the wafer 113 is placed in the second load lock 93.
- FIG. 9 is a flowchart of the interconnect 53 subroutine 706 of FIG. 7.
- step 900 the interconnect 53 subroutine 706 is started.
- step 901 the second wafer handler 89 transfers the wafer 113 from the first pass-through 95 to the second processing chamber 101.
- step 902 the silicon nitride layer 55 and any copper oxide layer 57a' are sputter-etched within the second processing chamber 101 to expose the first copper layer 57a (FIG. 4B) .
- step 903 the second wafer handler 89 transfers the wafer 113 from the second processing chamber 101 to the first processing chamber 99.
- An alternative to steps 901- 903 is to transfer the wafer 113 from the first pass-through 95 to the first processing chamber 99, and to sputter-etch the silicon nitride layer 55 and any copper oxide layer 57a' within the first processing chamber 99 (assuming the first processing chamber 99 is an HDP sputtering chamber) as previously described with reference to FIGS. 4A-D. In this manner the second processing chamber 101 is not required.
- step 904 the barrier layer 61 is deposited over the interlayer dielectric 59 and the exposed first copper layer 57a (FIG. 4C) .
- step 905 the second wafer handler 89 transfers the wafer 113 from the first processing chamber 99 to the third processing chamber 103.
- step 906 a copper seed layer is deposited on the barrier layer 61.
- step 907 the subroutine 706 ends and the program returns to steps 708-712 wherein the via 59' is filled with copper to complete the interconnect 53, and the wafer 113 is placed in the second load lock 93.
- FIG. 10 is a flowchart of the interconnect 63 subroutine 707 of FIG. 7. In step 1000, the interconnect 63 subroutine 707 is started.
- step 1001 the second wafer handler 89 transfers the wafer 113 from the first pass-through 95 to the first processing chamber 99.
- the controller 107 selects the processing sequences for either sequential deposition/sputter-etching within separate processing chambers (e.g., the first and second processing chambers 99, 101) (steps 1003-1006) or simultaneous deposition/sputter- etching within a single chamber (e.g., the first processing chamber 99) (steps 1007 and 1008) based on a previous selection by a user of the tool 81.
- the interconnect program 700 also may comprise processing sequences for sequential deposition/sputter- etching within a single processing chamber (e.g., the first processing chamber 99) as previously described with reference to FIGS. 2, 3A-C, 4A-D and 5A-C.
- step 1003 the barrier layer 71 is deposited over the interlayer dielectric 69 and the exposed silicon nitride layer 65 (FIG. 5A) . This may be performed via PVD, HDP deposition or CVD.
- step 1004 the second wafer handler 89 transfers the wafer 113 from the first processing chamber 99 to the second processing chamber 101.
- step 1005 the barrier layer 71, the silicon nitride layer 65 and any copper oxide layer 67a' are sputter-etched to expose the first copper layer 67a (FIG. 5B) .
- this etching is performed within an Applied Materials' Preclean II chamber.
- step 1006 the second wafer handler 89 transfers the wafer 113 from the second processing chamber 101 to the third processing chamber 103.
- step 1007 the barrier layer 71 is deposited on the interlayer dielectric 69 and on the sidewalls of the via 69' while the bottom of the via 69', the silicon nitride layer 65 and the copper oxide layer 67a' are simultaneously sputter-etched to expose the first copper layer 67a.
- simultaneous deposition/sputter-etching is performed in an HDP chamber such as an Applied Materials ' Vectra IMP chamber.
- simultaneous deposition/sputter-etching is achieved by adjusting the ratio of the RF power applied to both the substrate support pedestal 29 and to the wire coil 23 as compared to the DC power applied to the target 27.
- step 1008 the second wafer handler 89 transfers the wafer 113 from the first processing chamber 99 to the third processing chamber 103. No etching within the second processing chamber 101 is required as the first copper layer 67a is exposed in step 1007. Therefore, if simultaneous deposition/sputter-etching is used, the second processing chamber 101 is not required.
- a copper seed layer is deposited on the barrier layer 71 and on the exposed first copper layer 67a. Because the wafer 113 is maintained within a vacuum environment during transfer among the chambers 99 - 105, essentially no copper oxide reforms on the exposed first copper layer 67a prior to formation of the copper seed layer. An essentially oxide free, low resistance contact thereby is formed between the copper seed layer and the first copper layer 67a.
- the seed layer may be deposited using PVD, HDP deposition or CVD techniques .
- step 1010 the subroutine 707 ends and the program returns to steps 708-712 wherein the via 69' is filled with copper to complete the interconnect 63 , and the wafer 113 is placed in the second load lock 93.
- the interconnect program 700 of FIGS. 7-10 is merely exemplary.
- the program may comprise only a single subroutine 705, 706, 707, and/or each subroutine may contain only the sequential deposition and etch steps (within single or multiple processing chambers) or the simultaneous deposition and etch steps. Further, a number of steps may be performed prior to placing the wafer 113 within the tool 81, and with respect to the interconnects 43 and 63 , the interconnect program therefore may be as simple as depositing the second copper layer on the exposed first copper layer and thereby creating direct metal-to-metal contact between the first and second copper layers .
- the controller 107 may comprise a plurality of interfaced controllers, each of the plurality of controllers having input/output ports for receiving/transmitting control signals from/to other controllers, processing chambers, etc., interfaced thereto.
- control signals control various chamber conditions such as temperatures, pressures, flow rates, wafer, coil and target biases, etc., so as to achieve the desired processing step (e.g., deposition, etch, etc.) as is known in the art.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99937492A EP1099250A2 (en) | 1998-07-31 | 1999-07-26 | Method and apparatus for forming improved metal interconnects |
JP2000562948A JP2002521842A (en) | 1998-07-31 | 1999-07-26 | Method and apparatus for improved metal wiring |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/126,890 | 1998-07-31 | ||
US09/126,890 US6287977B1 (en) | 1998-07-31 | 1998-07-31 | Method and apparatus for forming improved metal interconnects |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000007236A2 true WO2000007236A2 (en) | 2000-02-10 |
WO2000007236A3 WO2000007236A3 (en) | 2000-06-22 |
Family
ID=22427225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/016887 WO2000007236A2 (en) | 1998-07-31 | 1999-07-26 | Method and apparatus for forming improved metal interconnects |
Country Status (5)
Country | Link |
---|---|
US (4) | US6287977B1 (en) |
EP (2) | EP1246240A2 (en) |
JP (1) | JP2002521842A (en) |
TW (1) | TW410431B (en) |
WO (1) | WO2000007236A2 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001020665A1 (en) * | 1999-09-14 | 2001-03-22 | Commissariat A L'energie Atomique | Method for producing a copper connection |
WO2002091461A2 (en) * | 2001-05-04 | 2002-11-14 | Tokyo Electron Limited | Ionized pvd with sequential deposition and etching |
EP1229580A3 (en) * | 2001-02-01 | 2003-03-26 | Texas Instruments Incorporated | Electrochemical reduction of copper seed for reducing voids in electrochemical deposition |
EP1352422A1 (en) * | 2001-01-18 | 2003-10-15 | STMicroelectronics S.A. | Method for making interconnection networks |
US7576002B2 (en) | 2000-11-01 | 2009-08-18 | Applied Materials, Inc. | Multi-step barrier deposition method |
JP2009246394A (en) * | 2009-07-27 | 2009-10-22 | Nec Corp | Manufacturing method of semiconductor device |
US7744735B2 (en) | 2001-05-04 | 2010-06-29 | Tokyo Electron Limited | Ionized PVD with sequential deposition and etching |
US7936069B2 (en) | 2004-06-10 | 2011-05-03 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
US8324095B2 (en) | 2001-09-26 | 2012-12-04 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
US8432037B2 (en) | 2004-06-10 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
US9062372B2 (en) | 2002-08-01 | 2015-06-23 | Applied Materials, Inc. | Self-ionized and capacitively-coupled plasma for sputtering and resputtering |
US10047430B2 (en) | 1999-10-08 | 2018-08-14 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
Families Citing this family (104)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7253109B2 (en) * | 1997-11-26 | 2007-08-07 | Applied Materials, Inc. | Method of depositing a tantalum nitride/tantalum diffusion barrier layer system |
KR20010032498A (en) * | 1997-11-26 | 2001-04-25 | 조셉 제이. 스위니 | Damage-free sculptured coating deposition |
US6911124B2 (en) * | 1998-09-24 | 2005-06-28 | Applied Materials, Inc. | Method of depositing a TaN seed layer |
US20050272254A1 (en) * | 1997-11-26 | 2005-12-08 | Applied Materials, Inc. | Method of depositing low resistivity barrier layers for copper interconnects |
US6355571B1 (en) * | 1998-11-17 | 2002-03-12 | Applied Materials, Inc. | Method and apparatus for reducing copper oxidation and contamination in a semiconductor device |
US7381638B1 (en) * | 1999-06-09 | 2008-06-03 | National Semiconductor Corporation | Fabrication technique using sputter etch and vacuum transfer |
US6927160B1 (en) * | 1999-06-09 | 2005-08-09 | National Semiconductor Corporation | Fabrication of copper-containing region such as electrical interconnect |
US20030116427A1 (en) * | 2001-08-30 | 2003-06-26 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
US8696875B2 (en) * | 1999-10-08 | 2014-04-15 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
US6277249B1 (en) * | 2000-01-21 | 2001-08-21 | Applied Materials Inc. | Integrated process for copper via filling using a magnetron and target producing highly energetic ions |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
US6641747B1 (en) * | 2001-02-15 | 2003-11-04 | Advanced Micro Devices, Inc. | Method and apparatus for determining an etch endpoint |
US6607977B1 (en) | 2001-03-13 | 2003-08-19 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnect applications |
US7781327B1 (en) * | 2001-03-13 | 2010-08-24 | Novellus Systems, Inc. | Resputtering process for eliminating dielectric damage |
US7186648B1 (en) | 2001-03-13 | 2007-03-06 | Novellus Systems, Inc. | Barrier first method for single damascene trench applications |
US6642146B1 (en) | 2001-03-13 | 2003-11-04 | Novellus Systems, Inc. | Method of depositing copper seed on semiconductor substrates |
US8043484B1 (en) | 2001-03-13 | 2011-10-25 | Novellus Systems, Inc. | Methods and apparatus for resputtering process that improves barrier coverage |
US6764940B1 (en) * | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
US6649517B2 (en) * | 2001-05-18 | 2003-11-18 | Chartered Semiconductor Manufacturing Ltd. | Copper metal structure for the reduction of intra-metal capacitance |
US6503824B1 (en) * | 2001-10-12 | 2003-01-07 | Mosel Vitelic, Inc. | Forming conductive layers on insulators by physical vapor deposition |
KR100993046B1 (en) * | 2001-11-14 | 2010-11-08 | 어플라이드 머티어리얼스, 인코포레이티드 | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
US6797620B2 (en) | 2002-04-16 | 2004-09-28 | Applied Materials, Inc. | Method and apparatus for improved electroplating fill of an aperture |
US7005375B2 (en) * | 2002-09-30 | 2006-02-28 | Agere Systems Inc. | Method to avoid copper contamination of a via or dual damascene structure |
US6797642B1 (en) | 2002-10-08 | 2004-09-28 | Novellus Systems, Inc. | Method to improve barrier layer adhesion |
US7565137B2 (en) * | 2002-10-25 | 2009-07-21 | At&T Mobility Ii Llc | Delivery of network services |
US7241696B2 (en) * | 2002-12-11 | 2007-07-10 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer |
US6949461B2 (en) * | 2002-12-11 | 2005-09-27 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure |
US7147767B2 (en) * | 2002-12-16 | 2006-12-12 | 3M Innovative Properties Company | Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor |
US6858124B2 (en) * | 2002-12-16 | 2005-02-22 | 3M Innovative Properties Company | Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor |
US6884338B2 (en) * | 2002-12-16 | 2005-04-26 | 3M Innovative Properties Company | Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor |
US7294241B2 (en) * | 2003-01-03 | 2007-11-13 | Chartered Semiconductor Manufacturing Ltd. | Method to form alpha phase Ta and its application to IC manufacturing |
US6802945B2 (en) | 2003-01-06 | 2004-10-12 | Megic Corporation | Method of metal sputtering for integrated circuit metal routing |
US6806192B2 (en) * | 2003-01-24 | 2004-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of barrier-less integration with copper alloy |
US6943111B2 (en) * | 2003-02-10 | 2005-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier free copper interconnect by multi-layer copper seed |
US6784105B1 (en) * | 2003-04-09 | 2004-08-31 | Infineon Technologies North America Corp. | Simultaneous native oxide removal and metal neutral deposition method |
US7842605B1 (en) | 2003-04-11 | 2010-11-30 | Novellus Systems, Inc. | Atomic layer profiling of diffusion barrier and metal seed layers |
US8298933B2 (en) | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
US20040211661A1 (en) * | 2003-04-23 | 2004-10-28 | Da Zhang | Method for plasma deposition of a substrate barrier layer |
JP2007502551A (en) * | 2003-06-13 | 2007-02-08 | アプライド マテリアルズ インコーポレイテッド | Integration of ALD tantalum nitride for copper metallization |
US7205235B2 (en) * | 2003-12-15 | 2007-04-17 | Freescale Semiconductor, Inc. | Method for reducing corrosion of metal surfaces during semiconductor processing |
KR100558009B1 (en) * | 2004-01-12 | 2006-03-06 | 삼성전자주식회사 | Method of fabricating a semiconductor device forming a diffusion barrier layer selectively and a semiconductor device fabricated thereby |
JP2005235860A (en) | 2004-02-17 | 2005-09-02 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
US20050189656A1 (en) * | 2004-02-26 | 2005-09-01 | Chun Yee Tan | Micro-vias for electronic packaging |
US7235487B2 (en) * | 2004-05-13 | 2007-06-26 | International Business Machines Corporation | Metal seed layer deposition |
JP4786680B2 (en) * | 2004-06-10 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US20060024953A1 (en) * | 2004-07-29 | 2006-02-02 | Papa Rao Satyavolu S | Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess |
KR100621548B1 (en) * | 2004-07-30 | 2006-09-14 | 삼성전자주식회사 | Method for forming metal interconnection layer of semiconductor device |
US7390739B2 (en) * | 2005-05-18 | 2008-06-24 | Lazovsky David E | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
US8882914B2 (en) * | 2004-09-17 | 2014-11-11 | Intermolecular, Inc. | Processing substrates using site-isolated processing |
US20060292846A1 (en) * | 2004-09-17 | 2006-12-28 | Pinto Gustavo A | Material management in substrate processing |
US7749881B2 (en) * | 2005-05-18 | 2010-07-06 | Intermolecular, Inc. | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
US20060060301A1 (en) * | 2004-09-17 | 2006-03-23 | Lazovsky David E | Substrate processing using molecular self-assembly |
US8084400B2 (en) * | 2005-10-11 | 2011-12-27 | Intermolecular, Inc. | Methods for discretized processing and process sequence integration of regions of a substrate |
US7399943B2 (en) * | 2004-10-05 | 2008-07-15 | Applied Materials, Inc. | Apparatus for metal plasma vapor deposition and re-sputter with source and bias power frequencies applied through the workpiece |
US7214619B2 (en) * | 2004-10-05 | 2007-05-08 | Applied Materials, Inc. | Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece |
US7268076B2 (en) * | 2004-10-05 | 2007-09-11 | Applied Materials, Inc. | Apparatus and method for metal plasma vapor deposition and re-sputter with source and bias power frequencies applied through the workpiece |
JP2006148074A (en) * | 2004-10-19 | 2006-06-08 | Tokyo Electron Ltd | Method of depositing film and equipment for plasma-deposing film |
US7879710B2 (en) * | 2005-05-18 | 2011-02-01 | Intermolecular, Inc. | Substrate processing including a masking layer |
WO2006058034A2 (en) * | 2004-11-22 | 2006-06-01 | Intermolecular, Inc. | Molecular self-assembly in substrate processing |
US7820020B2 (en) * | 2005-02-03 | 2010-10-26 | Applied Materials, Inc. | Apparatus for plasma-enhanced physical vapor deposition of copper with RF source power applied through the workpiece with a lighter-than-copper carrier gas |
US7465680B2 (en) * | 2005-09-07 | 2008-12-16 | Applied Materials, Inc. | Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 |
US7955436B2 (en) * | 2006-02-24 | 2011-06-07 | Intermolecular, Inc. | Systems and methods for sealing in site-isolated reactors |
US7544574B2 (en) * | 2005-10-11 | 2009-06-09 | Intermolecular, Inc. | Methods for discretized processing of regions of a substrate |
US8776717B2 (en) * | 2005-10-11 | 2014-07-15 | Intermolecular, Inc. | Systems for discretized processing of regions of a substrate |
EP1994550A4 (en) * | 2006-02-10 | 2012-01-11 | Intermolecular Inc | Method and apparatus for combinatorially varying materials, unit process and process sequence |
US8772772B2 (en) * | 2006-05-18 | 2014-07-08 | Intermolecular, Inc. | System and method for increasing productivity of combinatorial screening |
US7517736B2 (en) * | 2006-02-15 | 2009-04-14 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
US20070252277A1 (en) * | 2006-04-28 | 2007-11-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and fabrication method thereof |
US7645696B1 (en) | 2006-06-22 | 2010-01-12 | Novellus Systems, Inc. | Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer |
US7855147B1 (en) | 2006-06-22 | 2010-12-21 | Novellus Systems, Inc. | Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer |
JP2008010532A (en) * | 2006-06-28 | 2008-01-17 | Sony Corp | Manufacturing method of semiconductor device |
JP2008060243A (en) * | 2006-08-30 | 2008-03-13 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
JP2008085175A (en) * | 2006-09-28 | 2008-04-10 | Tokyo Electron Ltd | Semiconductor device manufacturing method, semiconductor device, substrate processing system, program, and storage medium |
US7510634B1 (en) | 2006-11-10 | 2009-03-31 | Novellus Systems, Inc. | Apparatus and methods for deposition and/or etch selectivity |
US20080160754A1 (en) * | 2006-12-27 | 2008-07-03 | International Business Machines Corporation | Method for fabricating a microelectronic conductor structure |
US8011317B2 (en) * | 2006-12-29 | 2011-09-06 | Intermolecular, Inc. | Advanced mixing system for integrated tool having site-isolated reactors |
DE102007004884A1 (en) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | A method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer |
DE102007004860B4 (en) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | A method of making a copper-based metallization layer having a conductive overcoat by an improved integration scheme |
US7682966B1 (en) | 2007-02-01 | 2010-03-23 | Novellus Systems, Inc. | Multistep method of depositing metal seed layers |
JP5194549B2 (en) | 2007-04-27 | 2013-05-08 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US20080280446A1 (en) * | 2007-05-08 | 2008-11-13 | Qimonda Ag | Method of producing a microscopic hole in a layer and integrated device with a microscopic hole in a layer |
US7897516B1 (en) | 2007-05-24 | 2011-03-01 | Novellus Systems, Inc. | Use of ultra-high magnetic fields in resputter and plasma etching |
US7922880B1 (en) | 2007-05-24 | 2011-04-12 | Novellus Systems, Inc. | Method and apparatus for increasing local plasma density in magnetically confined plasma |
US20080311711A1 (en) * | 2007-06-13 | 2008-12-18 | Roland Hampp | Gapfill for metal contacts |
US20090050471A1 (en) * | 2007-08-24 | 2009-02-26 | Spansion Llc | Process of forming an electronic device including depositing layers within openings |
US7659197B1 (en) | 2007-09-21 | 2010-02-09 | Novellus Systems, Inc. | Selective resputtering of metal seed layers |
US8017523B1 (en) | 2008-05-16 | 2011-09-13 | Novellus Systems, Inc. | Deposition of doped copper seed layers having improved reliability |
US8354751B2 (en) * | 2008-06-16 | 2013-01-15 | International Business Machines Corporation | Interconnect structure for electromigration enhancement |
TWI501302B (en) * | 2008-08-21 | 2015-09-21 | Acm Res Shanghai Inc | Barrier layer removal mtehod and apparatus |
KR20100032644A (en) * | 2008-09-18 | 2010-03-26 | 삼성전자주식회사 | Method of forming metallization in semiconductor devices using selectively plasma treatment |
JP5377993B2 (en) * | 2009-01-30 | 2013-12-25 | 株式会社日立ハイテクノロジーズ | Plasma processing method |
US8575000B2 (en) * | 2011-07-19 | 2013-11-05 | SanDisk Technologies, Inc. | Copper interconnects separated by air gaps and method of making thereof |
CN104081879B (en) * | 2012-01-18 | 2017-03-01 | 株式会社日本有机雷特显示器 | Electronic installation and its manufacture method |
US8729702B1 (en) * | 2012-11-20 | 2014-05-20 | Stmicroelectronics, Inc. | Copper seed layer for an interconnect structure having a doping concentration level gradient |
US9748169B1 (en) | 2016-04-04 | 2017-08-29 | International Business Machines Corporation | Treating copper interconnects |
US9786605B1 (en) | 2016-05-27 | 2017-10-10 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
US10396012B2 (en) | 2016-05-27 | 2019-08-27 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
US10312181B2 (en) | 2016-05-27 | 2019-06-04 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
TWI700799B (en) | 2016-10-04 | 2020-08-01 | 聯華電子股份有限公司 | Conductive structure, layout structure including conductive structure, and method for manufacturing conductive structure |
CA3229060A1 (en) * | 2017-01-18 | 2018-08-09 | Shine Technologies, Llc | High power ion beam generator systems and methods |
JP7171216B2 (en) * | 2018-04-10 | 2022-11-15 | 東洋鋼鈑株式会社 | Rolled bonded body and method for manufacturing rolled bonded body |
KR102493464B1 (en) | 2018-07-19 | 2023-01-30 | 삼성전자 주식회사 | Integrated circuit device and method for manufacturing the same |
US11081388B2 (en) | 2019-01-10 | 2021-08-03 | International Business Machines Corporation | Forming barrierless contact |
KR102372438B1 (en) * | 2019-04-30 | 2022-03-08 | 한국전기연구원 | Thermoelectric element substrate and thermoelectric element |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5486492A (en) * | 1992-10-30 | 1996-01-23 | Kawasaki Steel Corporation | Method of forming multilayered wiring structure in semiconductor device |
EP0788160A2 (en) * | 1996-02-05 | 1997-08-06 | Matsushita Electronics Corporation | Semiconductor device having a multi-layered wire structure |
EP0798778A2 (en) * | 1996-03-25 | 1997-10-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device of multilayer wire structure |
EP0892428A2 (en) * | 1997-07-17 | 1999-01-20 | Sharp Kabushiki Kaisha | Method of producing low resistance contacts between integrated circuit metal levels and structure produced thereby. |
Family Cites Families (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3410774A (en) | 1965-10-23 | 1968-11-12 | Ibm | Method and apparatus for reverse sputtering selected electrically exposed areas of a cathodically biased workpiece |
US4201266A (en) * | 1978-11-02 | 1980-05-06 | Texaco Inc. | Rotatable washer self-cleaning helical spring screen and methods |
US4358338A (en) | 1980-05-16 | 1982-11-09 | Varian Associates, Inc. | End point detection method for physical etching process |
AU570439B2 (en) | 1983-03-28 | 1988-03-17 | Compression Labs, Inc. | A combined intraframe and interframe transform coding system |
JPS6060060A (en) | 1983-09-12 | 1985-04-06 | 株式会社日立製作所 | Switchgear for door of railway rolling stock |
FI72557C (en) | 1984-01-11 | 1992-01-08 | Kemira Oy | Paper making process and blend composition for use therein |
US4865712A (en) | 1984-05-17 | 1989-09-12 | Varian Associates, Inc. | Apparatus for manufacturing planarized aluminum films |
US4681653A (en) | 1984-06-01 | 1987-07-21 | Texas Instruments Incorporated | Planarized dielectric deposited using plasma enhanced chemical vapor deposition |
JPH0697660B2 (en) | 1985-03-23 | 1994-11-30 | 日本電信電話株式会社 | Thin film formation method |
JPS61261472A (en) | 1985-05-13 | 1986-11-19 | Nippon Telegr & Teleph Corp <Ntt> | Bias sputtering method and its apparatus |
KR900005785B1 (en) | 1985-05-13 | 1990-08-11 | 닛뽄덴신덴와 가부시끼가이샤 | Flat thin film manufacturing method |
CH665428A5 (en) | 1985-07-26 | 1988-05-13 | Balzers Hochvakuum | METHOD FOR COATING MICRO-RECESSES. |
US4891112A (en) | 1985-11-12 | 1990-01-02 | Eastman Kodak Company | Sputtering method for reducing hillocking in aluminum layers formed on substrates |
JPS62287071A (en) | 1986-06-06 | 1987-12-12 | Tadahiro Omi | Semiconductor producing apparatus |
JPH0798521B2 (en) | 1986-08-20 | 1995-10-25 | 澁谷工業株式会社 | Rotary weight filling device |
US4756810A (en) | 1986-12-04 | 1988-07-12 | Machine Technology, Inc. | Deposition and planarizing methods and apparatus |
US4767496A (en) | 1986-12-11 | 1988-08-30 | Siemens Aktiengesellschaft | Method for controlling and supervising etching processes |
US4810335A (en) | 1987-01-20 | 1989-03-07 | Siemens Aktiengesellschaft | Method for monitoring etching processes |
US4962060A (en) | 1987-03-10 | 1990-10-09 | Advanced Micro Devices, Inc. | Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism |
JP2602276B2 (en) | 1987-06-30 | 1997-04-23 | 株式会社日立製作所 | Sputtering method and apparatus |
US4793895A (en) | 1988-01-25 | 1988-12-27 | Ibm Corporation | In situ conductivity monitoring technique for chemical/mechanical planarization endpoint detection |
US4963239A (en) | 1988-01-29 | 1990-10-16 | Hitachi, Ltd. | Sputtering process and an apparatus for carrying out the same |
US4874493A (en) | 1988-03-28 | 1989-10-17 | Microelectronics And Computer Technology Corporation | Method of deposition of metal into cavities on a substrate |
JPH0730468B2 (en) | 1988-06-09 | 1995-04-05 | 日電アネルバ株式会社 | Dry etching equipment |
JP2565758B2 (en) | 1988-11-14 | 1996-12-18 | 弓子 福原 | Sound environment control method |
US5126028A (en) | 1989-04-17 | 1992-06-30 | Materials Research Corporation | Sputter coating process control method and apparatus |
JPH0740569B2 (en) | 1990-02-27 | 1995-05-01 | エイ・ティ・アンド・ティ・コーポレーション | ECR plasma deposition method |
JPH0414831A (en) | 1990-05-08 | 1992-01-20 | Sony Corp | Formation method of interconnection |
JPH0430421A (en) | 1990-05-25 | 1992-02-03 | Sony Corp | Selective metal growth method |
US5069770A (en) | 1990-07-23 | 1991-12-03 | Eastman Kodak Company | Sputtering process employing an enclosed sputtering target |
US5078847A (en) | 1990-08-29 | 1992-01-07 | Jerry Grosman | Ion plating method and apparatus |
US5178739A (en) | 1990-10-31 | 1993-01-12 | International Business Machines Corporation | Apparatus for depositing material into high aspect ratio holes |
JPH0529254A (en) | 1991-07-24 | 1993-02-05 | Sony Corp | Forming method of wiring |
DE9109503U1 (en) | 1991-07-31 | 1991-10-17 | Magtron Magneto Elektronische Geraete Gmbh, 7583 Ottersweier, De | |
US5482611A (en) | 1991-09-30 | 1996-01-09 | Helmer; John C. | Physical vapor deposition employing ion extraction from a plasma |
US5270264A (en) | 1991-12-20 | 1993-12-14 | Intel Corporation | Process for filling submicron spaces with dielectric |
US5262354A (en) | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5300813A (en) | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5302266A (en) | 1992-03-20 | 1994-04-12 | International Business Machines Corporation | Method and apparatus for filing high aspect patterns with metal |
US5685961A (en) | 1992-03-27 | 1997-11-11 | P & D Medical Coatings, Inc. | Method for fabrication of metallized medical devices |
US5371042A (en) | 1992-06-16 | 1994-12-06 | Applied Materials, Inc. | Method of filling contacts in semiconductor devices |
US5612254A (en) | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
US5346600A (en) | 1992-08-14 | 1994-09-13 | Hughes Aircraft Company | Plasma-enhanced magnetron-sputtered deposition of materials |
US5271972A (en) | 1992-08-17 | 1993-12-21 | Applied Materials, Inc. | Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity |
DE4237334A1 (en) * | 1992-11-05 | 1994-05-11 | Hoechst Ag | Method for the quantitative purification of glycolipids |
US5510011A (en) | 1992-11-09 | 1996-04-23 | Canon Kabushiki Kaisha | Method for forming a functional deposited film by bias sputtering process at a relatively low substrate temperature |
US5354712A (en) | 1992-11-12 | 1994-10-11 | Northern Telecom Limited | Method for forming interconnect structures for integrated circuits |
US5350479A (en) | 1992-12-02 | 1994-09-27 | Applied Materials, Inc. | Electrostatic chuck for high power plasma processing |
US5718813A (en) | 1992-12-30 | 1998-02-17 | Advanced Energy Industries, Inc. | Enhanced reactive DC sputtering system |
US5376584A (en) | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
US5591269A (en) | 1993-06-24 | 1997-01-07 | Tokyo Electron Limited | Vacuum processing apparatus |
US5639357A (en) | 1994-05-12 | 1997-06-17 | Applied Materials | Synchronous modulation bias sputter method and apparatus for complete planarization of metal films |
US5651865A (en) | 1994-06-17 | 1997-07-29 | Eni | Preferential sputtering of insulators from conductive targets |
US5516399A (en) | 1994-06-30 | 1996-05-14 | International Business Machines Corporation | Contactless real-time in-situ monitoring of a chemical etching |
DE69529775T2 (en) | 1994-08-05 | 2003-10-16 | Ibm | Process for producing a damascus structure with a WGe polishing stop layer |
US5654232A (en) | 1994-08-24 | 1997-08-05 | Intel Corporation | Wetting layer sidewalls to promote copper reflow into grooves |
US5472349A (en) | 1994-10-31 | 1995-12-05 | The Whitaker Corporation | Surface mountable board edge connector |
EP0735577A3 (en) | 1994-12-14 | 1997-04-02 | Applied Materials Inc | Deposition process and apparatus therefor |
JP3655334B2 (en) | 1994-12-26 | 2005-06-02 | 松下電器産業株式会社 | Magnetron sputtering equipment |
US5585974A (en) | 1995-02-17 | 1996-12-17 | Conner Peripherals, Inc. | Disk drive with PRML read channel calibration using a noise generator |
US5512150A (en) | 1995-03-09 | 1996-04-30 | Hmt Technology Corporation | Target assembly having inner and outer targets |
US5613296A (en) | 1995-04-13 | 1997-03-25 | Texas Instruments Incorporated | Method for concurrent formation of contact and via holes |
US5534460A (en) | 1995-04-27 | 1996-07-09 | Vanguard International Semiconductor Corp. | Optimized contact plug process |
US5858184A (en) | 1995-06-07 | 1999-01-12 | Applied Materials, Inc. | Process for forming improved titanium-containing barrier layers |
US5589041A (en) | 1995-06-07 | 1996-12-31 | Sony Corporation | Plasma sputter etching system with reduced particle contamination |
EP0751566A3 (en) | 1995-06-30 | 1997-02-26 | Ibm | A thin film metal barrier for electrical interconnections |
US5810963A (en) | 1995-09-28 | 1998-09-22 | Kabushiki Kaisha Toshiba | Plasma processing apparatus and method |
US5584974A (en) | 1995-10-20 | 1996-12-17 | Eni | Arc control and switching element protection for pulsed dc cathode sputtering power supply |
AUPN637795A0 (en) * | 1995-11-03 | 1995-11-30 | Ici Australia Operations Proprietary Limited | Method and apparatus for blasthole stemming |
US5674787A (en) | 1996-01-16 | 1997-10-07 | Sematech, Inc. | Selective electroless copper deposited interconnect plugs for ULSI applications |
US5807467A (en) | 1996-01-22 | 1998-09-15 | Micron Technology, Inc. | In situ preclean in a PVD chamber with a biased substrate configuration |
US5770023A (en) | 1996-02-12 | 1998-06-23 | Eni A Division Of Astec America, Inc. | Etch process employing asymmetric bipolar pulsed DC |
US5744376A (en) | 1996-04-08 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte, Ltd | Method of manufacturing copper interconnect with top barrier layer |
US5725739A (en) | 1996-07-08 | 1998-03-10 | Micron Technology, Inc. | Low angle, low energy physical vapor deposition of alloys |
US5846332A (en) | 1996-07-12 | 1998-12-08 | Applied Materials, Inc. | Thermally floating pedestal collar in a chemical vapor deposition chamber |
US5693563A (en) | 1996-07-15 | 1997-12-02 | Chartered Semiconductor Manufacturing Pte Ltd. | Etch stop for copper damascene process |
US6001420A (en) | 1996-09-23 | 1999-12-14 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
US5685959A (en) | 1996-10-25 | 1997-11-11 | Hmt Technology Corporation | Cathode assembly having rotating magnetic-field shunt and method of making magnetic recording media |
US5933753A (en) | 1996-12-16 | 1999-08-03 | International Business Machines Corporation | Open-bottomed via liner structure and method for fabricating same |
JPH10219430A (en) | 1997-02-05 | 1998-08-18 | Minolta Co Ltd | Compound thin film obtainable by magnetron sputtering method and method and apparatus for production the same |
US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
JP3846970B2 (en) | 1997-04-14 | 2006-11-15 | キヤノンアネルバ株式会社 | Ionization sputtering equipment |
TW417249B (en) * | 1997-05-14 | 2001-01-01 | Applied Materials Inc | Reliability barrier integration for cu application |
US5985762A (en) | 1997-05-19 | 1999-11-16 | International Business Machines Corporation | Method of forming a self-aligned copper diffusion barrier in vias |
US5897752A (en) | 1997-05-20 | 1999-04-27 | Applied Materials, Inc. | Wafer bias ring in a sustained self-sputtering reactor |
US6051114A (en) | 1997-06-23 | 2000-04-18 | Applied Materials, Inc. | Use of pulsed-DC wafer bias for filling vias/trenches with metal in HDP physical vapor deposition |
US6375810B2 (en) | 1997-08-07 | 2002-04-23 | Applied Materials, Inc. | Plasma vapor deposition with coil sputtering |
US6042700A (en) | 1997-09-15 | 2000-03-28 | Applied Materials, Inc. | Adjustment of deposition uniformity in an inductively coupled plasma source |
US6136693A (en) | 1997-10-27 | 2000-10-24 | Chartered Semiconductor Manufacturing Ltd. | Method for planarized interconnect vias using electroless plating and CMP |
US6106625A (en) | 1997-12-02 | 2000-08-22 | Applied Materials, Inc. | Reactor useful for chemical vapor deposition of titanium nitride |
US5976327A (en) | 1997-12-12 | 1999-11-02 | Applied Materials, Inc. | Step coverage and overhang improvement by pedestal bias voltage modulation |
US6110821A (en) | 1998-01-27 | 2000-08-29 | Applied Materials, Inc. | Method for forming titanium silicide in situ |
-
1998
- 1998-07-31 US US09/126,890 patent/US6287977B1/en not_active Expired - Lifetime
-
1999
- 1999-05-27 TW TW088108728A patent/TW410431B/en not_active IP Right Cessation
- 1999-07-26 EP EP02014021A patent/EP1246240A2/en not_active Withdrawn
- 1999-07-26 WO PCT/US1999/016887 patent/WO2000007236A2/en not_active Application Discontinuation
- 1999-07-26 EP EP99937492A patent/EP1099250A2/en not_active Withdrawn
- 1999-07-26 JP JP2000562948A patent/JP2002521842A/en not_active Withdrawn
-
2001
- 2001-08-13 US US09/928,891 patent/US6559061B2/en not_active Expired - Fee Related
-
2002
- 2002-02-05 US US10/067,709 patent/US6709987B2/en not_active Expired - Lifetime
-
2004
- 2004-01-21 US US10/761,466 patent/US6992012B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5486492A (en) * | 1992-10-30 | 1996-01-23 | Kawasaki Steel Corporation | Method of forming multilayered wiring structure in semiconductor device |
EP0788160A2 (en) * | 1996-02-05 | 1997-08-06 | Matsushita Electronics Corporation | Semiconductor device having a multi-layered wire structure |
EP0798778A2 (en) * | 1996-03-25 | 1997-10-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device of multilayer wire structure |
EP0892428A2 (en) * | 1997-07-17 | 1999-01-20 | Sharp Kabushiki Kaisha | Method of producing low resistance contacts between integrated circuit metal levels and structure produced thereby. |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6521533B1 (en) | 1999-09-14 | 2003-02-18 | Commissariat A L'energie Atomique | Method for producing a copper connection |
WO2001020665A1 (en) * | 1999-09-14 | 2001-03-22 | Commissariat A L'energie Atomique | Method for producing a copper connection |
US10047430B2 (en) | 1999-10-08 | 2018-08-14 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
US7576002B2 (en) | 2000-11-01 | 2009-08-18 | Applied Materials, Inc. | Multi-step barrier deposition method |
EP1352422B1 (en) * | 2001-01-18 | 2018-10-31 | STMicroelectronics S.A. | Method for making interconnection networks |
EP1352422A1 (en) * | 2001-01-18 | 2003-10-15 | STMicroelectronics S.A. | Method for making interconnection networks |
EP1229580A3 (en) * | 2001-02-01 | 2003-03-26 | Texas Instruments Incorporated | Electrochemical reduction of copper seed for reducing voids in electrochemical deposition |
KR100878103B1 (en) | 2001-05-04 | 2009-01-14 | 도쿄엘렉트론가부시키가이샤 | Ionized pvd with sequential deposition and etching |
US6755945B2 (en) | 2001-05-04 | 2004-06-29 | Tokyo Electron Limited | Ionized PVD with sequential deposition and etching |
US7744735B2 (en) | 2001-05-04 | 2010-06-29 | Tokyo Electron Limited | Ionized PVD with sequential deposition and etching |
WO2002091461A3 (en) * | 2001-05-04 | 2003-02-27 | Tokyo Electron Ltd | Ionized pvd with sequential deposition and etching |
WO2002091461A2 (en) * | 2001-05-04 | 2002-11-14 | Tokyo Electron Limited | Ionized pvd with sequential deposition and etching |
US8324095B2 (en) | 2001-09-26 | 2012-12-04 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
US9062372B2 (en) | 2002-08-01 | 2015-06-23 | Applied Materials, Inc. | Self-ionized and capacitively-coupled plasma for sputtering and resputtering |
US7936069B2 (en) | 2004-06-10 | 2011-05-03 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
US8222146B2 (en) | 2004-06-10 | 2012-07-17 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
US8432037B2 (en) | 2004-06-10 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
US8749064B2 (en) | 2004-06-10 | 2014-06-10 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
JP2009246394A (en) * | 2009-07-27 | 2009-10-22 | Nec Corp | Manufacturing method of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US6559061B2 (en) | 2003-05-06 |
JP2002521842A (en) | 2002-07-16 |
US20020028576A1 (en) | 2002-03-07 |
US6709987B2 (en) | 2004-03-23 |
US6287977B1 (en) | 2001-09-11 |
WO2000007236A3 (en) | 2000-06-22 |
US20020115287A1 (en) | 2002-08-22 |
EP1246240A2 (en) | 2002-10-02 |
TW410431B (en) | 2000-11-01 |
US20040152301A1 (en) | 2004-08-05 |
US6992012B2 (en) | 2006-01-31 |
EP1099250A2 (en) | 2001-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6287977B1 (en) | Method and apparatus for forming improved metal interconnects | |
US7576002B2 (en) | Multi-step barrier deposition method | |
US6217721B1 (en) | Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer | |
US6238533B1 (en) | Integrated PVD system for aluminum hole filling using ionized metal adhesion layer | |
US7026238B2 (en) | Reliability barrier integration for Cu application | |
US6015749A (en) | Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure | |
US6949461B2 (en) | Method for depositing a metal layer on a semiconductor interconnect structure | |
US5918149A (en) | Deposition of a conductor in a via hole or trench | |
EP1570517B1 (en) | A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | |
EP0799903A2 (en) | Methods of sputtering a metal onto a substrate and semiconductor processing apparatus | |
US20010038886A1 (en) | Method of manufacturing semiconductor device | |
KR100501460B1 (en) | Method of filling holes in a semiconductor structure using an adhesion layer deposited from ionized metal | |
US6268284B1 (en) | In situ titanium aluminide deposit in high aspect ratio features | |
WO2002093648A2 (en) | Semiconductor device interconnect | |
US20030017696A1 (en) | Method for improving capability of metal filling in deep trench | |
JP2003258088A (en) | Semiconductor device, and method and apparatus for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP KR SG |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP KR SG |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1999937492 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1999937492 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1999937492 Country of ref document: EP |