WO2000005763A1 - Method of producing an interconnect structure for an integrated circuit - Google Patents
Method of producing an interconnect structure for an integrated circuit Download PDFInfo
- Publication number
- WO2000005763A1 WO2000005763A1 PCT/US1999/015073 US9915073W WO0005763A1 WO 2000005763 A1 WO2000005763 A1 WO 2000005763A1 US 9915073 W US9915073 W US 9915073W WO 0005763 A1 WO0005763 A1 WO 0005763A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulator layer
- trench
- photoresist
- layer
- mask
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000561658A JP2002521821A (en) | 1998-07-23 | 1999-07-01 | Method of manufacturing interconnect structure for integrated circuit |
DE69933933T DE69933933T2 (en) | 1998-07-23 | 1999-07-01 | METHOD FOR PRODUCING A LADDER TRACK STRUCTURE FOR INTEGRATED CIRCUIT |
EP99932210A EP1101247B1 (en) | 1998-07-23 | 1999-07-01 | Method of producing an interconnect structure for an integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/122,080 US6245662B1 (en) | 1998-07-23 | 1998-07-23 | Method of producing an interconnect structure for an integrated circuit |
US09/122,080 | 1998-07-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000005763A1 true WO2000005763A1 (en) | 2000-02-03 |
WO2000005763A9 WO2000005763A9 (en) | 2000-08-03 |
Family
ID=22400481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/015073 WO2000005763A1 (en) | 1998-07-23 | 1999-07-01 | Method of producing an interconnect structure for an integrated circuit |
Country Status (7)
Country | Link |
---|---|
US (2) | US6245662B1 (en) |
EP (1) | EP1101247B1 (en) |
JP (1) | JP2002521821A (en) |
KR (1) | KR100633979B1 (en) |
DE (1) | DE69933933T2 (en) |
TW (1) | TW457675B (en) |
WO (1) | WO2000005763A1 (en) |
Cited By (15)
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WO2001001480A1 (en) * | 1999-06-30 | 2001-01-04 | Intel Corporation | Method of protecting an underlying wiring layer during dual damascene processing |
GB2356973A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
EP1154468A2 (en) * | 2000-02-17 | 2001-11-14 | Applied Materials, Inc. | Method of depositing an amorphous carbon layer |
WO2001095382A2 (en) * | 2000-06-07 | 2001-12-13 | Infineon Technologies North America Corp. | Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow |
WO2002003457A2 (en) * | 2000-06-30 | 2002-01-10 | Infineon Technologies Ag | Via first dual damascene process for copper metallization |
US6406995B1 (en) | 1998-09-30 | 2002-06-18 | Intel Corporation | Pattern-sensitive deposition for damascene processing |
JP2002194547A (en) * | 2000-06-08 | 2002-07-10 | Applied Materials Inc | Method of depositing amorphous carbon layer |
US6649515B2 (en) | 1998-09-30 | 2003-11-18 | Intel Corporation | Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures |
EP1397830A2 (en) * | 2001-01-11 | 2004-03-17 | International Business Machines Corporation | Copper vias in low-k technology |
US6887645B2 (en) | 2000-08-31 | 2005-05-03 | Fuji Photo Film Co., Ltd. | Negative resist composition |
US7064078B2 (en) | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
US7094442B2 (en) | 2004-07-13 | 2006-08-22 | Applied Materials, Inc. | Methods for the reduction and elimination of particulate contamination with CVD of amorphous carbon |
US7407893B2 (en) | 2004-03-05 | 2008-08-05 | Applied Materials, Inc. | Liquid precursors for the CVD deposition of amorphous carbon films |
US7638440B2 (en) | 2004-03-12 | 2009-12-29 | Applied Materials, Inc. | Method of depositing an amorphous carbon film for etch hardmask application |
US9031685B2 (en) | 2001-07-27 | 2015-05-12 | Applied Materials, Inc. | Atomic layer deposition apparatus |
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US6429120B1 (en) | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6635583B2 (en) | 1998-10-01 | 2003-10-21 | Applied Materials, Inc. | Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating |
US6303972B1 (en) | 1998-11-25 | 2001-10-16 | Micron Technology, Inc. | Device including a conductive layer protected against oxidation |
US7067861B1 (en) * | 1998-11-25 | 2006-06-27 | Micron Technology, Inc. | Device and method for protecting against oxidation of a conductive layer in said device |
US7378740B2 (en) * | 1998-12-01 | 2008-05-27 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
US6936531B2 (en) | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6274478B1 (en) * | 1999-07-13 | 2001-08-14 | Motorola, Inc. | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
JP2001135723A (en) * | 1999-11-04 | 2001-05-18 | Nec Corp | Semiconductor device and method of manufacturing the same |
US6420262B1 (en) * | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US7262130B1 (en) * | 2000-01-18 | 2007-08-28 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6376370B1 (en) * | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6469775B1 (en) * | 2000-01-31 | 2002-10-22 | Micron Technology, Inc. | Reticle for creating resist-filled vias in a dual damascene process |
US6399478B2 (en) * | 2000-02-22 | 2002-06-04 | Sanyo Electric Co., Ltd. | Method of making a dual damascene structure with modified insulation |
ATE352869T1 (en) * | 2000-03-20 | 2007-02-15 | Koninkl Philips Electronics Nv | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION THEREOF |
US6576550B1 (en) | 2000-06-30 | 2003-06-10 | Infineon, Ag | ‘Via first’ dual damascene process for copper metallization |
US6846737B1 (en) * | 2000-08-15 | 2005-01-25 | Intel Corporation | Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials |
US6511912B1 (en) * | 2000-08-22 | 2003-01-28 | Micron Technology, Inc. | Method of forming a non-conformal layer over and exposing a trench |
US6395632B1 (en) * | 2000-08-31 | 2002-05-28 | Micron Technology, Inc. | Etch stop in damascene interconnect structure and method of making |
US6455432B1 (en) * | 2000-12-05 | 2002-09-24 | United Microelectronics Corp. | Method for removing carbon-rich particles adhered on a copper surface |
US6743732B1 (en) * | 2001-01-26 | 2004-06-01 | Taiwan Semiconductor Manufacturing Company | Organic low K dielectric etch with NH3 chemistry |
US6388330B1 (en) * | 2001-02-01 | 2002-05-14 | Advanced Micro Devices, Inc. | Low dielectric constant etch stop layers in integrated circuit interconnects |
US6372631B1 (en) * | 2001-02-07 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of making a via filled dual damascene structure without middle stop layer |
US6365505B1 (en) * | 2001-02-21 | 2002-04-02 | Advanced Micro Devices, Inc. | Method of making a slot via filled dual damascene structure with middle stop layer |
US6391766B1 (en) * | 2001-02-21 | 2002-05-21 | Advanced Micro Devices, Inc. | Method of making a slot via filled dual damascene structure with middle stop layer |
US20030008243A1 (en) * | 2001-07-09 | 2003-01-09 | Micron Technology, Inc. | Copper electroless deposition technology for ULSI metalization |
DE10154500B4 (en) * | 2001-11-07 | 2004-09-23 | Infineon Technologies Ag | Process for the production of thin, structured, metal-containing layers with low electrical resistance |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US7226853B2 (en) * | 2001-12-26 | 2007-06-05 | Applied Materials, Inc. | Method of forming a dual damascene structure utilizing a three layer hard mask structure |
US6806203B2 (en) | 2002-03-18 | 2004-10-19 | Applied Materials Inc. | Method of forming a dual damascene structure using an amorphous silicon hard mask |
US6635546B1 (en) * | 2002-05-16 | 2003-10-21 | Infineon Technologies Ag | Method and manufacturing MRAM offset cells in a damascene structure |
US6821905B2 (en) * | 2002-07-30 | 2004-11-23 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer |
DE10240176A1 (en) * | 2002-08-30 | 2004-04-29 | Advanced Micro Devices, Inc., Sunnyvale | A dielectric layer stack with a low dielectric constant including an etching indicator layer for use in dual damascene technology |
US6838372B2 (en) | 2002-09-25 | 2005-01-04 | Cookson Electronics, Inc. | Via interconnect forming process and electronic component product thereof |
US7071112B2 (en) * | 2002-10-21 | 2006-07-04 | Applied Materials, Inc. | BARC shaping for improved fabrication of dual damascene integrated circuit features |
US6917108B2 (en) | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
US7459790B2 (en) * | 2003-10-15 | 2008-12-02 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US20050253268A1 (en) * | 2004-04-22 | 2005-11-17 | Shao-Ta Hsu | Method and structure for improving adhesion between intermetal dielectric layer and cap layer |
US7078814B2 (en) * | 2004-05-25 | 2006-07-18 | International Business Machines Corporation | Method of forming a semiconductor device having air gaps and the structure so formed |
US7098105B2 (en) * | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US7339272B2 (en) * | 2004-06-14 | 2008-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with scattering bars adjacent conductive lines |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7442976B2 (en) * | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
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US7939482B2 (en) * | 2005-05-25 | 2011-05-10 | Freescale Semiconductor, Inc. | Cleaning solution for a semiconductor wafer |
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US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) * | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
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US8563229B2 (en) * | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US8298931B2 (en) * | 2007-09-28 | 2012-10-30 | Sandisk 3D Llc | Dual damascene with amorphous carbon for 3D deep via/trench application |
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KR100953729B1 (en) * | 2008-06-18 | 2010-04-19 | 서울시립대학교 산학협력단 | Method for reducing step for manufacturing stacked semiconductor module using cu over layer |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
DE102016104306B4 (en) | 2016-03-09 | 2020-04-09 | Infineon Technologies Ag | EXPANSION SENSOR OR REDUCING EXTENSION DRIFT OF A BRIDGE CIRCUIT |
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1998
- 1998-07-23 US US09/122,080 patent/US6245662B1/en not_active Expired - Fee Related
-
1999
- 1999-07-01 WO PCT/US1999/015073 patent/WO2000005763A1/en active IP Right Grant
- 1999-07-01 JP JP2000561658A patent/JP2002521821A/en active Pending
- 1999-07-01 DE DE69933933T patent/DE69933933T2/en not_active Expired - Fee Related
- 1999-07-01 KR KR1020017000966A patent/KR100633979B1/en not_active IP Right Cessation
- 1999-07-01 EP EP99932210A patent/EP1101247B1/en not_active Expired - Lifetime
- 1999-07-06 TW TW088111474A patent/TW457675B/en not_active IP Right Cessation
-
2001
- 2001-06-05 US US09/874,874 patent/US6548396B2/en not_active Expired - Fee Related
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EP0435187A2 (en) * | 1989-12-26 | 1991-07-03 | Fujitsu Limited | Method of fabricating a semiconductor device |
WO1997010612A1 (en) * | 1995-09-14 | 1997-03-20 | Advanced Micro Devices, Inc. | Damascene process for reduced feature size |
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Cited By (25)
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Publication number | Publication date |
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US6245662B1 (en) | 2001-06-12 |
KR20010072034A (en) | 2001-07-31 |
EP1101247B1 (en) | 2006-11-08 |
JP2002521821A (en) | 2002-07-16 |
US20020048929A1 (en) | 2002-04-25 |
WO2000005763A9 (en) | 2000-08-03 |
TW457675B (en) | 2001-10-01 |
US6548396B2 (en) | 2003-04-15 |
DE69933933T2 (en) | 2007-08-02 |
EP1101247A1 (en) | 2001-05-23 |
DE69933933D1 (en) | 2006-12-21 |
KR100633979B1 (en) | 2006-10-16 |
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