WO2000004586A1

WO2000004586A1 - Rare-earth electrical contacts for semiconductor devices

Info

Publication number: WO2000004586A1
Application number: PCT/US1999/012756
Authority: WO
Inventors: Ruey-Jen Hwu; Laurence P. Sadwick
Original assignee: The University Of Utah Research Foundation
Priority date: 1998-07-17
Filing date: 1999-06-07
Publication date: 2000-01-27

Abstract

Electrical contact to group III-V semiconductor materials used in fabricating semiconductor devices are provided. The electrical contacts are particularly suitable for high temperature electronic applications, and are fabricated by utilizing a substrate (10) or epitaxial layer made of a group III-V semiconductor material. A contact layer is formed on a surface of the substrate (10) or epitaxial layer, with the contact layer (14) composed of a rare earth compound such as dysprosium phosphide or dysprosium arsenide. A cap layer (16) of a group III-V semiconductor material can be formed on the contact layer (14).

Description

RARE-EARTH ELECTRICAL CONTACTS FOR SEMICONDUCTOR DEVICES

BACKGROUND OF THE INVENTION 1. The Field of the Invention

The present invention is related generally to electrical contacts to group III-V semiconductor compounds. More specifically, the present invention is related to contact materials including rare-earth elements alloyed with group V elements which are used to form electrical contacts to group III-V semiconductor devices. 2. The Relevant Technology

In the practical operation of any semiconductor device, it is necessary to supply current to the device and withdraw current from the device. Electrical contacts such as ohmic contacts are used to perform this function. In choosing an appropriate material for an electrical contact, there are several factors which should be taken into account. One factor which must be considered is the effective energy barrier to the flow of current which may exist when different materials are placed together in contact. If a metal is chosen having a suitable "work function", a material parameter which is directly related to energy levels of the metal with respect to a given reference energy level, then current will flow relatively easily to and from the semiconductor device. Semiconductor devices made from compounds of elements from groups III and

V of the periodic table of the elements are commonly used in applications ranging from transistors to photonic devices such as light emitting diodes (LEDs) and lasers. The III-V semiconductor compounds have properties which include high carrier mobility, which accounts for their fast response time, and a direct energy bandgap, which is in contrast to silicon semiconductors. The fact that many of the III-V semiconductor compounds have a direct energy bandgap is the major contributing factor to their efficiency in radiating systems such as LEDs and lasers, and is also the factor which determines the wavelength of emitted radiation. The III-V compounds, of which gallium arsenide (GaAs) is the prototypical example, can under proper conditions emit light in the red and infrared range, thereby making them suitable for applications such as optical fiber communications.

A problem with making good contacts to III-V "wide gap" semiconductors, such as GaAs and gallium nitride (GaN) for example, is that metals are hard to find that have a low enough work function to create a low energy barrier with respect to current flowing to and from the semiconductor device. The term "wide gap" refers to energy bandgaps in the range of about 1.4 to greater than about 3.4 eV. The relationship between the current density which can flow and the energy barrier height between the metal and semiconductor material in contact is given by the well known Schottky equation: J = A* T² exp (-q φ_b / k T) exp ((q V / k T) -1) where J is the current density, A* is the Richardson constant, k is Boltzmann's constant,

T is the operating temperature, q is the charge of the electron, φ_b is the energy barrier height between the metal and the semiconductor, and V is the applied voltage. It is apparent from this relationship that a large energy barrier drastically reduces the amount of current which can flow in the device. In view of this problem, contact materials formed of alloys of various metals and semiconductors have been investigated which have relatively low energy barriers with respect to the semiconductor. Compounds which have a low energy barrier, however, may not have a surface morphology which is conducive to the smooth interface required for reliable contact formation. This is particularly the case with gold and gold containing compounds.

Gold has been utilized with other metals to make electrical contacts to III-V semiconductor compounds. The main problem with gold compounds is that when they are subjected to the heat required for the alloying and contact formation process to the III- V semiconductor, the interface between the gold compounds and the III-V semiconductor becomes uneven and deteriorates, and can result in what is known as the "ball up" phenomenon. Gold has been observed to not withstand the high temperatures which are necessary for processing steps and which also inevitably occur in high power applications, wherein substantial amounts of heat are generated. Gold compounds also suffer from the tendency to form undesirable intermetallic compounds with the interconnection metal used in device settings, usually aluminum, resulting in a condition known as "purple plague."

Other materials have been experimented with to form contacts, including metals such as aluminum, silver, iron, and body-centered-cubic (BCC) cobalt; however, these metals have been proven to be thermodynamically unstable at relatively low temperatures. A different approach has been attempted with rare earth-arsenide compounds, such as ErAs and YbAs. These compounds have been shown to exhibit excellent material compatibility with III-V semiconductor devices and also good electrical characteristics from the point of view of Schottky contact formation.

The same types of problems exist with regard to finding suitable materials for high frequency Schottky barrier diodes, which may be considered to be a special type of contact, which only allow the flow of current in one direction. Such diodes have applications in the realm of microwave and millimeter wave devices, for example. Schottky diodes have been made with single crystal aluminum grown by molecular beam epitaxy on GaAs. These devices are apparently unstable at high temperatures and degrade under high power conditions.

Accordingly, there is a need to develop stable contact materials for III-V semiconductor compound devices, which can be used either as ohmic contacts or as Schottky diodes, depending upon the context of the application and the operating conditions. SUMMARY

The electrical contacts of the invention are fabricated by providing a substrate or epitaxial layer made of a group III-V semiconductor material such as gallium arsenide, gallium nitride, and the like. A contact layer is formed on a surface of the substrate or epitaxial layer with the contact layer composed of a rare-earth compound such as dysprosium phosphide or dysprosium arsenide. A cap layer of a group III-V semiconductor material can be formed on the contact layer.

The foregoing and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

In order to more fully understand the manner in which the above-recited and other advantages of the invention are obtained, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

Figures 1A-1C are cross-sectional schematic views showing successive structures formed during fabrication of an electrical contact for a semiconductor device according to the present invention;

Figure 2 is a schematic depiction of a molecular beam epitaxy system which can be utilized to form the electrical contact of the invention;

Figure 3 is a graph of the x-ray diffraction pattern of a GaAs substrate with a DyP epilayer thereon useful as an electrical contact according to the present invention; Figure 4 is a graph of the of the resistivity with respect to the Hall temperature for a DyP contact on a GaAs substrate according to the present invention;

Figure 5 is a graph of the mobility with respect to the Hall temperature for a DyP contact on a GaAs substrate according to the present invention;

Figure 6 is a graph of the current with respect to the voltage for DyP/GaAs Schottky diodes of the present invention.

Figure 7 is a graph of the barrier height with respect to the temperature for DyP/GaAs Schottky diodes of the present invention;

Figure 8 is a graph of the saturation current with respect to the temperature for DyP/GaAs Schottky diodes of the present invention; Figure 9 is a graph of the capacitance (C) with respect to voltage for DyP/GaAs

Schottky diodes of the present invention;

Figure 10 is a graph of 1/C² with respect to voltage for DyP/GaAs Schottky diodes of the present invention;

Figure 11 is a graph of the x-ray diffraction pattern of a GaAs substrate with a DyAs epilayer thereon useful as an electrical contact according to the present invention; and

Figure 12 is a graph of the mobility and resistivity with respect to the Hall temperature for DyP and DyAs contacts of the present invention.

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to electrical contacts for electrical connection to group III-V semiconductor compounds used in fabricating semiconductor devices. The electrical contacts of the invention, which can be employed as ohmic contacts or Schottky contacts, are particularly suitable for semiconductor device applications such as high power semiconductor lasers, or other high temperature or high frequency applications such as in electronic devices used in automotive and aerospace technologies.

As used herein, the term "ohmic contact" refers to a region where two materials are in contact, such as at the junction of a group III-V semiconductor substrate and a metallic layer thereon, which has the property that the current flowing through the region is substantially proportional to the potential difference or voltage across the region. The term "Schottky diode" refers to a region, such as the junction of a group III-V semiconductor substrate and a metallic layer thereon, which has a nonlinear rectifying characteristic such that current flows through the region substantially more in one direction than in the opposite direction when a certain voltage is applied. The development of thermally stable electrical contacts is one of the most challenging tasks for the development of III-V semiconductor devices for high temperature and high power applications. When thin metal films are exposed to high temperatures during fabrication or operation, interface reactions between the metal and semiconductor can take place that results in changes in the electrical properties of the contacts. Reliability considerations also require that the contacts and the metal semiconductor barriers be able to withstand harsh environments for relatively long periods of time without degradation.

Hence, there is a need for thermally and morphologically stable electrical contacts to the III-V semiconductors, which are prevalent in optoelectronic devices. Contacts which exhibit thermal stability at temperatures in excess of about 400 °C to about 500°C for long periods of time without degradation and formation of undesirable compounds would be extremely useful in the enhanced development of III-V semiconductor devices used in high power applications. The contact materials of the present invention provide such properties.

The materials used to form the electrical contacts of the invention are selected from rare-earth III-V binary compounds such as dysprosium phosphide, dysprosium arsenide, and the like. These compounds have high melting temperatures (e.g., greater than about 2000 °C), making them useful in forming contacts for high temperature applications. The contacts formed with these rare-earth compounds are thermodynamically stable and chemically inert. The high melting temperature of rare- earth/group V compounds such as dysprosium phosphide (DyP) and dysprosium arsenide (DyAs) make them useful contacts to III-V semiconductor compounds used in high power and high temperature electronic devices. The electrical contacts of the present invention are particularly useful with group

III-V semiconductor materials such as gallium arsenide, gallium nitride, gallium phosphide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, and the like. The group III-V semiconductor materials are preferably n-type or p-type semiconductor materials that have an appropriate doping concentration or are undoped. Referring to the drawings, wherein like structures are provided with like reference designations, Figures 1A-1C are cross-sectional schematic views showing successive structures formed during fabrication of an electrical contact from rare-earth compounds according to the present invention for a semiconductor device. These drawings only show the structures necessary to understand the present invention. Additional structures known in the art have not been included to maintain the clarity of the drawings. While the drawings depict the formation of a single electrical contact on a substrate, it should be understood that a plurality of such contacts can be formed during fabrication of a semiconductor device.

Figure 1A illustrates a semiconductor epitaxial layer or substrate 10 used in fabricating a semiconductor device. The epitaxial layer or substrate 10 has a first major surface 12 and is composed of a group III-V semiconductor material such as gallium arsenide, gallium nitride, gallium phosphide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, and the like.

As shown in Figure IB, a rare-earth contact layer 14 is formed on surface 12 of substrate 10 by a conventional deposition process such as molecular beam epitaxy

(MBE), electron-beam evaporation, sputtering, or other known technique. The MBE technique is particularly useful in achieving precise growth of layers of III-V semiconductor compounds. The contact layer 14 is formed to have a thickness in the range from about 100 Angstroms to about 15000 Angstroms, and preferably from about 5000 Angstroms to about 10000 Angstroms. The formed contact layer 14 can be composed of dysprosium phosphide, dysprosium arsenide, or other like rare-earth compounds.

In further optional processing, a buffer or cap layer can be formed over the contact layer by conventional deposition techniques. The buffer or cap layer prevents degradation of the contact layer, allowing the contact layer to retain its properties of thermal stability, electrical stability, and surface uniformity.

As shown in Figure 1C, a cap layer 16 is formed over contact layer 14. The cap layer 16 is formed by conventional deposition techniques such as vacuum deposition or sputtering and is formed to have a thickness in the range from about 100 Angstroms to about 10000 Angstroms, and preferably from about 2000 Angstroms to about 5000

Angstroms. The cap layer 16 is preferably made from the same group III-V semiconductor material as substrate 10, such as gallium arsenide, gallium phosphide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, and the like.

Figure 2 is a schematic depiction of an MBE system 20 which can be utilized to form contact layer 14 on substrate 10. The system 20 includes a central chamber 22 with a heating element 24 on which substrate 10 is placed. A gate valve 26 allows for vacuum conditions to be obtained in chamber 22 during operation of system 22 for layer growth. A load lock 27 is in communication with gate valve 26 at the exterior of system 20 and provides an air-tight seal for chamber 22 during operation of system 20. The chamber 22 is in communication with a high temperature effusion cell 28 which is provided with a source of a rare-earth element such as dysprosium for evaporation thereof into chamber 22. The chamber 22 is also in communication with a thermal cracker cell 30 which is provided with a source of a Group V element such as phosphorus or arsenic for evaporation thereof into chamber 22. A residual gas analyzer 32 and an ion gage 34 are also in communication with chamber 22 and allow the partial pressures of the gases from effusion cell 28 and cracker cell 30 to be monitored during growth of contact layer 12 on substrate 10.

During operation of MBE system 20 in order to form a contact layer on a semiconductor substrate, a substrate 10 composed of a III-V semiconductor compound such as gallium arsenide (GaAs) is placed in chamber 22 on heating element 24, which can have a temperature from about 450°C to about 520°C. The gate valve 26 is then closed in order to perform the layer growth under vacuum conditions to ensure purity of the layer. The effusion cell 28 is heated to a temperature of about 1150° to about 1250°C in order to evaporate the rare earth element such as dysprosium therein. The cracker cell 30 is heated to a temperature of about 750° to about 850°C in order to evaporate a group

V element such as phosphorous or arsenic. The phosphorus can be obtained from various sources such as tertiarybutylphosphine (TBP) or a solid phosphorous source. During growth of contact layer 12, dysprosium phosphide (DyP) or dysprosium arsenide (DyAs) are formed, and the partial pressures of the phosphorous or arsenic gases are monitored using residual gas analyzer 32 and ion gage 34. The cool down rate of the coated substrate after the growth cycle has a strong effect on the surface morphology, and a slower rate of cooling decreases the number of structural defects in contact layer 12.

The resulting crystallographic orientations of the DyP or DyAs epilayers following growth on GaAs is (001), with DyAs having a slightly higher degree of surface roughness due to the inherent lattice mismatch between DyAs and GaAs. However, the lattice mismatch between DyP and GaAs at room temperature is less than 0.01%, which greatly contributes to a smooth interface, thereby enhancing electrical contact reliability and overall performance.

The electrical contacts of the present invention for group III-V semiconductor devices provide many advantages and benefits. The contacts are thermally stable in high temperature and high power device applications, and are particularly useful in semiconductor devices of higher band gaps. The contacts are also compatible with large scale integrated device fabrication technology. The electrical contacts of the invention are particularly suitable for high temperature electronic applications, since the contact materials of the invention can withstand high temperature and high power conditions. The electrical contacts can thus be utilized in electronic devices employed in the automotive industry, in the aerospace industry such as in space vehicles and exploration, in the nuclear power industry, and in petroleum exploration.

The contact materials of the invention are also useful in forming Schottky diodes for high temperature and high frequency applications. Schottky diodes are frequently used in microwave and millimeter wave devices because of the relative simplicity of their fabrication and the inherent low carrier storage time which permits high frequency operation.

The following examples are given to illustrate the present invention, and are not intended to limit the scope of the invention.

Example 1 Electrical contacts having high temperature stability were prepared according to the following procedures. Sample substrates of undoped, semi-insulating (001) gallium arsenide (GaAs) were solvent degreased and cleaned following standard procedures. The substrates were chemically etched in a solution of 12:2:1 H₂O : NH₄OH : H₂O₂ or in a solution of 4: 1 : 1 H₂SO₄ : H₂O₂ : H₂O, and rinsed in deionized (DI) water. Prior to crystal growth, the substrates were heated to 600 °C to remove the native oxides.

An MBE system such as shown in Figure 2 was utilized to grow contact layers on the substrates. The MBE system was equipped with a 2200 L/s diffusion pump and a liquid nitrogen cooled trap. The lowest pressure the system achieved was about 5x10^"9 Torr. Dysprosium (Dy) was evaporated from a high temperature effusion cell containing 99.9% pure Dy. The phosphorus (P) flux was obtained from tertiarybutylphosphine

(TBP) or solid phosphorus using a custom-designed thermal cracker cell. The temperatures of the Dy effusion cell and the P cracker cell were raised up to 1150°- 1250°C and 750°-850°C, respectively, during epilayer growth. The TBP flow rate was 0.265-0.400 seem. The substrate temperatures ranged from 450°-520° C. The dysprosium phosphide (DyP) growth rate achieved was about 1.39-3.33

Angstroms(A)/sec, as determined from film thickness measurements. During growth of DyP, the partial pressure of P and P₂ were monitored using a residual gas analyzer (RGA).

The cool down rate of the sample substrates after the growth cycle was found to affect the surface morphology possibly due to the differences in thermal expansion coefficients of DyP and GaAs. A high rate of cool down resulted in slip plane formation. In general, comparable results were obtained using either TBP or solid phosphorus. However, solid P-grown DyP gave results that were more reproducible than those of TBP-grown samples.

The formed DyP epilayers were characterized by two theta and double crystal X- ray diffraction, as well as variable temperature Hall and resistivity measurements.

The x-ray diffraction (XRD) patterns of GaAs with a solid P-grown DyP epilayer is shown in the graph of Figure 3 and was obtained using a Philips APD 3720 diffractometer equipped with a monochromator adjusted for CuK^ (λ=l.54183 A) and driven by a stepper motor. The samples were scanned from 25° to 70° 2Θ. The x-ray data showed a very good quality, single crystal (001) DyP epilayer on the GaAs (001) substrate for substrate temperatures in the range of 475°-520°C.

The d-spacing, structure factor and 2Θ values for (002) and (004) planes for GaAs and DyP are shown in Table 1. From Table 1 , the approximate intensity ratios of (002) to (004) peaks of GaAs and DyP are 1:138 and 4:1, respectively. Since the intensity (measured in arbitrary units (a.u.)) of the (002) peak compared to the (004) peak for GaAs is very weak, the peak at 31.65 ° in the XRD pattern is due to the DyP epilayer as shown in Figure 3. Table 1

X-ray parameters for GaAs and DyP

(hkl) 2Θ d(A) structure factor (f)

GaAs (002) 31.6539° 2.8266 1.83

GaAs (004) 66.1129° 1.4133 21.48

DyP (002) 31.6533° 2.8265 42.30

DyP (004) 66.1115° 1.4132 21.48

The growth rate was found to be independent of substrate temperature. As expected from conventional MBE, the growth rate increased with increasing Dy effusion cell temperature and was independent of the phosphorus flux rate over a wide range of growth rates.

The electrical characterization of the sample substrates consisted of four-point probe, variable temperature Hall measurements, C-V measurements, and variable temperature I-V measurements performed on solid P-grown DyP. The Hall measurements were performed at temperatures between 300 K and 77 K. The resistivity values of DyP determined by four-point probe and Hall measurement methods were found to be consistent with each other and were in the range of 6.5xl0^"5 to 1.5xl0^"4 Ω-cm. A graph of the resistivity with respect to the Hall temperature is shown in Figure 4 for films having a thickness (t) of 0.8 and 0.7 microns. The Hall measurements indicated that the

DyP films were n-type with electron carrier concentrations on the order of 3x10²⁰ to 4x10²⁰ cm^"3. The room temperature mobility was found to be between 250 and 300 cm²/V-s and increased with decreasing Hall temperature. A graph of the mobility with respect to the Hall temperature is shown in Figure 5. The carrier mobility was found to increase with increasing epilayer thickness. This phenomena is probably related to the presence of impurities at the DyP/GaAs heterointerface.

Preliminary optical characterization was performed on the formed DyP layers using photothermal deflection spectroscopy (PDS). The samples were scanned from 2 to 0.5 eV photon energy and no appreciable absorption edge was found, which is consistent with the DyP material being a semi-metal. Electrical, optical, and magnetotransport measurements indicated that the formed DyP was a semi-metal.

The DyP layers were found to be stable in air and showed no signs of oxidation even after months of exposure to ambient air. It was also found that the lattice mismatch between DyP and GaAs was less than 0.01% at room temperature. Example 2

Electrical contacts formed of DyP were prepared on sample substrates of GaAs according to the procedures set forth in Example 1. An additional patterned layer of gold-germanium-nickel (Au-Ge-Ni) alloy was formed on the sample substrates by a conventional deposition process. The DyP layer was used as a Schottky contact and the Au-Ge-Ni layer was used as an ohmic contact in order to perform current-voltage (I-V) measurements for the DyP layer. The I-V measurements were done from 25 °C to 315 °C. The test showed the DyP layer to have an excellent rectifying action. The turn-on voltages at certain temperatures and their corresponding barrier heights are given in Table 2 below. TABLE 2

Temperature f°C) Turn-on voltage (V) Barrier height feV

25 0.23 0.7242

115 0.12 0.5523

225 0.08 0.4370 315 0.02 0.3683 The samples were then subjected to a heat test. The samples were left at 225 °C for 15 hours and then the I-V test was repeated. The results are tabulated in Table 3 below, showing the barrier heights measured before and after the heat test.

TABLE 3

Barrier height CeV

Temperature CO Before After

25 0.7242 0.7105

225 0.4370 0.4286

The results obtained after the heat test were found to be fairly consistent with the previous set of results. There was little deviation in the I-V characteristic as a result of the prolonged period of heating, with little difference observed in the values for the barrier height before and after the test, thereby demonstrating a degree of temperature stability. This indicates that the DyP contact layer has excellent potential for use in high temperature applications.

Example 3 Electrical contacts formed of DyP were prepared on sample substrates of GaAs according to the procedures set forth in Example 1 , in order to perform characterization studies to evaluate the DyP/GaAs structures for use as Schottky diodes for high temperatures and high frequency applications. The DyP/GaAs Schottky diodes were fabricated with an area of 40,000 μm². Electrical characterization including current- voltage (I-V) and capacitance-voltage (C-V) measurements were performed at different temperatures ranging from 25°C to 250°C. High frequency characterization was performed by measuring the scattering parameters (S parameters) of these Schottky diodes as functions of frequency.

Figure 6 shows a graph of the current with respect to the voltage for the DyP/GaAs Schottky diodes at temperatures from 25 °C to 200 °C. From the I-V data obtained, rectifying behavior was observed from 25 °C to close to 200° C, and a barrier height of approximately 0.81 eV was found at room temperature. The barrier height (V_b), as expected, decreases as temperature increases, as shown in the graph of Figure 7. The saturation current (I_s) increases dramatically as the temperature increases, as shown in the graph of Figure 8. Since the rectifying behavior is present at relatively high temperatures, this suggests the application of DyP as a practical choice for high temperature Schottky diodes. Such Schottky diodes can be used in high temperature RF detectors and mixers. The C-V measurements were performed at different temperatures ranging from 25°C to 250°C. From the data obtained, the C-V curves depicted in the graph of Figure 9 show little change with temperatures ranging from 25°C to 250° C, and display a C_max/C_min ratio of close to 3. The 1/C² -voltage curve was plotted from the room temperature C-V data and is shown in the graph of Figure 10. A uniform doping of

2.3x10¹⁷ cm^"3 was obtained from this plot, which agrees very well with the results given by other measurements. The well-behaved C-V curves at elevated temperatures demonstrate the potential use of these Schottky diodes as high power frequency multipliers. High frequency characterization of DyP/GaAs Schottky diodes were conducted using an HP vector network analyzer with a frequency capability of 45 MHz to 40 GHz. The equivalent circuit was constructed and the component parameters were obtained from Touchstone/Libra using the S-parameters from the high frequency measurement data. Based on these parameters, the cut-off frequency of the Schottky diodes with an area of 10 μm² was determined to be close to 2.5 THz. The cut-off frequency of these diodes can be improved through the manipulation of the doping of GaAs, device layout, etc.

Example 4 Electrical contacts formed of DyP and dysprosium arsenide (DyAs) were prepared on sample substrates of GaAs according to similar procedures as set forth in Example 1. Accordingly, the growth of DyP and DyAs on the substrates was performed on an MBE system equipped with a 2200 L/sec diffusion pump and a liquid nitrogen cooled trap. The background pressure of the system was about 5x10^"9 Torr. The Dy was evaporated from a high temperature effusion cell containing 99.99% pure Dy. The P and Arsenic (As) fluxes were obtained from solid phosphorus or arsenic using custom designed thermal cracker cells. The substrates were undoped, semi-insulating (001)

GaAs. Substrate preparation included solvent degreasing, 12:2:1 H₂O:NH₄OH:H₂O₂ etching, and DI water rinsing. The native oxide was desorbed at about 610°C with an impinging As₂ flux prior to the epilayer growth. An undoped GaAs buffer or cap layer was grown over the DyP layer on the GaAs substrate. The substrate temperatures used for DyP and DyAs growth ranged from 450°C to 600°C. with growth rates of 0.5 to 0.7 μm/hr, as determined from film thickness measurements.

The formed DyP and DyAs epilayers were characterized by two theta and double crystal X-ray diffraction, as well as variable temperature Hall and resistivity measurements. The XRD data showed very good quality (001) DyP and (001) DyAs epilayers on GaAs for substrate temperatures in the range of 500°C to 600°C. The XRD pattern of GaAs with a DyAs epilayer is shown in Figure 11. No pinholes in the DyP layers were observed in cross-section samples. In spite of the good growth of DyP on GaAs, the GaAs buffer layer grown on top of the DyP was usually twinned. Most of the top GaAs layer grew epitactically aligned with DyP/GaAs but there were areas where (111) GaAs grew on (001 ) DyP.

The Auger electron spectroscopy (AES) profile indicated abrupt interfaces with no significant impurities present in any of the layers. The tapping mode atomic force microscopy (AFM) analysis of DyP/GaAs revealed a smooth surface with root mean square (RMS) roughness between 4-8 A. The surface roughness of DyAs was between 10- 15 A, and may have been due to the larger lattice mismatch between DyAs and GaAs.

The electrical characterization of the DyP layer included four-point probe, variable temperature Hall measurements, and room temperature I-V measurements. The

Hall measurements were performed at temperatures between 300 K and 77 K. The resistivity values of DyP as determined by four-point probe and Hall measurement methods were found to be consistent and were in the range of 6.5x10^"5 to 1.5x10^"4 Ω -cm.

The Hall measurements indicate that DyP films are n-type with electron concentrations on the order of 3xl0²⁰ to 4xl0²⁰ cm^"3. The room temperature mobility was between 250 and 300 cm²/Vs and increased with a decrease in temperature. A graph of the resistivity and mobility with respect to the Hall temperature is shown in Figure 12. In addition, I-V measurements were performed with the DyP layer used as a

Schottky contact and a patterned Au-Ge-Ni layer used as an ohmic contact. The corresponding barrier height was found to be 0.75 eV.

The optical characterization the DyP was performed using photothermal deflection spectroscopy (PDS) and Fourier transform infrared spectroscopy (FTIR). The sample was scanned from 2 to 0.5 eV using PDS and from 0.5 to 0.2 eV using FTIR. No definitive absorption edge was found during either scan. This indicates the absence of a bandgap and is consistent with the material being a semi-metal.

For DyAs, the Hall measurements were performed between 300 K and 20 K. The resistivity was found to be in the region of l.OxlO^"4 to 1.5xl0^'4 Ω-cm, as shown in Figure 7. The DyAs was also found to be n-type with carrier concentration of the order of lxl 0²¹ to 2x10²¹ cm^"3. As a result of this high carrier concentration, the mobilities were between 25 and 40 cm²/Vs, and showed an increase with the decrease in temperature as shown in Figure 7. The DyAs layers were found to be fairly stable in air up to 300°C. The contact materials of the invention, including DyP and DyAs, due in part to their high temperature stability, their resistance to oxidation, and their ability to form a smooth interface with GaAs, have been demonstrated in accordance with the present invention to perform well as electrical contacts to III-V semiconductor devices, and also as Schottky diodes for high temperature and high frequency applications. The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

What is claimed is:

Claims

I . A semiconductor device, comprising: a substrate or epitaxial layer of a group III-V semiconductor material; and an electrical contact layer on a surface of the substrate or the epitaxial layer, the electrical contact layer comprising dysprosium phosphide.

2. The device of claim 1 , wherein the semiconductor material of the substrate or the epitaxial layer is selected from the group consisting of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium gallium arsenide, and aluminum gallium arsenide.

3. The device of claim 1, wherein the contact layer has a thickness from about 100 Angstroms to about 15000 Angstroms.

4. The device of claim 1, wherein the contact layer forms a Schottky diode.

5. The device of claim 1, further comprising a cap layer of a group III-V semiconductor material on the contact layer.

6. The device of claim 5, wherein the cap layer has a thickness from about

100 Angstroms to about 10000 Angstroms.

7. A semiconductor device, comprising: a substrate or epitaxial layer of a group III-V semiconductor material; and an electrical contact layer on a surface of the substrate or the epitaxial layer, the electrical contact layer comprising dysprosium arsenide.

8. The device of claim 7, wherein the semiconductor material is selected from the group consisting of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium gallium arsenide, and aluminum gallium arsenide.

9. The device of claim 7, wherein the contact layer has a thickness from about 100 Angstroms to about 15000 Angstroms.

10. The device of claim 7, wherein the contact layer forms a Schottky diode.

I I . The device of claim 7, further comprising a cap layer of a group III-V semiconductor material on the contact layer.

12. The device of claim 11, wherein the cap layer has a thickness from about

100 Angstroms to about 10000 Angstroms.

13. A method of fabricating an electrical contact for a semiconductor device, comprising the steps of: providing a substrate or epitaxial layer of a group III-V semiconductor material; and forming a contact layer on a surface of the substrate or the epitaxial layer, the contact layer comprising a rare-earth compound selected from the group consisting of dysprosium phosphide and dysprosium arsenide.

14. The method of claim 13, wherein the semiconductor material of the substrate or the epitaxial layer is selected from the group consisting of gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium gallium arsenide, and aluminum gallium arsenide.

15. The method of claim 13, wherein the contact layer is formed to have a thickness from about 100 Angstroms to about 15000 Angstroms.

16. The method of claim 13 , wherein the contact layer is formed by molecular beam epitaxy.

17. The method of claim 13, wherein the contact layer is formed by evaporating dysprosium and phosphorus onto a surface of the substrate or the epitaxial layer.

18. The method of claim 13, wherein the contact layer is formed by evaporating dysprosium and arsenic onto a surface of the substrate or the epitaxial layer.

19. The method of claim 13, further comprising the step of forming a cap layer of a group III-V semiconductor material on the contact layer.

20. The method of claim 19, wherein the cap layer is formed to have a thickness from about 100 Angstroms to about 10000 Angstroms.