WO1999059088A3 - A programmable logic device with macrocell controlled by a pla - Google Patents
A programmable logic device with macrocell controlled by a pla Download PDFInfo
- Publication number
- WO1999059088A3 WO1999059088A3 PCT/IB1999/000783 IB9900783W WO9959088A3 WO 1999059088 A3 WO1999059088 A3 WO 1999059088A3 IB 9900783 W IB9900783 W IB 9900783W WO 9959088 A3 WO9959088 A3 WO 9959088A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pla
- terms
- logic
- macrocell
- programmable logic
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Abstract
A programmable logic device (PLD) includes a macrocell which controls the output path of the logic signals output by one or more logic arrays implementing user logic functions. Complex control terms are implemented and provided to the macrocell by a programmable logic array (PLA), which includes at least one (and typically a plurality) of Sum terms (OR gates) electrically programmably coupled to a plurality of Product terms (AND gates) receiving input logic signals. In a favorable embodiment, the PLD includes a plurality of macrocells coupled via a communication channel to the PLA which generates the control terms. The PLA has the advantage of improving density and flexibility, so that complex control terms may be implemented without the need to implement multiple paths through the user logic arrays, thereby avoiding decreases in speed and poaching of capacity from the user logic arrays.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7568098A | 1998-05-11 | 1998-05-11 | |
US09/075,680 | 1998-05-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999059088A2 WO1999059088A2 (en) | 1999-11-18 |
WO1999059088A3 true WO1999059088A3 (en) | 2000-01-20 |
Family
ID=22127320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1999/000783 WO1999059088A2 (en) | 1998-05-11 | 1999-04-29 | A programmable logic device with macrocell controlled by a pla |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1999059088A2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0252654A2 (en) * | 1986-07-02 | 1988-01-13 | Advanced Micro Devices, Inc. | Memory device with programmable output structures |
US4847612A (en) * | 1988-01-13 | 1989-07-11 | Plug Logic, Inc. | Programmable logic device |
-
1999
- 1999-04-29 WO PCT/IB1999/000783 patent/WO1999059088A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0252654A2 (en) * | 1986-07-02 | 1988-01-13 | Advanced Micro Devices, Inc. | Memory device with programmable output structures |
US4847612A (en) * | 1988-01-13 | 1989-07-11 | Plug Logic, Inc. | Programmable logic device |
Also Published As
Publication number | Publication date |
---|---|
WO1999059088A2 (en) | 1999-11-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5592106A (en) | Programmable logic array integrated circuits with interconnection conductors of overlapping extent | |
US5705939A (en) | Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors | |
US5543732A (en) | Programmable logic array devices with interconnect lines of various lengths | |
US5399922A (en) | Macrocell comprised of two look-up tables and two flip-flops | |
US5541530A (en) | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks | |
US6396304B2 (en) | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks | |
US5341044A (en) | Flexible configuration logic array block for programmable logic devices | |
US6636070B1 (en) | Driver circuitry for programmable logic devices with hierarchical interconnection resources | |
US5900743A (en) | Programmable logic array devices with interconnect lines of various lengths | |
US5473266A (en) | Programmable logic device having fast programmable logic array blocks and a central global interconnect array | |
US6049225A (en) | Input/output interface circuitry for programmable logic array integrated circuit devices | |
US5015884A (en) | Multiple array high performance programmable logic device family | |
US5444394A (en) | PLD with selective inputs from local and global conductors | |
US4903223A (en) | Programmable logic device with programmable word line connections | |
EP0759662A3 (en) | Time multiplexed programmable logic device | |
JP2012044708A (en) | Interconnection and input/output resources for programmable logic integrated circuit devices | |
US6605959B1 (en) | Structure and method for implementing wide multiplexers | |
WO1999059088A3 (en) | A programmable logic device with macrocell controlled by a pla | |
US5565793A (en) | Programmable logic array integrated circuit devices with regions of enhanced interconnectivity | |
US6107825A (en) | Input/output circuitry for programmable logic devices | |
US6833730B1 (en) | PLD configurable logic block enabling the rapid calculation of sum-of-products functions | |
US5872463A (en) | Routing in programmable logic devices using shared distributed programmable logic connectors | |
US7119575B1 (en) | Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency | |
US7432733B1 (en) | Multi-level routing architecture in a field programmable gate array having transmitters and receivers | |
US5684413A (en) | Condensed single block PLA plus PAL architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
NENP | Non-entry into the national phase |
Ref country code: KR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
122 | Ep: pct application non-entry in european phase |