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Publication numberWO1999044147 A3
Publication typeApplication
Application numberPCT/DE1999/000504
Publication date28 Oct 1999
Filing date25 Feb 1999
Priority date25 Feb 1998
Also published asCA2321874A1, CA2321877A1, CN1298520A, CN1298521A, DE19807872A1, DE19980309D2, DE19980312D2, EP1057102A2, EP1057102B1, EP1057117A2, EP1057117B1, EP1164474A2, EP1164474A3, EP2293193A1, US6480937, US6571381, US6687788, US20030074518, WO1999044120A2, WO1999044120A3, WO1999044147A2
Publication numberPCT/1999/504, PCT/DE/1999/000504, PCT/DE/1999/00504, PCT/DE/99/000504, PCT/DE/99/00504, PCT/DE1999/000504, PCT/DE1999/00504, PCT/DE1999000504, PCT/DE199900504, PCT/DE99/000504, PCT/DE99/00504, PCT/DE99000504, PCT/DE9900504, WO 1999/044147 A3, WO 1999044147 A3, WO 1999044147A3, WO 9944147 A3, WO 9944147A3, WO-A3-1999044147, WO-A3-9944147, WO1999/044147A3, WO1999044147 A3, WO1999044147A3, WO9944147 A3, WO9944147A3
InventorsRobert Muench, Martin Vorbach
ApplicantRobert Muench, Pact Inf Tech Gmbh, Martin Vorbach
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
WO 1999044147 A3
Abstract
Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. The tree structure of the configuration units enables a kind of cacheing of the configuration data. The configurations are mainly accessed locally. In the worst case scenario, a configuration has to be loaded from the higher-order configuration memory in case the relative data are not available in any of the CTs (configuration tables) in the hierarchy.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
EP0686915A2 *24 May 199513 Dec 1995Nec CorporationHierarchical resource management method
EP0707269A1 *27 Sep 199517 Apr 1996International Business Machines CorporationCache coherence network for a multiprocessor data processing system
US4860201 *2 Sep 198622 Aug 1989The Trustees Of Columbia University In The City Of New YorkBinary tree parallel processor
Non-Patent Citations
Reference
1 *WADA K ET AL: "A PERFORMANCE EVALUATION OF TREE-BASED COHERENT DISTRIBUTED SHARED MEMORY", PROCEEDINGS OF THE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUT AND SIGNAL PROCESSING, VICTORIA, MAY 19 - 21, 1993, vol. 2, 19 May 1993 (1993-05-19), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 390 - 393, XP000419298
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US88691217 Jul 201121 Oct 2014Pact Xpp Technologies AgMethod for the translation of programs for reconfigurable architectures
US891459030 Sep 200916 Dec 2014Pact Xpp Technologies AgData processing method and device
USRE4522321 Oct 201028 Oct 2014Pact Xpp Technologies AgMethod of self-synchronization of configurable elements of a programmable module
Classifications
International ClassificationG06F12/08, G06F15/78, G06F15/82, H03K19/173
Cooperative ClassificationG06F12/0811, G06F12/084, G06F12/0813, G06F15/7867
European ClassificationG06F12/08B4L, G06F12/08B4N, G06F12/08B4S, G06F15/78R
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