WO1999044120A3 - VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.) - Google Patents

VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.) Download PDF

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Publication number
WO1999044120A3
WO1999044120A3 PCT/DE1999/000505 DE9900505W WO9944120A3 WO 1999044120 A3 WO1999044120 A3 WO 1999044120A3 DE 9900505 W DE9900505 W DE 9900505W WO 9944120 A3 WO9944120 A3 WO 9944120A3
Authority
WO
WIPO (PCT)
Prior art keywords
deadlocks
configurations
dpgas
fpgas
modules
Prior art date
Application number
PCT/DE1999/000505
Other languages
English (en)
French (fr)
Other versions
WO1999044120A2 (de
Inventor
Martin Vorbach
Robert Muench
Original Assignee
Pact Inf Tech Gmbh
Martin Vorbach
Robert Muench
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pact Inf Tech Gmbh, Martin Vorbach, Robert Muench filed Critical Pact Inf Tech Gmbh
Priority to AT99914430T priority Critical patent/ATE217713T1/de
Priority to EA200000880A priority patent/EA003407B1/ru
Priority to JP2000533804A priority patent/JP4338308B2/ja
Priority to DE19980309T priority patent/DE19980309D2/de
Priority to EP99914430A priority patent/EP1057102B1/de
Priority to AU33262/99A priority patent/AU3326299A/en
Priority to CA002321874A priority patent/CA2321874A1/en
Priority to US09/623,113 priority patent/US6571381B1/en
Priority to DE59901446T priority patent/DE59901446D1/de
Publication of WO1999044120A2 publication Critical patent/WO1999044120A2/de
Publication of WO1999044120A3 publication Critical patent/WO1999044120A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Abstract

Anstatt wie bisher eine zentrale und globale Einheit in einen Baustein zu integrieren, welche alle Konfigurations-Anforderungen bearbeitet, existieren nun eine Mehrzahl von hierarchisch angeordneten aktiven Einheiten, welche diese Aufgabe übernehmen können. Dabei wird eine Anforderung von der tiefsten Ebene nur dann an die nächst höher gelegene Ebene weitergeleitet, wenn die Anforderung nicht bearbeitet werden konnte. Die höchst gelegene Ebene ist an einen internen oder externen übergeordneten Konfigurationsspeicher angeschlossen, der alle jemals für diesen Programmlauf benötigten Konfigurationsdaten enthält. Deadlocks werden verhindert, indem eine feste zeitliche Abfolge der zu ladenden Konfigurationen eingeführt wird und die Konfigurationen zu einer Liste zusammengefasst werden. Die Statusinformationen der CEL werden vor dem Laden gesichert und bleiben dadurch während des Abarbeitens der gesamten Liste von Konfigurationen unverändert.
PCT/DE1999/000505 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.) WO1999044120A2 (de)

Priority Applications (9)

Application Number Priority Date Filing Date Title
AT99914430T ATE217713T1 (de) 1998-02-25 1999-02-25 Verfahren zur deadlockfreien konfiguration von datenflussprozessoren und bausteinen mit zwei- oder mehrdimensionaler programmierbarer zellstruktur (fpgas, dpgas, o. dgl.)
EA200000880A EA003407B1 (ru) 1998-02-25 1999-02-25 Способ исключающего взаимоблокировку конфигурирования потоковых процессоров и микросхем с двух- или многомерной структурой расположения программируемых ячеек (ппвм, дпвм и т.п.)
JP2000533804A JP4338308B2 (ja) 1998-02-25 1999-02-25 ２次元またはそれ以上の次元のプログラミング可能なセル構造を備えたデータフロープロセッサおよびコンポーネントをデッドロックなくコンフィグレーションする方法
DE19980309T DE19980309D2 (de) 1998-02-25 1999-02-25 Verfahren zur deadlockfreien Konfiguration von Datenflußprozessoren und Bausteinen mit zwei- oder mehrdimensionaler programmierbarer Zellstruktur (FPGAs, DPGAs, od. dlg.)
EP99914430A EP1057102B1 (de) 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.)
AU33262/99A AU3326299A (en) 1998-02-25 1999-02-25 Method for configuring data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) without producing deadlocks
CA002321874A CA2321874A1 (en) 1998-02-25 1999-02-25 Method for configuring data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) without producing deadlocks
US09/623,113 US6571381B1 (en) 1998-02-25 1999-02-25 Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
DE59901446T DE59901446D1 (de) 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19807872A DE19807872A1 (de) 1998-02-25 1998-02-25 Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
DE19807872.2 1998-02-25

Publications (2)

Publication Number Publication Date
WO1999044120A2 WO1999044120A2 (de) 1999-09-02
WO1999044120A3 true WO1999044120A3 (de) 1999-11-11

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/DE1999/000505 WO1999044120A2 (de) 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.)
PCT/DE1999/000504 WO1999044147A2 (de) 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000504 WO1999044147A2 (de) 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)

Country Status (10)

Country Link
US (3) US6480937B1 (de)
EP (4) EP1057117B1 (de)
JP (2) JP4215394B2 (de)
CN (2) CN1298520A (de)
AT (2) ATE217715T1 (de)
AU (2) AU3326299A (de)
CA (2) CA2321874A1 (de)
DE (5) DE19807872A1 (de)
EA (2) EA003406B1 (de)
WO (2) WO1999044120A2 (de)

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