|Publication number||WO1999017184 A1|
|Publication date||8 Apr 1999|
|Filing date||12 Aug 1998|
|Priority date||29 Sep 1997|
|Publication number||PCT/1998/2431, PCT/GB/1998/002431, PCT/GB/1998/02431, PCT/GB/98/002431, PCT/GB/98/02431, PCT/GB1998/002431, PCT/GB1998/02431, PCT/GB1998002431, PCT/GB199802431, PCT/GB98/002431, PCT/GB98/02431, PCT/GB98002431, PCT/GB9802431, WO 1999/017184 A1, WO 1999017184 A1, WO 1999017184A1, WO 9917184 A1, WO 9917184A1, WO-A1-1999017184, WO-A1-9917184, WO1999/017184A1, WO1999017184 A1, WO1999017184A1, WO9917184 A1, WO9917184A1|
|Inventors||Richard Alan Dayan, Robert Sachsenmaier|
|Applicant||International Business Machines Corporation, Ibm United Kingdom Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (1), Referenced by (4), Classifications (7), Legal Events (5)|
|External Links: Patentscope, Espacenet|
LAPTOP COMPUTER WITH POWER USE MANAGEMENT
Field of the Invention
The invention relates to computers which are capable of being battery powered and in particular to management of power consumption in such computers .
Background of the Invention
Computers intended for both battery and external powered operation generally include power management to reduce power consumption during battery operation. Such management typically shuts down resources such as hard disk storage when they are not actually in use. Such management can cause performance degradation when the resource is needed but this loss of performance is traded for extended battery operation. For example, in the case of the disk drive, it must, if powered down, come up to speed before is can be accessed imposing a usage delay. It is also known to determine the lowest practical operating voltage for use in battery operated devices such as pagers to increase battery life (see e g. U.S. Pat. No. 5,086,501) .
As processors become more powerful from a computing standpoint they also generally require more operating power. As operating power requirements increase they increase heat buildup problems and lower operating time for a given capacity battery. Fans are sometimes used to help with the cooling problems but they also create a battery drain for the computer when in battery-powered mode.
Summary of the Invention
This invention recognizes that while processors for computers are typically optimized for a particular operating voltage they are capable of operating over a range of voltage. Also, while processors are generally designed to operate over a narrow voltage range they can be designed for operation over a broader range with little loss of performance at the peak performance point .
Accordingly, the present invention provides a computer system as claimed in claim 1 or claim 5.
The present invention recognizes that, by so using CPU devices processed to extend the operating voltage range that they are selectively switched off the performance peak to a lower voltage operating point it is possible to exercise added control over power consumption for both battery preservation and heat control purposes while retaining the potential for full performance operation. In a presently preferred implementation, the processor operating voltage is reduced in response to the computer being placed in battery-powered mode, with the reduction of voltage the clock frequency may also be reduced to support the operation at the reduced voltage. While the lower clock rate reduces performance, it is generally a modest tradeoff for the increase in operating time under battery power and a lower rate of heat build-up.
Since power consumption varies as the square of the voltage this approach to power management is highly effective to extend operating time under battery power and to reduce operating temperature. The preferred implementation reduces operating voltage in response to elevated temperature levels inside the computer in both battery and external powered modes. Hence, upon detecting that the temperature is approaching an undesirably high value the processor voltage is reduced to the lowest operating level. Various combinations of these switching approaches may be employed for example by using a lowered voltage level for battery- powered operation and an even lower voltage level for high temperature situations in both battery and external powered modes.
Brief Description of the Drawings
The invention will now be described in greater detail regarding preferred modes of implementation with reference to the drawings wherein:
Fig. 1. is a pictoral representation of a portable computer system suitable for incorporating the invention;
Fig. 2 is a diagram of a computer system showing system elements involved in the presently preferred implementation for the invention;
Fig. 3 is a diagrammatic representation of a voltage versus clock- speed for a processor suboptimized in performance for a wider operating voltage range (not to scale) ;
Fig. 4 is a state diagram indicating the changes occurring when the system moves among the various voltage states according to the invention;
Fig. 5-8 are flow charts describing logic for creating control signals to control processor voltage according to the invention;
Fig. 9 is a circuit diagram of an exemplary voltage selection circuit for use with the invention; Description of the Preferred Embodiment
Referring to Fig. 1, a computer system 10 powerable by a battery and suitable for incorporating the invention includes a connector 12 for receiving alternative external power from a power source 14 such as a transformer power supply (shown) or a docking station (not shown) .
Certain portions of the computer system 10 related to the invention are shown in Fig. 2. A processor unit (CPU) 20 is connected to a RAM module 22, a ROM module 24 and a hard drive 26 using a control bus 28, a data bus 30 and an address bus 32 as is well known for general purpose computing systems. Also connected to busses 28, 30 and 32 is a register 34 for storing status data or flags for controlling system operation according to the invention.
A thermal sensor 40 applies its output signal T to an analog-to-digital converter 42 which supplies a digital temperature signal Td to a storage location of register 34. This signal Td serves to indicate the level of temperature inside the computer system 10 and, according to a preferred implementation for the invention three ranges are recognized. The first range is below the normal or spec level and the second is between spec and danger level, which level is set at a temperature where continued operation would result in damage. The third is above the danger level and requires drastic action to avoid damage.
The connector 14 for external power connects to a charging circuit 50 which is also connected to a battery 52 which is the main internal power source for the computer system 10. The charging circuit 50, as is known in the art, provides for charging of the battery 52 when external power is connected and supplies power to the DC to DC regulator 54. A logic signal Fp9 is produced to be on if external power is present and off if external power is absent.
The DC to DC regulator 54 for a preferred embodiment provides three levels of voltage VBl, vs2 and vs3 (highest to lowest respectively in Fig. 3) for energizing the CPU 20. These voltages are supplied to a voltage selector 56 which selects a voltage Vs, which is applied to the CPU 20. 58. The voltage selector 56 has three control input signals Cvl, Cv2 and Cv3 which are produced as will be described below to control CPU clock rate (or correspondingly period) and operating voltage according to one embodiment for the invention. The signals Cvl, Cv2 and Cv3 are also applied to the clock 58 which provides at its output respective uniform clock rates respective of the signal which is in the on state. The selected voltages and clock rates are coordinated as is indicated in Fig. 3 to correspond to the three selected operating points indicated there .
Referring to Fig. 3, there is a showing (not to scale) of operating voltages VBl, Vs2 and Vs3 for a CPU and corresponding clock rates Rl, R2 and R3 for reliable operation. The present invention recognizes that the energy required by the CPU tends to vary as the square of the operating voltage and, consequently, a drop in applied voltage can reduce power consumption and heating significantly.
The state diagram of Fig. 4 indicates the incidents that trigger transitions from one voltage mode state to another. The states recognized are preferably includes High voltage modes 60 and 62, medium voltage mode 64, low voltage mode 66 and recoverable shut down or hibernate mode 68 m which the current memory contents are stored on the hard disk 26 (Fig. 2) and the system is turned off. The transitions among the states are triggered by changes to power source and thermal sensor temperature level as is indicated on the transition paths of the Fig. 4.
Logic for the transitions indicated m Fig. 4 is implemented, preferably, by computer programs stored on hard drive 26 and executed by CPU 20. This logic is described below with reference to Figs. 5 8. Note that whenever the operating system enters a logic sequence for power management as shown m Figs. 5-8 it first completes all l/o operations and suspends all tasks so that any system changes initiated do not trigger an error.
Referring to Fig. 5, upon power up computer system 10 (see Fig. 1) begins (100) a power up process often referred to as power on self test or POST which does system initialization. During the POST sequence, according to the invention the thermal sensor is read (102) and tested (104) against the normal temperature specification Ts for the system. If m the normal range the power source is checked (106) and a negative test (battery power) causes the voltage control signals to be set (110) for the intermediate level (Cv2 = 1) .
If the thermal sensor signal indicates the temperature is above normal the voltage control signals are set (112) for the low level (Cv3 = 1) and the fan is signalled (114) to turn on. If the power at 106 is external (Fps =1, see Fig. 3), the voltage control signals are set (116) for the highest voltage (Cvl = 1) . Current state data is then stored (118) .
Referring to Fig. 6, continuing the logic flow from Fig. 5 transfer point Al, there is performed a reading of temperature (400) at thermal sensor 40 and a test (402) of the temperature relative to the predefined warning temperature Tw. If the warning level is exceeded the fan-on control signal is set (Cf = 1) (404) and the state is stored (406) . If the temperature is below warning level POST continues.
Now referring to Fig. 7, a periodic interrupt (200) is programmed for temperature checking and the sensor signal is read (202) each time the interrupt occurs. The interrupt may also be triggered by the detector when crossing the predefined level defining temperature points Tw and Ts as is well known using logic in the detector (not shown) . The temperature level is tested (204) against a predefined upper level Ts and if below against a predefined lower warning level Tw (206) . If below the warning level no action is taken (208) but, if above, the fan is signalled on (210) and the stored fan state flag is updated (212) . If the temperature at 204 is above the Ts level Cv3 is tested (214) to determine if the processor voltage is at the lowest level V3. If yes a test (216) is made to determine if the fan is on and if so the system 10 is forced to go to the hibernate by storing memory data and shutting down (218) . If the fan is off the logic transfers to operation 210 to turn on the fan. If the processor is not at the lowest voltage at 214 (Cv3 = 0) the fan is checked (220) and, if on, the processor voltage is set to the lowest level v3 (222) and the stored state data (Fvl, Fv2 and Fv3) for the system is updated (224) . If the fan is off at 20 the sequence at B is followed. The sequence returns at 226.
The logic for processing power source changes is keyed to a periodic interrupt or a interrupt triggered at the charging circuit 50 similar to the temperature monitoring. Referring to Fig. 8, the interrupt (300) initiates a read (302) of the stored power source state and the state of Fps (304) at charging circuit 50 and then does a compare (306) to determine if a change has occurred. If none the logic returns (308) to allow other processing. If, however, a power source change has occurred, a test is made (310) to determine the new power source and for an external source the high voltage mode (Cvl= 1) is set (312) . If, on the other hand, the new power source is the internal battery 52, the medium voltage is selected by setting Cv2 = 1. Then the voltage states are saved as Fvl, Fv2
Referring to Fig. 9, a voltage selector suitable for implementing the invention includes field effect transistors 501, 502 and 503 which are connected to output the voltage Vs for the processor 20 and have respectively as inputs the voltages Vsl, Vs2 and Vs3. Control inputs for transistors 501, 502 and 503 respectively are control signals Cvl, Cv2 and Cv3. Only one of the control signal is in the on state at a time and the voltage at the corresponding transistor becomes Vs the voltage supplied to the processor 20. Accordingly the voltage applied to processor is adjusted according to the invention based upon the state of the temperature of the system, the power source and the fan (if any) state.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|EP0712064A1 *||5 Oct 1995||15 May 1996||Digital Equipment Corporation||Variable frequency clock control for microprocessor-based computer systems|
|EP0785496A1 *||13 Jan 1997||23 Jul 1997||Compaq Computer Corporation||Thermal management of computers|
|JPH0283720A *||Title not available|
|1||*||PATENT ABSTRACTS OF JAPAN vol. 014, no. 283 (P - 1063) 19 June 1990 (1990-06-19)|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9043627||9 May 2013||26 May 2015||Apple Inc.||Methods and apparatuses for controlling the temperature of a data processing system|
|US9274574||1 May 2014||1 Mar 2016||Apple Inc.||Methods and apparatuses for determining throttle settings to satisfy a system power constraint|
|US9317090||27 Apr 2015||19 Apr 2016||Apple Inc.||Methods and apparatuses for operating a data processing system|
|US9671845||7 Jan 2014||6 Jun 2017||Apple Inc.||Methods and apparatuses for dynamic power control|
|International Classification||G06F1/26, G06F1/20|
|Cooperative Classification||G06F1/263, G06F1/206, Y02B60/1275|
|European Classification||G06F1/26B, G06F1/20T|
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