WO1999016177A3 - Communication processor having buffer list modifier control bits - Google Patents

Communication processor having buffer list modifier control bits Download PDF

Info

Publication number
WO1999016177A3
WO1999016177A3 PCT/US1998/020011 US9820011W WO9916177A3 WO 1999016177 A3 WO1999016177 A3 WO 1999016177A3 US 9820011 W US9820011 W US 9820011W WO 9916177 A3 WO9916177 A3 WO 9916177A3
Authority
WO
WIPO (PCT)
Prior art keywords
communication processor
control bits
buffer list
modifier control
list modifier
Prior art date
Application number
PCT/US1998/020011
Other languages
French (fr)
Other versions
WO1999016177B1 (en
WO1999016177A2 (en
Inventor
Bradley Roach
Peter Fiacco
Greg Scherer
Stuart Berman
David Duckman
Original Assignee
Emulex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Emulex Corp filed Critical Emulex Corp
Priority to CA002304620A priority Critical patent/CA2304620C/en
Priority to EP98949477A priority patent/EP1023668A4/en
Priority to JP2000513358A priority patent/JP3457947B2/en
Publication of WO1999016177A2 publication Critical patent/WO1999016177A2/en
Publication of WO1999016177A3 publication Critical patent/WO1999016177A3/en
Publication of WO1999016177B1 publication Critical patent/WO1999016177B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H04L49/9052—Buffering arrangements including multiple buffers, e.g. buffer pools with buffers of different sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

A communication processor (22) sends and receives frames of data and commands. Transmit and receive protocol engine (32 and 30) is controlled by host driver software (38) which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.
PCT/US1998/020011 1997-09-24 1998-09-24 Communication processor having buffer list modifier control bits WO1999016177A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002304620A CA2304620C (en) 1997-09-24 1998-09-24 Communication processor having buffer list modifier control bits
EP98949477A EP1023668A4 (en) 1997-09-24 1998-09-24 Communication processor having buffer list modifier control bits
JP2000513358A JP3457947B2 (en) 1997-09-24 1998-09-24 Communication processor with buffer list modifier control bits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/937,065 1997-09-24
US08/937,065 US6304910B1 (en) 1997-09-24 1997-09-24 Communication processor having buffer list modifier control bits

Publications (3)

Publication Number Publication Date
WO1999016177A2 WO1999016177A2 (en) 1999-04-01
WO1999016177A3 true WO1999016177A3 (en) 1999-08-12
WO1999016177B1 WO1999016177B1 (en) 1999-10-07

Family

ID=25469442

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/020011 WO1999016177A2 (en) 1997-09-24 1998-09-24 Communication processor having buffer list modifier control bits

Country Status (6)

Country Link
US (1) US6304910B1 (en)
EP (1) EP1023668A4 (en)
JP (1) JP3457947B2 (en)
KR (1) KR100367949B1 (en)
CA (1) CA2304620C (en)
WO (1) WO1999016177A2 (en)

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US6185203B1 (en) 1997-02-18 2001-02-06 Vixel Corporation Fibre channel switching fabric
GB2342021B (en) * 1997-11-17 2002-12-31 Seagate Technology Method and dedicated frame buffers for receiving frames
US6470026B1 (en) * 1998-10-30 2002-10-22 Agilent Technologies, Inc. Fibre channel loop map initialization protocol implemented in hardware
US6985431B1 (en) 1999-08-27 2006-01-10 International Business Machines Corporation Network switch and components and method of operation
US6769033B1 (en) 1999-08-27 2004-07-27 International Business Machines Corporation Network processor processing complex and methods
US6643710B1 (en) * 1999-09-17 2003-11-04 3Com Corporation Architecture to fragment transmitted TCP packets to a requested window size
US6856619B1 (en) * 2000-03-07 2005-02-15 Sun Microsystems, Inc. Computer network controller
US6775693B1 (en) * 2000-03-30 2004-08-10 Baydel Limited Network DMA method
US6757730B1 (en) 2000-05-31 2004-06-29 Datasynapse, Inc. Method, apparatus and articles-of-manufacture for network-based distributed computing
WO2002063479A1 (en) * 2001-02-02 2002-08-15 Datasynapse, Inc. Distributed computing system
US7359397B2 (en) * 2002-04-19 2008-04-15 Seagate Technology Llc Prioritizing transfers across an interface
JP2004080226A (en) * 2002-08-14 2004-03-11 Nec Corp Proxy fc port, fc network, and fc transmission transfer method used for them
WO2004017220A1 (en) * 2002-08-19 2004-02-26 Broadcom Corporation One-shot rdma
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US8111696B2 (en) * 2008-10-14 2012-02-07 Emulex Design & Manufacturing Corporation Method to improve the performance of a computer network
JP4922442B2 (en) 2010-07-29 2012-04-25 株式会社東芝 Buffer management device, storage device including the same, and buffer management method

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US5727218A (en) * 1996-03-05 1998-03-10 Unisys Corp. Controlling an apparatus disposed for adapting fiber channel transmissions to an industry standard data bus
US5809328A (en) * 1995-12-21 1998-09-15 Unisys Corp. Apparatus for fibre channel transmission having interface logic, buffer memory, multiplexor/control device, fibre channel controller, gigabit link module, microprocessor, and bus control device
US5828901A (en) * 1995-12-21 1998-10-27 Cirrus Logic, Inc. Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer

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Also Published As

Publication number Publication date
JP3457947B2 (en) 2003-10-20
WO1999016177B1 (en) 1999-10-07
WO1999016177A2 (en) 1999-04-01
CA2304620C (en) 2004-08-10
CA2304620A1 (en) 1999-04-01
JP2001517888A (en) 2001-10-09
US6304910B1 (en) 2001-10-16
KR100367949B1 (en) 2003-01-14
KR20010078685A (en) 2001-08-21
EP1023668A4 (en) 2005-02-09
EP1023668A2 (en) 2000-08-02

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