WO1998054833A1

WO1998054833A1 - Improved transimpedance amplifier

Info

Publication number: WO1998054833A1
Application number: PCT/BR1998/000030
Authority: WO
Inventors: Valentino Corso; Ezio Maria Bastida
Original assignee: TELECOMUNICAÇõES BRASILEIRAS S/A - TELEBRÁS
Priority date: 1997-05-30
Filing date: 1998-06-01
Publication date: 1998-12-03
Also published as: BR9703233A; EP0916183A1

Abstract

Improved transimpedance amplifier in monolithic integrated circuit form, comprising an inverting cascode amplifier stage having at least one peaking inductor (64, 68, 114, 118, 152, 157, 172, 177) followed by one or more amplification stages, where the transimpedance amplifier gain is controlled by means of the adjustment of the D.C. current flowing through the first transistor (65, 115, 153, 173) cascode inverter stage so as to regulate its transconductance. Said adjustment comprises the addition or subtraction of current at the connection of the first and second transistors in the inverting cascode amplifier stage, either by means of a resistor connected between said connection and a preset positive, negative or zero voltage source or by an accessory current supply circuit that adds or subtracts a controlled DC current amount.

Description

IMPROVED TRANSIMPEDANCE AMPLIFIER BACKGROUND OF THE INVENTION The present invention relates to transimpedance amplifiers, and more specifically to monolithic amplifiers to be manufactured in large quantities for use in wide-band low-cost optical front-ends.

Due to the exceptional ability of transmitting a large quantity of data per unit time, as well as insensitivity to electromagnetic interferences, high bit rate optical links play a basic role in telecommunications development. Moreover, owing to a large and increasing customer demand for high speed digital services, optical equipment manufacturers are, at present, extremely interested in the development of low cost broadband networks.

In such applications, the optical signal is usually transmitted through optical fiber, whose receiver - or repeater - end is coupled to a photodiode that converts the optical signal into an electrical current signal. Transimpedance amplifiers are low noise devices that convert this electric current into a voltage signal with a magnitude adequate for subsequent electronic processing. Such amplifiers are certainly the most important elements of optical receivers, since they practically determine basic receiver - or repeater - features, such as bandwidth, sensitivity, dynamic range and bit error rate. The lower the amplifier noise the better the receiver sensitivity will be, and, therefore, its ability to be used for longer transmitter to receiver spacings for a given transmitted optical power level. In transimpedance amplifier circuit configurations, the current is converted into voltage by means of a feedback resistor R_F bridging input and output of an inverting amplifier. The value of this resistor must be carefully chosen since a higher resistance increases the gain of the amplifier while decreasing the equivalent noise current_. However, the amplifier bandwidth as well as its dynamic range are inversely proportional to the value of R_F. Moreover said bandwidth decreases in accordance with the parasitic capacitance of the photodiode as well as with the number of stages constituting the inverting amplifier.

According to the previous art, low frequency circuits normally include several stages, while very large bandwidth circuits use a configuration in which the amplification is performed by a single transistor (here called, for brevity, single transistor inverter).

Due to the inherent low voltage gain, the single transistor inverter should use a low feedback resistance, therefore preserving the bandwidth. However, as noted before, this degrades the achievable noise performance.

In order to attain a better noise performance and a wider bandwidth, single inductor peaking, such as shown in Fig. 1, or double inductor peaking such as shown in Fig. 2, were introduced in single transistor inverters. The feedback resistors that provide conversion of current into voltage are referred to as 19 in

Fig. 1 and 39 in Fig. 2.

A further improvement in noise performances was attained by using cascode inverter circuit configurations, such as exemplified in Fig. 3, where 44 and 48 are the two peaking inductors.

Amplifiers such as those shown in figures 1, 2 and 3 are used in large numbers in optical communication systems, therefore the utilization of said devices assembled from discrete components would bring the systems' cost to prohibitive levels. On the other hand, when these circuits are realized in monolithic form - producing high volume low cost devices - the resulting amplifiers show increased dependence on the manufacturing process drift. In some cases, these circuits show a tendency to oscillate, lowering the yield of the manufacturing process, since the circuits so affected have to be discarded. This can be seen in the graph in Fig. 5, where curve 81 illustrates the frequency response when the component values are in the middle of the tolerance range, and curve 82 shows the behavior of the same circuit when a particular process fluctuation brought some component values to the limit of the tolerance range. In this latter case, a 13dB peak in the high frequencies makes the circuit completely unsuitable for use in optical receivers, mainly due to the fact that the circuit is working very near to oscillation conditions. There are other instances where the deficient frequency response requires a boost in the high end to achieve an adequate bandwidth. Another inherent problem of these amplifiers lies in the bandwidth reduction when their input is loaded by the diode capacitance: the higher frequency currents are shunted to ground instead of entering the amplifier. To compensate this decrease, the amplifier gain has to be increased at the high end of the operating bandwidth by means of one or two peaking inductors. The use of peaking with one or two inductors in monolithic cascode amplifiers, with the purpose of reducing noise and increasing bandwidth, demands an close control of stray reactances in the inductors, transistors and layout, due to the possibility of unwanted oscillations, as mentioned before.

It is therefore an object of the present invention to provide low cost monolithic transimpedance amplifiers having bandwidth and noise performance much better than those previously achieved with known cascode inverters

A second objective of the invention is to make the performance of these amplifiers substantially independent of fluctuations that occur during manufacturing or to provide practical low-cost ways to compensate for said fluctuations.

Another objective is to provide circuits capable of operating with no substantial bandwidth reduction, even when low-cost photodiodes are used. Such diodes usually have a much higher capacitance than their more expensive counterparts. SUMMARY OF THE INVENTION

In accordance with the invention, the transimpedance amplifier gain control is provided by the addition or subtraction of a controlled D.C. current to the first transistor cascode inverter stage so as to adjust its transconductance.

According to another feature if the invention, said control current is provided by a control resistor which is connected between the inverter transistor and a fixed or adjustable voltage source.

According to yet another feature of the invention, said control current is supplied by an accessory current supply circuit that adds or subtracts a controlled amount of D.C. current to said first inverter transistor.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features and advantages of the invention will be more apparent from the following detailed description in conjunction with the appended drawings in which: Figure 1 shows a single device inverter transimpedance amplifier with single inductor peaking, according to the previous known art.

Figure 2 shows a single device inverter transimpedance amplifier with double inductor peaking, according to the previous state of the art.

Figure 3 shows a cascode transimpedance amplifier with double inductor peaking, from which single inductor circuits can be derived by short circuiting one of its inductors.

Figure 4 shows a first preferred embodiment of the invention, comprising a cascode transimpedance amplifier with double inductor peaking and a gain control resistor. Figure 5 shows a typical effect of the process fluctuation on the Fig. 3 amplifier bandwidth, considering the total input capacitance of 0,5 pF (photodiode + stray).

Figure 6 shows the peaking control and stabilizing action as a function of the voltage applied to the control resistor for a Fig. 4 circuit. Double inductor peaking is used and a total input capacitance (photodiode + stray) of 0,5 pF is taken into account.

Figure 7 shows a second preferred embodiment of the invention, comprising a cascode type transimpedance amplifier with double inductor peaking, positive current feedback a gain control resistor. Single inductor circuits, in accordance with the invention, are obtained by short circuiting one of the inductors.

Figure 8 shows the experimental response curves for the Fig. 7 circuit as a function of the total input capacitance (photodiode + stray), between 0 and 1.2pF in 0.2pF steps, when no control voltage is applied.

Figure 9 shows the frequency response curves for the same circuit, under similar conditions of input , when the control voltage is -4N.

Figure 10 shows the schematic of the first embodiment of the invention, when adapted for operation with a single power supply. Figure 11 shows the schematic of the second embodiment of the invention, when adapted for operation with a single power supply.

DETAILED DESCRIPTION OF THE INVENTION Notwithstanding the fact that all circuit embodiments shown comprise GaAs MESFET's, the same configurations may be used with transistors manufactured according to other technologies.

In the first preferred embodiments of the invention, shown in Fig. 4, the first transistor 65 performs the inverting amplifying action, the second transistor 66 functions as a grounded gate non-inverting amplifier, and third transistor 67 works as the active load of the cascode stage. Transistor 69 is a current source used for obtaining the DC voltage that biases the gate of 66, while transistors 73 and 74 form the output buffer amplifier of the source follower type. Inductor 64 resonates in series with the input capacitance of transistor 65, so that voltage gain increases with signal frequency. Inductor 68 has a similar effect, increasing the load of the cascode stage at high frequencies, reducing the noise fluctuations of the current that circulates in the amplifying devices. By shorting either inductor 64 or 68, a single inductor configuration is obtained. Block 100 is a series connected cascade of diodes, performing a DC level shifting of the bias voltage applied to the gate of transistor 66.

In the circuit of Fig. 4, negative feedback is provided by resistor 62, while the input transistor 65 bias is provided by resistor 63. Gain control resistor 71 has a high enough value to prevent a substantial degrading of the amplifier's noise performance as well as its voltage gain. This resistor can be connected either to an external voltage source or to the positive or negative supplies or to ground. The value of this voltage is a function of measurements performed in specific locations of the semiconductor wafer during manufacture, prior to the dicing into individual chips. In order to increase the control options, an external resistor may be connected in series with resistor 71. On-chip resistor trimming methods can also be employed. Furthermore, in accordance with the invention, instead of a resistor 71, one may make use of any circuit capable of adding or subtracting in a controlled manner DC current to or from the input transistor, provided that said circuit does not substantially degrade the amplifier gain, bandwidth, dynamic range or noise performances. Computer simulations of the Fig. 4 circuit performance were conducted, showing a transimpedance bandwidth greater than 3,5 GHz, with extremely low equivalent input noise current densities (< 4pA/Hz^,/2), using standard low-cost 0.5μm gate gallium arsenide MESFET's.. These results enable the circuit for use in 5Gbits/s links. In the previous art, the maximum bit rate obtained with a cascode configuration using this technology was about one-half (2.5Gbit/s) and the equivalent noise input current densities were higher than 5pA/Hz^1/2. Moreover, due to the low component count, the circuit configuration shown in Fig. 4 resultsin a very high overall device yield per wafer.

Figure 5 shows the effect of the process fluctuations on the circuit performance, when lead 72 is unconnected, meaning that resistor 71 is out of the circuit. Under such conditions, the circuit of Fig. 4 becomes identical to the one in Fig. 3. The frequency response curves of the graph in Fig. 5 were calculated for a total input capacitance of 0.5pF with the PSPICE program, by using data from the Triquint foundry for 0.5μm GaAs FET's. Curve 81 shows the performance with nominal process conditions, while curve 82 results when a particular process fluctuation (LLLOLO) occurs. This curve shows a large undesired peaking of the transimpedance function which makes the amplifier unsuitable for use in optical receivers, mainly due to the fact that the circuit is working very near to oscillation conditions.

Applying a suitable control voltage to resistor lead 72, the circuit can be stabilized, and the transimpedance peaking can be reduced to less than 3dB. This is shown in Fig. 6, where curve 83 corresponds to the original frequency response. Curve 84 already shows some response improvement, with a reduction in the high frequency peaking is due to the application of ON at point 72. The optimum response, shown as curve 85 results from a voltage of -1,2N at lead 72. It can be seen that now the response is quite flat within the passband of interest. In this example, resistor 71 is approximately equal to 500 ohms. Considering that the grounded gate transistor 66 has a dynamic impedance around 40Ω, it can be seen that more than 90% of the signal amplified by transistor 65 will be inputted to transistor 66 to be amplified by the latter.

Another preferred embodiment of the invention is shown in Fig. 7, in which positive current feedback is applied from transistor 124 source to the drain of transistor 115. This adds to the total current flow through the latter, therefore increasing its transconductance. Similarly to the previous circuit, in the present configuration transistor 115 drain current can be either added or subtracted through resistor 121, thereby providing a gain adjustment in this stage.

A circuit having the Fig. 7 configuration was designed for use with PIN photodiodes for 2,5Gbits/s links and fabricated at the Marconi foundry. Tests conducted with this circuit produced the set of curves of Fig. 8, in which curve 131 corresponds to zero total input parasitic capacitance (photodiode + stray), and the following ones, to 0.2pF capacitance increments, with no control voltage applied. It can be seen that the circuit performs well even with parasitic capacitances of the order of lpF (see curve 136). However, with low values of Ctot (sum of the photodiode and the stray capacitances), the curves show undesired high-frequency peaking (curves 132 and 135).

Applying a control voltage of -4N to lead 122, results in the performance shown by the curves of Fig. 9. It can be seen that said control gives a satisfactory circuit performance, even with low capacitance values C_tot between 0 and 0.6 pF

(curves 142 and 144). Moreover, the transconductance bandpass shows an increase of 0.3GHz on the high frequency end.

In both circuits of figures 4 and 7, two power supplies were used, a positive 10 and a negative 20. Said circuits, however, can be modified so as to work with only one supply, by adding diode cascades to the transistor sources, to shift the DC voltage levels.

Applying this procedure to the circuit of Fig. 4, results in the amplifier of Fig. 10, where it is seen that besides the block 100 (connected to the gate of transistor 155), similar blocks were added to provide a DC voltage shift of transistors 153 and 162 sources, thereby allowing the use of only one positive supply 10. This same procedure can be applied to the circuit of Fig. 7, resulting in the amplifier of Fig. 11.

As will be apparent to those skilled in the art, numerous modifications may be made within the scope of the invention, which is not intended to be limited except in accordance with the following claims. An example of such modifications would consist in the addition of automatic gain control (AGC), which could be achieved in several ways, one of them being the variation of the negative feedback resistance (62 in Fig. 4 or 112 in Fig. 7) in accordance with the signal strength, and another being the splitting of the amplified signal current by means of a differential amplifier stage.

Claims

1. IMPROVED TRANSIMPEDANCE AMPLIFIER in monolithic integrated circuit form, comprising an inverting cascode amplifier stage having at least one peaking inductor (64, 68, 114, 118, 152, 157, 172, 177) followed by one or more amplification stages, characterized in that the transimpedance amplifier gain control is provided by the adjustment of the amount of the D.C. current flowing through the first transistor (65, 115, 153, 173) cascode inverter stage so as to regulate its transconductance

2. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 1, characterized by the fact that said adjustment comprises the addition of a DC current to the terminal (65 a) of the first transistor that is connected to the second transistor (66) input terminal, in the inverting cascode amplifier stage.

3. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 1, characterized by the fact that said adjustment comprises the subtraction of part of the DC current at the terminal (65 a) of the first transistor that is connected to the second transistor (66) input terminal, in the inverting cascode amplifier stage.

4. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 2, characterized by the fact that said DC current addition is provided by means of a control resistor (71, 121, 158, 180) connected between said terminal (65 a) of the first transistor and a preset voltage source (72, 122, 159, 181).

5. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 3, characterized by the fact that said DC current addition is provided by means of a control resistor (71, 121, 158, 180) connected between said terminal (65 a) of the first transistor and a preset voltage source (72, 122, 159, 181).

6. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 4, characterized by the fact that said voltage source is positive.

7. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 4, characterized by the fact that said voltage source is negative.

8. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 4, characterized by the fact that said voltage source is at ground potential.

9. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 5, characterized by the fact that said voltage source is positive.

10. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 5, characterized by the fact that said voltage source is negative.

11. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 5, characterized by the fact that said voltage source is at ground potential.

12. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim 1, characterized by the fact that said adjustment is provided by a by an accessory current supply circuit circuit that adds or subtracts a controlled DC current amount, connected to the terminal (65 a) of the first transistor that is connected to the second transistor (66) input terminal, in the inverting cascode amplifier stage..

13. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim

4, characterized by the fact that the resistance value of the control resistor (71, 121, 158, 180) is adjusted according to measurements performed in specific locations of the semiconductor wafer during the manufacturing process of the integrated circuit.

14. IMPROVED TRANSIMPEDANCE AMPLIFIER, according to Claim

5, characterized by the fact that the resistance value of the control resistor (71, 121, 158, 180) is adjusted according to measurements performed in specific locations of the semiconductor wafer during the manufacturing process of the integrated circuit.

15. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 1.

16. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 2.

17. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 3.

18. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 4.

19. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 5.

20. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 6.

21. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 7.

22. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 8.

23. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 9..

24. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 10.

25. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 11.

26. IMPROVED TRANSIMPEDANCE AMPLIFIER, characterized by the addition of an automatic gain control circuit (AGC) to the amplifier of Claim 12.