WO1998039846A2 - Delay-locked loop with binary-coupled capacitor - Google Patents
Delay-locked loop with binary-coupled capacitor Download PDFInfo
- Publication number
- WO1998039846A2 WO1998039846A2 PCT/US1998/004346 US9804346W WO9839846A2 WO 1998039846 A2 WO1998039846 A2 WO 1998039846A2 US 9804346 W US9804346 W US 9804346W WO 9839846 A2 WO9839846 A2 WO 9839846A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die
- signal
- delay
- input
- clock signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Dram (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU65433/98A AU6543398A (en) | 1997-03-05 | 1998-03-05 | Delay-locked loop with binary-coupled capacitor |
JP53881698A JP3778946B2 (en) | 1997-03-05 | 1998-03-05 | Delay locked loop with binary coupled capacitors |
KR1019997008090A KR100662221B1 (en) | 1997-03-05 | 1998-03-05 | Delay-locked loop with binary-coupled capacitor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/811,918 | 1997-03-05 | ||
US08/811,918 US5946244A (en) | 1997-03-05 | 1997-03-05 | Delay-locked loop with binary-coupled capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998039846A2 true WO1998039846A2 (en) | 1998-09-11 |
WO1998039846A3 WO1998039846A3 (en) | 1998-12-03 |
Family
ID=25207946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/004346 WO1998039846A2 (en) | 1997-03-05 | 1998-03-05 | Delay-locked loop with binary-coupled capacitor |
Country Status (5)
Country | Link |
---|---|
US (7) | US5946244A (en) |
JP (1) | JP3778946B2 (en) |
KR (1) | KR100662221B1 (en) |
AU (1) | AU6543398A (en) |
WO (1) | WO1998039846A2 (en) |
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US6665351B2 (en) | 2000-02-02 | 2003-12-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Circuit and method for providing a digital data signal with pre-distortion |
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"VARIABLE DELAY DIGITAL CIRCUIT" IBM TECHNICAL DISCLOSURE BULLETIN, vol. 35, no. 4A, 1 September 1992, pages 365-366, XP000314796 * |
PATENT ABSTRACTS OF JAPAN vol. 011, no. 083 (E-489), 13 March 1987 & JP 61 237512 A (NEC IC MICROCOMPUT SYST LTD), 22 October 1986 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6665351B2 (en) | 2000-02-02 | 2003-12-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Circuit and method for providing a digital data signal with pre-distortion |
DE10141939B4 (en) * | 2000-08-23 | 2011-08-11 | Samsung Electronics Co., Ltd., Kyonggi | Flip-flop circuit for clock signal-dependent data buffering and signal height comparator containing the same |
Also Published As
Publication number | Publication date |
---|---|
JP3778946B2 (en) | 2006-05-24 |
US20020057624A1 (en) | 2002-05-16 |
US20010053100A1 (en) | 2001-12-20 |
US6262921B1 (en) | 2001-07-17 |
US20020008556A1 (en) | 2002-01-24 |
KR100662221B1 (en) | 2007-01-02 |
US6400641B1 (en) | 2002-06-04 |
AU6543398A (en) | 1998-09-22 |
KR20000076004A (en) | 2000-12-26 |
WO1998039846A3 (en) | 1998-12-03 |
US6490207B2 (en) | 2002-12-03 |
US6483757B2 (en) | 2002-11-19 |
JP2001514812A (en) | 2001-09-11 |
US6256259B1 (en) | 2001-07-03 |
US5946244A (en) | 1999-08-31 |
US6490224B2 (en) | 2002-12-03 |
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