WO1998039846A2

WO1998039846A2 - Delay-locked loop with binary-coupled capacitor

Info

Publication number: WO1998039846A2
Application number: PCT/US1998/004346
Authority: WO
Inventors: Troy A. Manning
Original assignee: Micron Technology, Inc.
Priority date: 1997-03-05
Filing date: 1998-03-05
Publication date: 1998-09-11
Also published as: US6256259B1; JP2001514812A; JP3778946B2; US5946244A; US6490224B2; US20020008556A1; US20020057624A1; US20010053100A1; US6483757B2; US6490207B2; KR20000076004A; WO1998039846A3; US6400641B1; US6262921B1; AU6543398A; KR100662221B1

Abstract

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Description

DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR

TECHNICAL FIELD

The present invention relates to integrated circuit devices, and more particularly, to delay-locked loop circuits in integrated circuit devices.

BACKGROUND OF THE INVENTION

Many high-speed integrated devices, such as a synchronous memory device 40 shown in Figure 1, perform operations in a predetermined sequence. These operations are generally performed responsive to respective command signals issued by a command generator, such as a memory controller 44.

It will be understood by one skilled in the art that the block diagram of Figure 1 omits some signals applied to the memory device 40 for purposes of brevity. Also, one skilled in the art will understand that the command signals COM may be composed of a combination of other signals or may be a packet of control data. In either case, the combination of signals or packet is commonly referred to as simply a command. The exact nature of these signals or packet will depend on the nature of the memory device 40, but the principles explained above are applicable to many types of memory devices, including synchronous DRAMs and packetized DRAMs. Also, although the timing control by issuing command signals according to a fixed relationship with the clock signal will be explained with reference to memory devices, the principles described herein are applicable to other integrated circuits that utilize counters or related switching signals responsive to a clock signal. Timing of operations within the device 40 is determined by a logic control circuit 42 controlled by an internal clock signal CKBUF. In a synchronous DRAM, the logic control circuit 42 may be realized conventionally. In a packetized memory system, the logic control circuit may include command sequencing and decoding circuitry.

Timing of signals outside of the memory device 40 is determined by an external clock signal CKIN that is produced by an external device 44 such as a memory controller. Usually, operations within the memory device 40 must be synchronized to operations outside of the memory device 40. For example, commands and data are transferred into or out of the memory device 40 on command and data busses 48, 49, respectively, by clocking command and data latches 50, 52 according to d e internal clock signal CKBUF. Command timing on the command bus 48 and data timing on the data bus 49 are controlled by the external clock signal CKIN. To transfer commands and data to and from the busses 48, 49 at the proper times relative to the external clock signal CKIN, the internal clock signal CKBUF must be synchronized to the external clock signal CKIN. To ensure that the clock signals CKBUF, CKIN can be synchronized, the internal clock signal CKBUF is derived from the external clock signal CKIN. A buffer amplifier 46 buffers the external clock signal CKIN to produce a buffered version of the external clock signal CKIN as the internal clock signal CKBUF. The buffer amplifier 46 is a conventional differential amplifier that provides sufficient gain and appropriate level shifting so that the buffered clock signal CKBUF can drive circuits within the memory device 40 at CMOS levels.

The buffer amplifier 46 also induces some time delay so mat the buffered clock signal CKBUF is phase-shifted relative the external clock signal CKIN. As long as the phase-shift is very rninimal, timing within the memory device 40 can be synchronized easily to tiie external timing.

Unfortunately, as the frequency of operation of the memory device 40 increases, the time delay induced by die buffer amplifier 46 may become significant. Consequently, commands or data supplied by the memory controller 44 may be gone from the command or data bus 48, 49 before the latches 50, 52 are activated on die appropriate edge of the buffered clock signal CKBUF. To prevent the latches 50, 52 from missing commands that arrive synchronously with the external clock CKIN, the memory device 40 may be operated at lower frequencies. However, lower frequency operation of memory devices typically reduces die speed of operation undesirably.

To improve synchronization of the internal and external riming, a prior art memory device 60 shown in Figure 2 includes an analog delay-locked loop 62 mat receives the buffered clock signal CKBUF and produces a synchronized clock signal CKSYNC that is synchronized to die external clock signal CKIN. To compensate for the delay of die buffer amplifier 46, the synchronized clock signal CKSYNC is phase-shifted relative to die buffered clock signal CKBUF by an amount offsetting the delay of die buffer amplifier 46. Because d e synchronized clock signal CKSYNC is synchronized and substantially in phase with die external clock signal CKIN, commands and data arriving on the command bus 48 or data bus 49 can be synchronized to die external clock CKIN through die synchronous clock signal CKSYNC.

One problem with die memory device 60 of Figure 2 is tiiat conventional delay-locked loops 62 typically operate only over a narrow frequency band. Consequentiy, die memory device 60 may not operate properly in multifrequency environments or in a wide range of applications.

Moreover, many conventional analog delay-locked loops include relatively sophisticated analog components tiiat are not always easily integrated witii digital memory components. Also, as operating conditions vary, the delay of the buffer amplifier 46 can vary, thereby causing corresponding variations in me phase shift. If the delay-locked loop 62 does not adjust die phase shift of the synchronous clock signal CKSYNC accordingly, operations within die device 40 may not remain properly synchronized to die external clock CKIN. SUMMARY OF THE INVENTION

A delay-locked loop produces a plurality of phase shifted signals in response to an input signal at a selected input frequency. The delay-locked loop includes a variable delay circuit that outputs a delayed clock signal. A race detection circuit receives die delayed clock signal and die input clock signal and, depending upon whetiier the delayed clock signal leads or lags d e input clock signal, die race detection circuit outputs an increment or decrement signal to a counter. In response to die increment or decrement signal, die counter increments or decrements a digital count signal. The variable delay circuit includes a bank of selectable capacitors, each selectively coupled between a reference potential and a supply potential by a respective selection switch. Each of die selection switches is controlled by 1 bit of d e digital count signal from the counter. If d e corresponding bit is a "1," the selection switch couples die capacitor in parallel with the otiier capacitors. The capacitance of die bank is determined by die number and capacitance of die selected capacitors. Because d e delay of die delay circuit corresponds to die capacitance, die delay of die delay circuit is controlled by die digital count signal.

Each capacitor in the bank has a capacitance corresponding to die significance of its respective bit of die digital count. For example, d e capacitor controlled by d e most significant bit of me digital signal is die largest capacitor and die capacitor controlled by die least significant bit of die digital signal is die smallest capacitor.

In one embodiment, die race detection circuit is formed from a pair of pulse generators, each having its output coupled to a respective gating circuit. The gating circuits each include control ports and are responsive to control signals at die control ports to pass or block die pulse from die respective pulse circuit. The outputs of die gating circuits drive respective latch circuits. Each of die latch circuits includes an output coupled to control port of die gating circuit coupled to die otiier latch circuit so tiiat the latches output d e control signals. Thus, if a pulse passes through die first gating circuits and sets its corresponding latch, die latch output disables die second gating circuit and prevents die second latch from being set.

If botii pulses arrive at their corresponding gating circuit substantially simultaneously, botii of die latches are set before the gating circuits are disabled. In response to botii latches being set, an arbitration circuit disables clocking of die counter so tiiat die digital count signal remains constant, thereby maintaining the delay of die variable delay circuit.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a prior art memory device driven by a memory controller and including a buffer amplifier producing a buffered clock signal.

Figure 2 is a block diagram of a prior art memory device driven by a memory controller and including a delay-locked loop tiiat produces a synchronized clock signal from die buffered clock signal.

Figure 3 is a block diagram of a memory device according to one embodiment of die invention under control of a memory controller and including a pair of digital delay-locked loops and a latch circuit tiiat produce a synchronized internal clock signal. Figure 4 is a signal timing diagram of selected signals witiϋn the memory device of Figure 3.

Figure 5 is a schematic of one of die delay-locked loops of Figure 3.

Figure 6 is a signal timing diagram of selected signals witiiin die delay-locked loop of Figure 5.

Figure 7 is a schematic of a pulse generator in the delay-locked loop of Figure 5.

Figure 8 is a schematic of a buffer model circuit in the delay- locked loop of Figure 5. Figure 9 is a schematic of a race detection circuit in die delay- locked loop of Figure 5.

Figure 10 is a block diagram of a computer system including die memory controller and memory device of Figure 3.

DETAILED DESCRIPTION OF THE INVENTION

As shown in Figure 3, a memory device 70 according to one embodiment of die invention operates under control of die external clock signal CLKBSf and commands COM from me external device 44. One skilled in die art will recognize that the commands COM are typically a composite of signals such as die row and column address strobes RAS*, CAS* or output enable signal OE*. Alternatively, the commands COM may be incorporated in a packet of control data in a packetized memory system.

The memory device 70 includes die logic control circuit 42 and buffer amplifier 46 as described above witii reference to Figures 1 and 2. However, ratiier than the analog delay-locked loop 62 of d e device 60 of Figure 2, die memory device 70 includes a synchronous clock circuit 72 formed from an input inverter 74, first and second digital delay-locked loops 76, 78 and a latch circuit 80. Operation of d e synchronous clock circuit 72 will now be explained witii reference to Figures 4-6. In response to die input clock signal CLKIN, the buffer amplifier

46 outputs a buffered clock signal CLKBUF that is delayed with respect to die input clock signal CLKIN by die response time XBUF of the buffer amplifier 46. The first delay-locked loop 76 receives an inverted version of die buffered clock signal CKBUF from the inverter 74 and die second delay-locked loop 78 receives the buffered clock signal CKBUF directly. As will be described below with reference to Figure 5, the delay-locked loops 76, 78 are trailing-edge based delay-locked loops tiiat produce a first delayed clock CKal* as shown in die tiiird graph of 4 in response to falling edge of die buffered clock signal CKBUF and a second delayed clock CKa2* as shown in the fourth graph of Figure 4 in response to the falling edge of die inverted buffered clock signal CKBUF*. Consequently, die operations described below will be initiated at time by a falling edge of die external clock signal CKIN that causes a falling edge of die buffered clock signal CKBUF. As will also be described below, die delayed clock signals CKal*, CKa2* are synchronized to the falling and rising edges, respectively, of buffered clock signal CKBUF. Each falling edge of die clock signals CKal*, CKa2* leads die corresponding falling or rising edge of die buffered clock signal CKBUF by a time XLE_AD diat is substantially equal to die sum of the delay time TBUF of the buffer amplifier 46 and delay time TL_ATCH ^OI~ die latch circuit 80. Thus, falling edges of the first delayed clock signal CKal* lead falling edges die external clock signal CKIN by approximately the delay time of the latch circuit 80. Similarly, falling edges of die second delayed clock signal CKa2* lead rising edges of die external clock signal CKIN by the delay time of the latch circuit 80. The latch circuit 80 receives the delayed clock signals CKal*,

CKa2* at inputs of respective NAND gates 82, 84. As will be explained below, die latch circuit 80 responds to falling edges of die first delayed clock signal CKal* by producing a low-going edge of die synchronized clock signal CKSYNC. The latch circuit 80 responds to low-going edges of die second clock signal CKa2* by producing high-going edges of die synchronous clock signal CKSYNC. The rising and falling edges of synchronized clock signal CKSYNC lag the falling edges of die delayed clock signals CKal*, CKa2* by die delay time T AT_CH of the latch circuit 80, and d e falling edges of d e delayed clock signals CKal*, CKa2* lead the external clock signal CKIN by the delay time T_LATCH of the latch circuit 80. Therefore, the synchronous clock signal CKSYNC is substantially in phase with die external clock signal CKIN.

The logic control circuit 42 establishes timing of operations within die memory device 70 responsive to die synchronous clock signal CKSYNC. For example, the logic control circuit 42 activates the command latches 50 on edges of die synchronous clock signal CKSYNC to latch commands COM tiiat arrive on die command bus 48 at edges of external clock signal CKIN, based upon die synchronous clock signal CKSYNC. Similarly, die logic control circuit 42 can activate die data latches 52 at a fixed phase relative to die external clock CLKIN. One skilled in die art will recognize from the following description tiiat timing of signals in the delay-locked loop 76 is dictated principally by falling edges of die buffered clock signal CKBUF. For the delay-locked loop 78, die inverter 74 converts rising edges of die buffered clock signal CKBUF to falling edges of the inverter buffered clock signal CKBUF*. Therefore, the delay- locked loop 78 responds to falling edges of die inverted buffered clock signal CKBUF*. The delay-locked loops 76, 78 can be substantially identical, because timing in botii delay-locked loops 76, 78 is controlled by falling edges. Therefore, only the first delay-locked loop 76 will be described in detail herein.

Figure 5 shows die delay-locked loop 76 in greater detail. The delay-locked loop 76 is formed from a variable delay line 86, a preset circuit 88, a race detection circuit 90 and a counter 92. The variable delay line 86 forms the principal delay element of the delay-locked loop 76 and receives die buffered clock signal CLKBUF at a pulse generator 94. The pulse generator 94 is a conventional circuit that responds to die falling edge of d e buffered clock signal CLKBUF at time 1₃ with a very brief high-going pulse, on die order of 0.5 nS, as shown in d e tiiird graph of Figure 6. One example of a suitable pulse generator 94 is shown in Figure 7 where d e pulse generator 94 is formed from a NAND gate 96 and inverters 98.

The output pulse from die pulse generator 94 begins at time , which is delayed slightly relative to die falling edge of die buffered clock signal CLKBUF at time t₃, due to the delay of the pulse generator 94. The output pulse from me pulse generator 94 drives a first inverter 100 to produce an inverted pulse at time 1₅. The inverted pulse at time ts drives a second inverter 102 and also drives a precharge input 104 of a capacitor bank 106. The effect of the inverted pulse on die capacitor bank 106 will be described first. When die inverted pulse arrives at the precharge input 104 at time ts, die inverted pulse briefly turns ON a bank of PMOS transistors 108 coupled in series with respective capacitors 110 between a supply voltage Vcc and ground. The ON PMOS transistors 108 provide current paths from the supply voltage Vcc to tiieir respective capacitors 110 to precharge the capacitors 110 toward die supply voltage Vcc during die time the pulse is low. The capacitor voltages Vc are coupled by respective selection switches 112 to a common node 114 which is also connected to die output of die second inverter 102. In a manner to be described below witii reference to Figure 9, selected ones of die selection switches 112 are turned ON by respective bits of a count signal COUNT so that die voltages on the selected capacitors 110 are provided to die common node 114 by die ON selector switches.

Because die capacitors 110 are coupled in parallel, die capacitance of d e capacitor bank equals the sum of die capacitors coupled to die common node 114. The capacitance of the bank is tinis controlled by die count signal COUNT. For example, if all of the bits of die count signal COUNT are high, all of the capacitors 110 are coupled to die common node 114 and die capacitance presented to die common node 114 equals die sum of all die capacitors' capacitances. To allow die capacitance to be varied in equal increments, each capacitor has a binarily weighted capacitance, where the weighting corresponding to the significant of die respective bit of die count signal COUNT. For example, the capacitor controlled by die most significant bit (far right) has twice the capacitance of the capacitor controlled by die second most significant bit. Likewise, the capacitor controlled by d e least significant bit (far left) has half the capacitance of die capacitor controlled by d e next least significant bit.

During a very brief period following time ts (i.e., before the second inverter 102 responds to die low transition from the first inverter), die ON PMOS transistors 108 charge the capacitors 110 while the second inverter 102 discharges me capacitors 110 dirough die common node 114. The PMOS transistors 108 have substantially more current capacity tiian the second inverter 102, so the common node voltage rises. At time t₆, which follows time ts only by die delay of die second inverter 102, the output of die second inverter 102 transitions high, thereby assisting die PMOS transistors 108 to quickly charge the capacitor voltages Vc to die supply voltage Vcc at time t . The rising edge of die pulse from die pulse generator 94 dius precharges the capacitors 110 to die supply voltage at time t .

The propagation of die leading edge of the pulse from the pulse generator 94 dirough die remaining portion of die variable delay line 86 does not affect the operation of the delay-locked loop 76, as can be seen from the following discussion. In response to d e high voltage at die common node 114, a tiiird inverter 116 applies a low to a NAND gate 118 at time t , as shown in the sixtii graph of Figure 6. The second input of die NAND gate 118 receives an inverted pulse from a reset pulse generator 120 and an inverter 122, as shown in the eightii graph of Figure 6. The inverted pulse arrives at die NAND gate 118 before the falling edge of die tiiird inverter output and establishes a high NAND gate output. Thus, die falling edge of die tiiird inverter output has no effect on the output of the NAND gate 118, because the inverted pulse from die inverter 122 has already driven die NAND gate output high at approximately time ts. By the time die inverted pulse applied to die NAND gate 118 ends at about time t₈, the output of the third inverter 116 has transitioned low. Therefore, the output of the NAND gate 118 does not transition low when the inverted pulse returns high.

The output of the NAND gate 118 forms the first delayed clock signal CLKal*, as shown in the seventii graph of Figure 6. Since the output of the NAND gate 118 is already driven high by die time die output of die inverter 116 goes low as described above, die leading edges of the first delayed clock signal CLKal* are initiated by die inverted pulses from the inverter 122 and die pulses are sustained by die output of die tiiird inverter 116.

The output of die NAND gate 118 also drives a delay block 124 formed from a NOR gate 126 and an inverter 127 that produces a first shifted delayed clock CLKbl*. However, die high-going transition of the delayed clock signal CLKal* does not affect the first shifted delayed clock signal CLKbl*, because die NOR gate 126 has received the pulse from the pulse generator 120 and its output has already been driven low before the first delayed clock CLKal* transitions high, as shown in the nintii graph of Figure 6. The output of die delay block 124 also drives a second delay block

130 to produce a second shifted delayed clock signal CLKcl* tiiat is delayed slightly relative to die first shifted delayed clock signal CLKbl*, as shown in die tenth diagram of Figure 6.

In addition to forming the second shifted delayed clock signal CLKcl*, die output of die second delay block 130 also drives a delay buffer 128 tiiat has a delay substantially equal to die delay of die buffer amplifier 46 (Figure 3). The delay buffer 128 produces a delayed feedback signal CLKFB that is delayed relative to the second shifted delayed clock signal CLKcl* by approximately d e time delay of d e buffer amplifier 46. The feedback clock signal CLKFB goes high at time tu in response to the transition of the second shifted delayed clock signal CLKcl* at time t₉.

As shown in Figure 8, the delay buffer 128 is formed from a series of inverters 133 and NOR gates 135, where d e second input of each NOR gate 135 is driven by die pulse generator 120. Each of die inverters 133 and NOR gates 135 delays die second shifted delayed clock signal CLKcl* by one gate delay.

The NOR gates 135 receive the reset pulse from die reset pulse generator 120 at tiieir second inputs. Because the reset pulse bypasses die inverters 100, 102, 116, me NAND gate 118, and the delay blocks 124, 130, reset pulse reaches die NOR gates 135 prior to any transitions caused by die pulse from the pulse generator 94. The high going reset pulse therefore sets the outputs of the NOR gates 135 low and tiius the feedback clock signal CLKFB high very shortly after the buffered clock signal CLKBUF transitions. The reset pulse prevents any transient signals from inadvertently causing a low going transition of the feedback clock signal CLKFB that would trigger the race detection circuit 90. One example of such an inadvertent low going transition may occur where the delay locked loop 86 is far from being locked. If die decaying output from the second inverter 102 is very slow, die input to die tiiird inverter 116 may fall below its threshold voltage just as a subsequent falling edge of die buffered clock signal CLKBUF arrives at the pulse generator 94 and tihe race detection circuit 90. Before the pulse from the pulse generator 94 reaches the third inverter 116, die tiiird inverter 116 outputs a high going transition in response to the decaying common node voltage. The high going transition from the third inverter 116 could cause a low going transition of die buffered clock signal CLKBUF if the reset NOR gates 135 did not ensure the buffered clock signal CLKBUF would remain high. Such an inadvertent low going pulse would trigger the race detection circuit and cause an improper incrementing or decrementing of die count signal COUNT.

To allow the delay of d e delay buffer 128 to be tuned to die specific delay of die buffer amplifier 46, four tapping switches 137 are coupled between various tapping locations in the chain of inverters 133 and die output of die delay buffer 128. The tapping switches 137 are conventional programmable switches, such as antifuses. When the switches are closed, tiiey bypass one or more pairs of the inverters 133, diereby reducing d e overall delay of d e delay buffer 128.

Returning to Figures 5 and 6, die response of die variable delay line 86 to the falling edge of die pulse from e pulse generator 94 will now be described. When the pulse from die pulse generator 94 returns low at time t , the output of the first inverter 100 transitions high, as shown in the fourth graph of Figure 6. The high output from the first inverter 100 turns OFF all of die PMOS transistors 108, diereby isolating the capacitors 110 from the supply voltage Vcc- Very shortly tiiereafter, at time tg, the output of the second inverter 102 attempts to transition low in response to me high-going transition of the output from the first inverter 100. However, the output of the second inverter 102 does not transition low immediately because die voltage of the common node 114 is sustained by die capacitors 110 dirough die ON selection switches 112. Consequently, die output of die second inverter decays according to an RC time constant defined by die output resistance of die inverter 102 and die capacitance of the capacitors 110 coupled to die common node 114. Because the capacitance of the bank is controlled by die count signal COUNT, the count signal COUNT also defines die decay rate of die second inverter output. The initial value of the count signal COUNT and tiius the initial decay rate may be selected based upon an anticipated average buffer delay time, or may simply begin at the lowest or highest value of the counter 92. The output of die tiiird inverter 116 transitions high at time tio when the voltage of the common node 114 decays to a direshold voltage Vj of the tiiird inverter 116, as shown in the fifth graph of Figure 6. The time between the high-going transition at the input of the second inverter 102 and die low- going transition of the third inverter 116 is thus determined by the count signal COUNT, because the count signal COUNT controls the decay rate of die common node voltage, as described above.

By d e time die tiiird inverter output transitions high at time tio, the precharge pulse from the inverter 122 has already returned high, as shown in die eighth graph of Figure 6. Therefore, when the output of the tiiird inverter 116 transitions high at time tio, the output of the NAND gate 118 (CLKal*) transitions low at time tn, which is delayed relative to time tio by the gate delay of die NAND gate 118. The falling edge of d e first clock signal CLKal* at time tn causes the first shifted delayed clock signal CLKbl* to transition low at time tπ and die second shifted delayed clock signal CLKcl* to transition low at time tι₃. The feedback clock signal CLKFB therefore transitions low at time tι_4> which is delayed relative to the second-shifted delayed clock signal CLKcl* by the delay time XBUF' of the delay buffer 128.

The feedback clock CLKFB and die buffered clock signal CLKBUF are input to first and second inputs of die race detection circuit 90. The race detection circuit 90 compares trailing edges of d e clock signals CLKFB, CLKBUF to determine whether d e feedback clock signal CLKFB leads, lags, or is substantially synchronized to die buffered clock signal CLKBUF.

If the feedback clock signal CLKFB leads the buffered clock signal CLKBUF by a delay time xi, as shown in the lowermost graph of Figure 6, the race detection circuit 90 outputs an active low UP* signal and a count pulse CPUL to the counter 92. In response to die active low UP* signal and die count pulse CPUL, the counter 92 increments the count signal COUNT, thereby incrementing die capacitance of die capacitor bank 106 as described above. The increased capacitance of die capacitor bank 106 increases die RC time constant to slow the decay rate of me next pulse output from me second inverter 102, as shown between times tι₆ and tn in the fifth graph of Figure 6.

The decreased decay rate of die second inverter output delays die low-going transition of die third inverter output until time tn. Consequently, the first delayed clock signal CLKal* transitions low at time tig and die feedback clock signal CLKFB returns low at time tι₉, which leads die buffered clock signal CLKBUF by a time delay τ₂, as shown in die lowermost graph of Figure 6. Because the high-to-low transition of the feedback clock signal CLKFB has been delayed due to d e increased capacitance of me capacitor bank 106, the lead time τ₂ of the feedback clock signal CLKFB relative to the buffered clock signal CLKBUF has been reduced relative to die original lead time However, the feedback clock signal CLKFB still leads the buffered clock signal CLKBUF. Therefore, the race detection circuit 90 outputs another active low UP* signal and count pulse CPUL to increment die counter 92 once again. The capacitance, and tiius decay time of the second inverter output, is increased further to further delay die transition of the third inverter output until time t₂o. The first delayed clock signal CLKal* tiierefore transitions low at time t₂ι and the feedback clock signal CLKFB transitions low at time t₂₂-

At time t₂₂, die falling edge of die feedback clock signal CLKFB is synchronized with die falling edge of die buffered clock signal CLKBUF. As will be described below witii reference to Figure 9, the race detection circuit 90 does not output a count pulse CPUL and die counter 92 does not increment die count signal COUNT, because die delay-locked loop 76 is substantially synchronized. One skilled in die art will recognize that, when the feedback clock signal CLKFB lags the buffered clock signal CLKBUF, die race detection circuit 90 can decrement die counter 92. The capacitance will tiius decrease, diereby reducing die delay time of die variable delay line 86 until the clock signals CLKFB, CLKBUF are synchronized. Figure 9 shows one circuit realization of d e race detection circuit

90. The race detection circuit 90 receives die feedback clock signal CLKFB at a first pulse generator 130 and d e buffered clock signal CLKBUF at a second pulse generator 132. Each of die pulse generators 130, 132 is similar in structure to die pulse generator 94 of Figure 7. Thus, the pulse generators 130, 132 produce short output pulses in response to falling edges of die clock signals CLKFB, CLKBUF, respectively.

The output pulses from the pulse generators 130, 132 are input to respective gating circuits 134, 136 tiiat include pairs formed by complementary pairs of transistors 138, 140 and 142, 144. In die first gating circuit 134, the gate of d e NMOS transistor 138 is controlled by a first control signal CONl and die gate of the PMOS transistor 140 is controlled by an inverted version of me first control signal CONl*. When die first control signal CONl is high, botii transistors 138, 140 are ON and die output of the pulse generator 130 is coupled to a first latch circuit 146. When die first control signal CONl is low, botii transistors 138,

140 are OFF, thereby isolating die first latch circuit 146 from die first pulse generator 130. Additionally, the inverted first control signal CONl* turns ON a reference transistor 150, thereby grounding die input of die first latch circuit 146 whenever die transistors 138, 140 are OFF. In the second gating circuit 136, die NMOS transistor 142 is controlled by a second control signal CON2 and die PMOS transistor 144 is controlled by an inverted second control signal CON2*. When die second control signal CON2 is high, die transistors 142, 144 are ON and die output of the second pulse generator 132 is coupled to a second latch circuit 148.

When the second conϋ^*ol signal CON2 is low, the transistors 142, 144 are OFF, thereby isolating the second latch circuit 148 from the second pulse generator 132. Additionally, the inverted second control signal CON2* turns ON a second reference transistor 152 to ground d e input of the second latch circuit 148.

The output of die first latch circuit 146 is buffered dirough a pair of inverters 154 to produce the UP* signal for the counter 92. Additionally, die outputs of botii of the latch circuits 146, 148 are input to an arbitration circuit 156 tiiat determines whetiier or not to produce die control pulse CPUL for the counter 92.

The operation of die race detection circuit 90 will now be explained for situations where the feedback clock signal CLKFB leads the buffered clock signal CLKBUF, where the feedback clock signal CLKFB lags the buffered clock signal CLKBUF, and where die feedback clock signal CLKFB is substantially synchronous with the buffered clock signal CLKBUF. Initially, both latch circuits 146, 148 output high signals CONl, CON2. Therefore, each gating circuit 134, 136 couples the output of its respective pulse generator 130, 132 to the input of its respective latch circuit 146, 148.

If the feedback clock signal CLKFB leads the buffered clock signal CLKBUF, the first pulse generator 130 outputs a high-going pulse prior to die second pulse generator 132. The pulse from the first pulse generator 130 passes directly dirough die gating circuit 134 to a first NOR gate 160 in the first latch circuit 146. In response to the high-going pulse, die first NOR gate 160 produces a low output tiiat forms the second control signal CON2. The low second control signal CON2 turns OFF die transistors 142, 144, thereby isolating the pulse generator 132 from the second latch circuit 148. Consequently, when the second pulse generator 132 outputs its pulse, die pulse does not reach die second latch circuit 148. As a result, die output of die second latch circuit 148 remains high if the output of the first latch circuit 146 transitions low first. The low transition of die first latch output passes through the buffer

154 to produce an active low UP* signal that is input to the counter 92. Additionally, die outputs of die latch circuits 146, 148 are applied to die arbitration circuit 156. Within die arbitration circuit 156, the low-going output of die first latch 146 causes a NAND gate 164 to output a high-going signal. Because botii inputs to d e NAND gate 164 were high previously, die low-going latch output causes die NAND gate output to transition high. The high output of the NAND gate 164 is delayed by a pair of delay circuits 166, 168 and tiien inverted at an inverter 169 to produce a delayed low-going signal. The delayed low-going signal is input to a diree-mput NOR gate 170 that receives the low UP* signal at a second input.

The third input to die three-input NOR gate 170 comes from a NOR gate 176 that is driven by die outputs of die latches 146, 148. Because d e second latch output is high, the NOR gate 176 provides a low signal to die tiiree- input NOR gate 170. Initially (i.e., before the high-going transition from the NAND gate 164 induces a low-going input to me ti ree-input NOR gate 170), the inverter 169 supplies a high voltage to the three-input NOR gate 170 that keeps the output of the NOR gate 176 high. Consequently, the low signal from the NOR gate 176 does not affect the output of the three-input NOR gate 170.

When the delayed rising edge from the NAND gate 164 causes the inverter 169 to provide a low-going signal to me tiiree-input NOR gate 170, all three inputs to the NOR gate 170 are low. In response, the output of the NOR gate 170 transitions high. The high transition is converted to a low transition by an inverter 172. The low-going transition is tiien applied to a pulse generator 173 tiiat produces die count pulse CPUL. Thus, the race detection circuit 90 provides an active low UP* signal and d e count pulse CPUL to the counter 92 in response to the feedback clock CLKFB leading die buffered clock signal CLKBUF, thereby incrementing die count signal COUNT. In addition to activating the three-input NOR gate 170, die high-going pulse from the NAND gate 164 is fed back dirough a delay circuit including a pulse generator 175 and buffer 177 to provide a reset pulse to reset the latch circuits 146, 148.

If the buffered clock signal CLKBUF leads die feedback clock signal CLKFB, the second pulse generator 132 outputs a pulse tiiat passes through the second gating circuit 136 to drive die output of the second latch circuit 148 low. The output of die second latch circuit 148 forms the first control signal CONl. Therefore, the low-going output of the second latch 148 turns OFF die transistors 138, 140, thereby isolating the first pulse generator 130 from the first latch circuit 146. When the first pulse generator 130 outputs a pulse, the OFF transistors 138, 140 block the pulse from reaching the first latch circuit 146. The output of the first latch circuit 146 therefore remains high and d e UP* signal remains inactive high.

The low-going transition from the second latch circuit 148 causes the output of die NAND gate 164 to transition high, thereby causing die inverter 172 to provide a low-going transition to the pulse generator 173. In response, the pulse generator 173 outputs d e count pulse CPUL. Thus, in response to die feedback clock signal CLKFB lagging die buffered clock signal CLKBUF, the race detection circuit 90 outputs an inactive high UP* signal and a count pulse CPUL to the counter 92, diereby causing the counter 92 to decrement die count signal COUNT.

If die falling edges of d e clock signals CLKBF, CLKBUF arrive substantially simultaneously, both pulse generators 130, 132 output pulses at approximately the same time. The pulses pass through the gating circuits 134, 136, thereby driving the outputs of both of die latch circuits 146, 148 low. Neitiier pulse is blocked because die pulses pass through die gating circuits 134, 136 before the control signals CONl, CON2 go low. The low output from the first latch circuit 146 causes the UP* signal to go active low. Additionally, the low outputs cause die NOR gate 176 in the arbitration circuit 156 to output a high signal to die tiiree-input NOR gate 170. The output of die tiiree-input NOR gate 170, which was already low due to the high output from the inverter 169, remains low. The low outputs from the latch circuits 146, 148 also cause die output of die NAND gate 164 to go high. The high-going output of die NAND gate 164 is delayed by die delay circuits 166, 168 and inverted by die inverter 169 to produce a delayed, low-going transition to the tiiree-input NOR gate 170. When the low-going signal from the inverter 169 reaches the tiiree-input NOR gate 170, die high signal has no effect on die tiiree-input NOR gate 170, because the NOR gate 176 has already pulled one input of die tiiree-input NOR gate 170 high. Consequently, the output of the three-input NOR gate 170 does not transition high in response to the low-going transition from the inverter 169. The inverter 172 therefore does not output a low-going transition to the pulse generator 173, and die pulse generator 173 does not supply a count pulse CPUL to the counter 92. Thus, the count signal COUNT from the counter 92 is neither incremented nor decremented. In summary, when the feedback clock signal CLKFB and d e buffered clock signal CLKBUF are substantially synchronized, the count signal COUNT remains constant and die delay of die delay line 86 remains unchanged.

Figure 10 is a block diagram of a computer system 200 that contains tiie memory device 70 and memory controller 44 of Figure 3. The computer system 200 includes a processor 202 for performing computer functions such as executing software to perform desired calculations and tasks. The processor 202 also includes command and data buses 210 to activate the memory controller 44. One or more input devices 204, such as a keypad or a mouse, are coupled to die processor 202 and allow an operator to manually input data thereto. One or more output devices 206 are coupled to die processor 202 to display or otherwise output data generated by die processor 202. Examples of output devices include a printer and a video display unit. One or more data storage devices 208 are coupled to die processor to store data on or retrieve data from external storage media (not shown). Examples of storage devices 208 and storage media include drives tiiat accept hard and floppy disks, tape cassettes and compact-disk read-only memories. While the invention has been described herein by way of exemplary embodiments, various modifications may be made witiiout departing from die spirit and scope of die invention. For example, although the delay- locked loop 76 has been described herein as being a clock source for a memory device 70, one skilled in die art will recognize tiiat die delay-locked loop 76 may be useful in many applications, including controlling timing within the memory controller 44 or in any other application tiiat utilizes a synchronized clock signal. Moreover, altiiough the capacitor bank 106 is described herein as being coupled to a single node, it may be desirable in some applications to include more than one capacitor bank 106 or to couple the capacitors 110 at separate locations along the variable delay circuit 88. Further, a variety of logic structures may be employed for die various components, including die pulse generators 94, 120, 130, 132 and arbitration circuit 156. Additionally, the counter 92 is described herein as being incremented or decremented by one when the feedback clock signal CLKFB leads or lags die buffered clock signal CLKBUF. One skilled in the art will understand tiiat the counter 92 may be incremented by values otiier than one and tiiat the delay-locked loops 76, 78 may be locked more quickly if a more sophisticated algoridim is employed for incrementing or decrementing the counter 92. Accordingly, die invention is not limited except as by d e appended claims.

Claims

1. A delay-locked loop adapted to produce a delayed output signal in response to an input signal at a selected frequency, comprising: a variable delay circuit having an input terminal, an output terminal, and a control input terminal, die delay circuit including a capacitor bank having a variable capacitance corresponding to a digital control signal adapted to be applied to die control input terminal, the delay circuit being operative to provide die delayed output signal at die output terminal in response to the input signal, the delayed output signal being delayed relative to die input signal by a delay corresponding to the capacitance; and a comparing circuit having a first input coupled to d e input terminal, a second input coupled to die output terminal, and a control output coupled to die control input terminal, the comparing circuit being configured to provide die digital control signal at the control output in response to the relative phases of the input signal and die delayed output signal.

2. The delay-locked loop of claim 1 wherein die comparing circuit includes: an edge comparing circuit including the first and second inputs and having a phase output providing an adjustment signal indicative of edges of die delayed output signal leading or lagging die input signal; and a counter having a counter input coupled to die phase output, die counter being operative to produce die digital signal and responsive to die adjustment signal to vary die digital signal in response to die adjustment signal to increase or decrease die capacitance.

3. The delay-locked loop of claim 2 wherein the edge comparing circuit includes a race circuit operative to output an up signal indicating an increase in the capacitance in response to the delay signal at die delay input terminal leading die input signal to die primary input terminal.

4. The delay-locked loop of claim 3 wherein die race circuit is further operative to output a down signal indicating an decrease in the capacitance in response to the delay signal at the delay input terminal lagging die input signal at me primary input terminal.

5. The delay-locked loop of claim 3 wherein die counter is responsive to die up signal and a count pulse to increment the digital signal and wherein he race circuit is further operative to output the count pulse in response to the delay signal at die delay input terminal leading d e input signal at d e primary input terminal.

6. The delay-locked loop of claim 5 wherein the race circuit further includes an arbitration circuit, the arbitration circuit being configured to inhibit the count pulse when the delay signal at the delay input terminal is substantially synchronized to die input signal at the primary input terminal,.

7. The delay-locked loop of claim 1 wherein the capacitor bank includes: a plurality of capacitors coupled in parallel; and a plurality of selection switches each coupled to respective ones of the capacitors, each selection switch being responsive to a selected bit of die digital control signal to selectively decouple the respective capacitor from the remaining capacitors.

8. The delay-locked loop of claim 7 wherein die variable delay circuit includes: a precharge circuit coupled to die capacitors and responsive to die input signal to precharge the capacitors to a selected voltage wherein d e edge comparing circuit includes a race circuit operative to output an up signal indicating an increase in die capacitance in response to d e delay signal at d e delay input terminal leading die input signal to die primary input terminal; a discharging circuit coupled to tiae precharge circuit and configured to controllably discharge the capacitors; a voltage detector having a detect input terminal coupled to die capacitors and a detector output terminal, die voltage detector being operative to produce a delayed intermediate signal when the capacitor voltage discharges below a selected tiireshold voltage; and an output stage having an input terminal coupled to d e detector output terminal and responsive to produce die delayed signal in response to the intermediate signal.

9. The delay-locked loop of claim 8 wherein die output stage includes a plurality of serially coupled fixed delay circuits.

10. The delay-locked loop of claim 9 wherein die output stage further includes a selectively programmable bypass circuit coupled in parallel with one or more of die fixed delay circuits.

11. A variable delay circuit for a delay-locked loop, comprising: an input terminal; an output terminal; a reference terminal; a first buffer having a first input coupled to d e first input terminal and a first buffer output; a second buffer having a second input coupled to die first buffer output, and a second buffer output coupled to die output terminal; a first capacitor selectively coupleable between the first buffer output and die reference terminal; a second capacitor selectively coupleable between die first buffer output and the reference terminal; and a first isolation switch serially coupled witii the first capacitor, between die first output and die first reference terminal, the first isolation switch having a first switching input and being responsive to a selection signal at the first switching input to selectively coupled the first capacitor between die first buffer output and the reference terminal.

12. The variable delay circuit of claim 11 wherein die second buffer is an inverter.

13. The variable delay circuit of claim 11 for use with a shifted input signal having a delay relative to a reference input signal, further including a model circuit serially coupled witii the first and second buffers having a model circuit delay corresponding to die delay of d e input signal.

14. The variable delay circuit of claim 13 wherein the model circuit includes: a serially connected chain of delay elements, serially coupled to die first and second buffers; and a programmable bypass circuit selectively programmable to bypass one or more of the delay elements.

15. The variable delay circuit of claim 11, further including a precharging circuit coupled to die first input terminal and responsive to a clock signal at die first input to precharge die first capacitor.

16. The variable delay circuit of claim 15, further comprising: a discharging circuit coupled to die precharging circuit and configured to controllably discharge die first capacitor; a voltage detector having a detect input terminal coupled to die first capacitor and a detector output terminal, the voltage detector being operative to produce a delayed intermediate signal when die capacitor voltage discharges below a selected threshold voltage; and an output stage having an input terminal coupled to die detector output terminal and responsive to produce die delayed signal in response to die intermediate signal.

17. The variable delay circuit of claim 16 for use witii a shifted input signal having a delay relative to a reference input signal, further including a model circuit serially coupled witii the first and second buffers having a model circuit delay corresponding to d e delay of die input signal.

18. The variable delay circuit of claim 17 wherein me model circuit includes: a serially connected chain of delay elements, serially coupled to die first and second buffers; and a programmable bypass circuit selectively programmable to bypass one or more of the delay elements.

19. A memory device responsive to an input clock signal, comprising: a command input terminal; a clock input terminal; a memory array; a buffer amplifier having an amplifier input coupled to die clock input terminal and a buffer output, die buffer amplifier being responsive to the input clock signal at die amplifier input to produce a buffered clock signal having a phase shift relative to the input clock signal; a delay-locked loop adapted to produce a phase shifted signals in response to die buffered clock signal, die delay-locked loop comprising: a variable delay circuit having an input terminal coupled to die buffer output, an output terminal, and a control input terminal, the delay circuit including a capacitor bank having a variable capacitance corresponding to a digital control signal adapted to be applied to die control input terminal, me delay circuit being operative to provide die delayed output signal at die output terminal in response to die buffered clock signal, die delayed output signal being delayed relative to d e buffered clock signal by a delay corresponding to die capacitance; and a comparing circuit having a first input coupled to die input terminal, a second input coupled to die output terminal, and a control output coupled to die control input terminal, the comparing circuit being configured to provide the digital control signal at die control output in response to die relative phases of the buffered clock signal and d e delayed output signal; and a control circuit having a command input coupled to die command input terminal, a clock input coupled to die output terminal of the delay-locked loop, and a control output coupled to die memory array, the control circuit being configured to control transfers of data into and out of die memory array in response to the delayed output signal.

20. The memory device of claim 19 wherein die variable delay circuit further includes a model circuit coupled between the output terminal and the second input, ti e model circuit having a model circuit delay corresponding to die delay of die buffer amplifier.

21. The memory device of claim 19 wherein die comparing circuit includes: an edge comparing circuit including d e first and second inputs and having a phase output, die edge comparing circuit being responsive to provide an adjustment signal indicative of edges of die delayed output signal leading or lagging d e input signal; and a counter having a counter input coupled to die phase output, die counter being operative to produce the digital signal and responsive to die adjustment signal to vary die digital signal in response to die adjustment signal to increase or decrease die capacitance.

22. The memory device of claim 21 wherein die edge comparing circuit includes a race circuit operative to output an up signal indicating an increase in the capacitance in response to die delay signal at die delay input terminal leading the input signal to the primary input terminal.

23. The memory device of claim 22 wherein die race circuit is further operative to output a down signal indicating an decrease in die capacitance in response to tiie delay signal at die delay input terminal lagging the input signal to die primary input terminal.

24. The memory device of claim 22 wherein die counter is responsive to die up signal and a count pulse to increment digital signal and wherein die race circuit is further operative to output die count pulse in response to die delay signal at die delay input terminal leading die input signal to the primary input terminal.

25. The memory device of claim 24 wherein die race circuit further includes an arbitration circuit, die arbitration circuit being configured to inhibit the count pulse when die delay signal at die delay input terminal is substantially synchronized to die input signal at die primary input terminal.

26. The memory device 19 wherein the capacitor bank includes: a plurality of capacitors coupled in parallel; and a plurality of selection switches each coupled to respective ones of die capacitors, each selection switch being responsive to a selected bit of die digital control signal to selectively decouple the respective capacitor from the remaining capacitors.

27. The memory device of claim 19 wherein the variable delay circuit includes: a precharge circuit coupled to the capacitors and responsive to the input signal to precharge die capacitors to a selected voltage wherein die edge comparing circuit includes a race circuit operative to output an up signal indicating an increase in die capacitance in response to die delay signal at die delay input terminal leading d e input signal to ti e primary input terminal; a discharging circuit coupled to die precharge circuit and configured to controllably discharge die capacitors; a voltage detector having a detect input terminal coupled to the capacitors and a detector output terminal, die voltage detector being operative to produce a delayed intermediate signal when die capacitor voltage discharges below a selected tiareshold voltage; and an output stage having an input terminal coupled to d e detector output terminal and responsive to produce d e delayed signal in response to the intermediate signal.

28. The memory device of claim 27 wherein tiie output stage includes a plurality of serially coupled fixed delay circuits.

29. The memory device of claim 28 wherein die output stage further includes a selectively programmable bypass circuit coupled in parallel with one or more of the fixed delay circuits.

30. A method of producing a substantially synchronized, delayed clock signal in response to an input clock signal, comprising the steps of: buffering the input clock signal to produce a buffered clock signal having a first delay relative to die input clock signal; charging a capacitor bank to a charged voltage in response to a first edge of die buffered clock signal; after charging the capacitor bank, controllably discharging die capacitor bank; monitoring die voltage of the capacitor bank; in response to die monitored voltage falling below a tiireshold voltage, producing an edge of a feedback clock signal; comparing the edge of die feedback clock signal to a second edge of d e buffered clock signal; if die edge of the feedback clock signal leads the second edge of die buffered clock signal, increasing die capacitance of die capacitor bank; and if die edge of die feedback clock signal lags the second edge of the buffered clock signal, decreasing die capacitance of the capacitor bank.

31. The method of claim 30, further including the step of producing a count signal to estabUsh the capacitance of the capacitor bank, wherein d e step of increasing the capacitance includes die step of incrementing or decrementing die count signal.

32. The method of claim 31, further including the steps of: dete╧Çnining if the edge of die feedback clock signal and die edge of die buffered clock signal are substantially synchronous; and if die edges of die feedback clock signal and the buffered clock signal are substantially synchronous, inhibiting the incrementing or decrementing of die count signal.

33. The method of claim 30 wherein die step of increasing the capacitance includes die step of coupling a plurality of capacitors in parallel.

34. The method of claim 30 wherein die step of comparing die edge of die feedback clock signal to die edge of the input clock signal includes die steps of: producing a first pulse in response to the edge of die feedback clock signal; producing a second pulse in response to die edge of die input clock signal; blocking a transmission path of the first pulse in response to the second pulse; blocking a transmission patii of the second pulse witii the first pulse; and determining if eitiier of the first or second pulses completed d e respective transmission path prior to the respective transmission path being blocked.

35. A metiiod of locking a delay-locked loop to an input clock signal, comprising the steps of: providing a digital count; producing a pulse in response to an edge of die input clock signal; delaying die pulse witii a delay circuit having a delay time corresponding to d e count to produce a feedback clock signal; comparing the feedback clock signal to d e input clock signal; producing a signal indicative of die feedback clock signal leading or lagging die input clock signal; if die feedback clock signal leads die input clock signal, incrementing or decrementing d e count; and increase die delay time in response to the incremented or decremented count.

36. The method of claim 35 wherein the step of delaying die pulse with a delay circuit includes the steps of: charging a capacitance to a selected voltage; controllably charging or discharging die capacitor in response to die pulse; detecting when die capacitor voltage passes a tiireshold voltage; and producing a delayed pulse in response to die capacitor voltage passing the tiireshold voltage.

37. The method of claim 36 wherein die step of increasing die delay time includes increasing the capacitance.

38. The method of claim 37 wherein die step of producing a signal indicative of d e feedback signal leading or lagging the input clock signal includes die steps of: applying die feedback signal to a first switch; applying the input clock signal to a second switch; if die feedback clock signal passes through the first switch, opening die second switch; if die input clock signal passes through die second switch, opening die first switch; detecting if the feedback clock signal passes dirough d e first switch; and detecting if die input clock signal passes through the second switch.

39. The method of claim 38, further including die steps of: if botii clock signals pass through d e respective switches, disabling incrementing or decrementing of the count.