WO1998031017A1 - Adjustable output driver circuit - Google Patents
Adjustable output driver circuit Download PDFInfo
- Publication number
- WO1998031017A1 WO1998031017A1 PCT/US1997/023801 US9723801W WO9831017A1 WO 1998031017 A1 WO1998031017 A1 WO 1998031017A1 US 9723801 W US9723801 W US 9723801W WO 9831017 A1 WO9831017 A1 WO 9831017A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- output
- transistors
- voltage
- output transistors
- type
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
- H03K17/164—Soft switching using parallel switching arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Definitions
- This invention relates generally to integrated circuits and particularly to data output drivers for high speed data transmission.
- Integrated circuits typically include a number of input/output pins which are used for communication with additional circuitry.
- an integrated memory device such as a dynamic random access memory (DRAM) includes both control inputs for receiving memory operation control signals, and data pins for bi-directional data communication with an external system or processor.
- DRAM dynamic random access memory
- the data transmission rate of modern integrated circuits is primarily limited by internal circuitry operating speeds.
- Communication networks can typically transmit signals between circuitry at a rate that is faster than the capacity of some integrated circuits.
- a group of integrated circuits can be combined on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data that is transmitted at a high speed.
- a group of memory devices such as DRAMs, static RAMs, or read only memories (ROM), can be connected to a common data bus.
- the data rate of the bus may be substantially faster than the feasible operating speed of the individual memories.
- Each memory therefore, is operated so that while one memory processes received data, another memory receives new data.
- the present invention describes an output driver circuit comprising output transistors having a control terminal, and electrically coupling an output node to a first voltage, and a control circuit coupled to the control terminal of the output transistors.
- the control circuit sequentially turns on or off the output transistors in response to a transition of an input signal received by the control circuit.
- the control circuit also comprises forcing circuitry for selectively forcing a signal on an internal control circuit node to the first or a second voltage.
- a synchronous memory device comprising an array of memory cells for storing data received on a data communication line, and an output driver circuit having an output node electrically coupled to the data communication line.
- the output driver provides data read from the array of memory cells.
- the output driver circuit comprises first output transistors for electrically coupling a first voltage to an output node, second output transistors for electrically coupling the output node to a second voltage, and a control circuit.
- the control circuit is coupled to a control terminal of each of the first and second output transistors for sequentially turning on or off the output transistors in response to respective transitions in first and second input signals received by the control circuit.
- the memory further comprises matching circuitry for matching an output load at the control terminal of each output transistor.
- the present invention is particularly useful for high speed data communications, such as in a synchronous memory including a dynamic random access memory (DRAM).
- DRAM dynamic random access memory
- Figure 1 is a schematic illustration of one embodiment of the present invention
- Figure 2 is a more detailed schematic of one embodiment of the output driver circuit of Figure 1;
- Figure 3 is a schematic of wave-shaping control circuitry of Figure 2 in more detail;
- Figure 4 is a schematic of one embodiment of sequence circuits of Figure 3.
- Figure 5 is a schematic of another embodiment of sequence circuits of Figure 3.
- Figure 6 is a graph illustrating the voltage vs. time waveforms of the output driver circuit of Figure 2;
- Figure 7 is a graph illustrating the voltage vs. time waveform of a DQ voltage of the output driver circuit of Figure 2 and a DQ' voltage of a typical output driver circuit;
- Figure 8 is a graph of waveforms resulting from a first unequal weighting of the output transistors
- Figure 9 is a graph of waveforms resulting from a second unequal weighting of the output transistors;
- Figure 10 is a more detailed schematic of another embodiment of the output driver circuit of Figure 1 ;
- Figure 11 is a timing diagram of the circuit of Figure 5;
- Figure 12 is a schematic of another embodiment of sequence circuits of Figures 3 or 10;
- Figure 13 is a timing diagram of the circuit of Figure 12;
- Figure 14 is a schematic of an alternate embodiment of the output driver circuit;
- Figure 15 is a schematic of an alternate embodiment of the output driver circuit.
- Figure 16 is a schematic of an alternate embodiment of the output driver circuit.
- the present invention is applicable to integrated circuit devices.
- the present invention can be embodied as an integrated circuit memory device.
- These memory devices include, but are not limited to, synchronous memories, dynamic random access memories (DRAM, or SDRAM), and static memories (SRAM).
- Figure 1 illustrates one embodiment of the present invention and the environment in which it is used.
- a memory device 80 is illustrated which includes a memory array 90.
- memory 80 has been simplified to focus on the feature particularly relevant to understanding the present invention. Necessary control and communication circuitry for the memory, therefore, have not been shown, but are known to those skilled in the art.
- Memory array 90 includes memory cells and read circuitry for reading data stored in the memory cells.
- Output driver circuit 100 receives the data read from memory array 90 as first input signal D at node 110 and its binary complement, second input signal DN, at node 120, and provides in response thereto an output signal DQ at output node 130.
- Output node 130 is electrically coupled to receiving node 140 through data communication line 150, which may include distributed interconnect, pad, and other resistance and capacitance both on and off the integrated circuit chip. Output node 130 is also electrically coupled to a termination power supply voltage, V term , at termination node 160 through termination resistor 170. First and second power supply voltages, such as V DD at node 180 and V ss at node 190 are provided to output driver circuit 100. V term is typically a voltage approximately midway between V DD and V ss .
- Figure 2 is a schematic illustration that illustrates one embodiment of the output driver circuit 100 in more detail.
- a first plurality 200 of output transistors such as P-type transistors 200A-C, have their drain terminals coupled together and to output node 130.
- Wave-shaping control circuit 202 provides independent control terminal signals at nodes 205 A-C to the respective gate terminals of P-type transistors 200 A-C.
- the source terminals of P-type transistors 200A-C are coupled together and to V DD through a first impedance 210.
- first impedance 210 comprises active devices such as P-type transistors 210A-C, having their drain terminals coupled together and to the source terminals at node 220 of each of P-type transistors 200A-C in the first plurality 200 of output transistors.
- P-type transistors 210A-C have their source terminals coupled together and to V DD at node 180.
- V OH level control circuit 212 provides independent control terminal signals at nodes 215 A-C to the respective gate terminals of P-type transistors 210A-C to programmably control first impedance 210 by varying how many and which of P-type transistors 210A- C are turned on.
- P-type transistors 210A-C that are turned on contribute to the effective value of the impedance between node 220 and V DD at node 180.
- P-type transistors 210A-C may have varying width/length aspect ratios, or may each comprise different multiples of instances of parallel- connected P-type transistors of the same width/length aspect ratio, or may otherwise be designed for optimizing the effective value of the impedance between node 220 and V DD at node 180 by permuting which of P-type transistors 210A-C are turned on.
- Impedance 210 forms a resistive divider with termination resistor 170, the impedance values of which determine the binary high logic voltage level, V OH , at output node 130.
- V OH level control circuit 212 by controlling which of P-type transistors 210A-C are turned on, controls the value of impedance 210 and, in turn, controls the value of V 0H .
- a second plurality 250 of output transistors such as N-type transistors 250A-C, have their drain terminals coupled together and to output node 130.
- Wave-shaping control circuit 202 provides independent control terminal signals at nodes 255A-C to the respective gate terminals of N-type transistors 250A-C.
- the source terminals of N-type transistors 250A-C are coupled together and to V ss through a second impedance 260.
- second impedance 260 comprises active devices such as N-type transistors 260A-C, having their drain terminals coupled together and to the source terminals at node 270 of each of N-type transistors 250A-C in the second plurality 250 of output transistors.
- N-type transistors 260A-C have their source terminals coupled together and to V ss at node 190.
- V OL level control circuit 272 provides independent control terminal signals at nodes 275 A-C to the respective gate terminals of N-type transistors 260A-C to programmably control impedance 260 by varying how many and which of N-type transistors 260A-C are turned on.
- N-type transistors 260 A-C that are turned on contribute to the effective impedance between node 270 and V ss at node 190.
- N-type transistors 260A-C may have varying width/length aspect ratios, or may each comprise different multiples of instances of parallel-connected N-type transistors of the same width/length aspect ratio, or may otherwise be designed for optimizing the effective impedance between node 270 and VSS at node 190 by permuting which of N-type transistors 260 A-C are turned on.
- Impedance 260 forms a resistive divider with termination resistor 170, the impedance values of which determine the binary low logic voltage level, V OL , at output node 130.
- V OL level control circuit 272 by controlling which of N-type transistors 260A-C are turned on, controls the value of impedance 260 and, in turn, controls the value of V 0L .
- first plurality 200 of output transistors, second plurality 250 of output transistors, first impedance 210, and second impedance 260 have each been described, for clarity of illustration, as comprising three field-effect transistors. However, it is understood that the exact number of said transistors may be selected according to individual design constraints without departing from the scope and spirit of the present invention.
- Wave-shaping circuit 202 includes sequence circuits 300A-B receiving at respective first and second input signals D and DN at input terminals 305 that are electrically coupled to respective nodes 110 and 120. Sequence circuits 300A-B respectively provide, in response thereto, sequentially time-delayed control terminal signals at output terminals 310 A-C that are electrically coupled to respective nodes 205 A-C and 255A-C. The sequentially time-delayed control terminal signals effect coupling of output node 130 to respective V DD at node 180 and V ss at node 190 through respective first plurality 200 and second plurality 250 of output transistors.
- sequence circuits 300A-B provide control over the slew rate of the voltage at output node 130, with the slew rate control being substantially independent of the V OH and V OL level control provided by first and second impedances 210 and 260, respectively.
- Figure 4 is a schematic illustration that illustrates one embodiment of each of sequence circuits 300A-B in more detail.
- Figure 4 includes a string of series-cascaded inverters 400A-F, for receiving an input signal at input terminal 305, and providing a number of sequentially delayed signals in response thereto at output terminals 310 A-C.
- the delay between the signal transition at the input terminal 305 and the signal transition at each of the output terminals 310A-C is determined by the inverter delays of the corresponding number of inverters therebetween, including interconnect capacitance and load capacitance of subsequent inverters and output transistors.
- Figure 5 is a schematic illustration that illustrates another embodiment of each of sequence circuits 300A-B in more detail.
- Figure 5 includes pairs of series-cascaded inverters 500A-F.
- Each pair of inverters such as pairs 500 A-B, 500C-D, 500E-F, receives the input signal at input terminal 305 and provide a sequentially delayed signal in response thereto at respective output terminals 31 OA-C.
- Each pair of inverters, such as pairs 500A-B, 500C-D, 500E-F has a capacitance interposed therebetween, such as respective capacitances 505A-C.
- the capacitances 505 A-C are preferably trimmably adjustable, such as by fuse or other programmable elements, for tailoring the delays between the signal transition at the input terminal 305 and the signal transition at each of the output terminals 310A-C.
- the capacitances are trimmed so that each delay path is different to provide a number of sequentially delayed signals at output terminals 310A-C.
- Figure 6 is a graph illustrating the voltage vs. time waveforms of the output driver circuit 100.
- signal A represents the voltage waveform at nodes 205 A and 255 A
- signal B represents the voltage waveform at nodes 205B and 255B
- signal C represents the voltage waveform at nodes 205C and 255 C
- signal DQ represents the voltage waveform at node 130.
- Figure 6 illustrates the slew-rate tailoring of transitions in the DQ signal in response to the sequentially delayed control terminal signals provided by wave- shaping control circuit 202.
- Figure 6 also illustrates the reduced signal swing, i.e. V OH and V OL voltage levels, provided by impedances 210 and 260 in conjunction with terminating resistor 170.
- Figure 7 is a graph illustrating the voltage vs. time waveform of the voltage DQ at output node 130 of output driver circuit 100 with respect to a voltage DQ' of a conventional output driver circuit without the slew-rate wave- shaping provided by the present invention.
- the slew rate of voltage transitions of the voltage DQ according to the output driver circuit 100 of the present invention may be controlled more precisely that the voltage transitions of the voltage DQ' according to the conventional output driver circuit.
- Figure 7 illustrates the case wherein each of the output transistors in the first plurality 200 and second plurality 250 are equally weighted; their effective width/length aspect ratios are substantially identical. As seen in Figure 7, this results in an approximately linear slew rate wave-shaping.
- Figure 8 is a graph, similar to Figure 7, in which the output transistors in the first plurality 200 and second plurality 250 of output transistors are not equally weighted.
- Figure 8 illustrates the case where the intermediate transistors, such as 200B and 250B, have effective width/length aspect ratios that are larger than the effective width/length aspect ratios of the end transistors, such as 200A, 200C, 250A, and 250C.
- the slew rate of the voltage DQ at output node 130 is faster near the midpoint between the V OH and V 0L levels.
- Figure 9 is a graph, similar to Figure 7, in which the output transistors in the first plurality 200 and second plurality 250 of output transistors are not equally weighted.
- Figure 9 illustrates the case where the intermediate transistors, such as 200B and 250B, have effective width/length aspect ratios that are smaller than the effective width/length aspect ratios of the end transistors, such as 200A, 200C, 250A, and 250C.
- the slew rate of the voltage DQ at output node 130 is faster near the each of the V OH and V OL levels than near the midpoint between these two levels.
- Figures 7-9 illustrate different approaches to weighting output transistors in each of the first plurality 200 and second plurality 250 of output transistors.
- Ones of the first plurality 200 of output transistors could also be weighted differently from ones of the second plurality 250 of output transistors; many combinations are possible in order to obtain the desired wave-shaping of the voltage DQ at output node 130.
- the output driver circuit 100 described above can suffer from rise and fall time imbalance. That is, Nodes 205 A-C and nodes 255A-C of Figure 2 could suffer from finite rise and fall time imbalance because the respective node loads are not equivalent.
- the load difference is primarily do to nodes 205 A-C driving P-type transistors and nodes 255A-C driving N-type transistors. In addition, the size of the N-type and P-type transistors are typically not equivalent.
- a P-type transistor fabricated as capacitor 604 is coupled between nodes 255A-C and ground
- an N-type transistor fabricated as capacitor 602 is coupled between nodes 255A-C and ground, as illustrated in Figure 10.
- matching circuitry for matching the output load is provided in one embodiment using capacitor connected transistors.
- Either of the sequence circuits described in Figures 4 and 5 can be used in the wave- shaping control circuit 202 of output driver circuit 600.
- an alternate sequence circuit can be used to reduce frequency dependancy, as explained below.
- Figure 11 illustrates the operation of one delay stage of cascaded inverters 500A and 500B, of Figure 5.
- the diagram illustrates the voltage at nodes 305, 306 and 310A. It will be appreciated that as the input signal (node 305) increases in frequency, node 306 does not reach full power rail. Thus, the output signal (node 310A) will have data dependent delays. That is, the rising edge of node 301 A is delayed from the rising edge of node 305 by time T, but the delay between the falling edge of node 310A and the falling edge of node 305 will be less than time T at higher frequencies.
- each delay stage of the circuit of Figure 5 which provide terminal signals 205 and 255 will have forcing circuitry 312.
- the forcing circuitry comprises P-type transistors 320 and 322, and N-type transistors 324 and 326. In operation, when the input (node 305) and output (node 310A) transition from a high logic state to low logic state, transistors 320 and 322 are activated and pull node 306 to V DD .
- FIG. 14 is a schematic illustration that illustrates an alternate output driver circuit 640.
- the first and second impedances 210 and 260, respectively, and corresponding V 0H and V OL level control circuits 212 and 272 of output driver circuit 600, are not present.
- N- type capacitors 602 and P-type capacitors 604 are included to balance the load of each stage of the output driver.
- Figure 15 is a schematic illustration that illustrates a single-ended alternate embodiment of the output driver circuit 100.
- the second plurality 250 of output transistors and second impedance 260 are not present.
- This embodiment offers slew rate and V OH level control of the voltage DQ at output node 130; the V 0L level is established at V terra by the resistive connection through termination resistors 170 to the termination voltage at node 160.
- Capacitors 602 are not required for this single-ended embodiment.
- Figure 16 is a schematic illustration that illustrates another single-ended alternate embodiment of the output driver circuit 100. In Figure 12, the first plurality 200 of output transistors and first impedance 210 are not present.
- This embodiment offers slew rate and V 0L level control of the voltage DQ at output node 130; the V 0H level is established at V term by the resistive connection through termination resistors 170 to the termination voltage at node 160. Again, because there only a single load, capacitors 604 are not required.
- the present invention includes method and apparatus of wave- shaping a signal, including logic voltage levels and a slew rate of a voltage transition therebetween.
- the present invention is particularly useful for high speed data communications, such as in a synchronous memory including a dynamic random access memory (DRAM).
- DRAM dynamic random access memory
- An output driver circuit which offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM).
- Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and V DD and V ss power supplies.
- Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal.
- Load compensating capacitors have been described for balancing the output loads and eliminating rise and fall time imbalances.
- delay element stages have been described which include feed forward and feed back circuitry to reduce data dependant delays during high frequency operation.
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT97953418T ATE206240T1 (en) | 1997-01-06 | 1997-12-18 | ADJUSTABLE OUTPUT DRIVER CIRCUIT |
KR10-1999-7006128A KR100489460B1 (en) | 1997-01-06 | 1997-12-18 | Adjustable output driver circuit |
AU57170/98A AU5717098A (en) | 1997-01-06 | 1997-12-18 | Adjustable output driver circuit |
EP97953418A EP0950247B1 (en) | 1997-01-06 | 1997-12-18 | Adjustable output driver circuit |
DE69707016T DE69707016T2 (en) | 1997-01-06 | 1997-12-18 | ADJUSTABLE OUTPUT DRIVER |
JP53091798A JP4288708B2 (en) | 1997-01-06 | 1997-12-18 | Adjustable output driver circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/779,344 | 1997-01-06 | ||
US08/779,344 US5838177A (en) | 1997-01-06 | 1997-01-06 | Adjustable output driver circuit having parallel pull-up and pull-down elements |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998031017A1 true WO1998031017A1 (en) | 1998-07-16 |
Family
ID=25116125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/023801 WO1998031017A1 (en) | 1997-01-06 | 1997-12-18 | Adjustable output driver circuit |
Country Status (8)
Country | Link |
---|---|
US (2) | US5838177A (en) |
EP (2) | EP0950247B1 (en) |
JP (2) | JP4288708B2 (en) |
KR (1) | KR100489460B1 (en) |
AT (2) | ATE227468T1 (en) |
AU (1) | AU5717098A (en) |
DE (2) | DE69707016T2 (en) |
WO (1) | WO1998031017A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002003553A1 (en) * | 2000-06-30 | 2002-01-10 | Intel Corporation | Buffer with compensating drive strength |
US6606705B1 (en) | 1999-09-15 | 2003-08-12 | Intel Corporation | Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level |
Families Citing this family (120)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5949254A (en) * | 1996-11-26 | 1999-09-07 | Micron Technology, Inc. | Adjustable output driver circuit |
US5838177A (en) * | 1997-01-06 | 1998-11-17 | Micron Technology, Inc. | Adjustable output driver circuit having parallel pull-up and pull-down elements |
JPH10326489A (en) * | 1997-05-26 | 1998-12-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
US6870419B1 (en) | 1997-08-29 | 2005-03-22 | Rambus Inc. | Memory system including a memory device having a controlled output driver characteristic |
US6094075A (en) | 1997-08-29 | 2000-07-25 | Rambus Incorporated | Current control technique |
US6111446A (en) * | 1998-03-20 | 2000-08-29 | Micron Technology, Inc. | Integrated circuit data latch driver circuit |
US6268748B1 (en) * | 1998-05-06 | 2001-07-31 | International Business Machines Corp. | Module with low leakage driver circuits and method of operation |
US6308231B1 (en) | 1998-09-29 | 2001-10-23 | Rockwell Automation Technologies, Inc. | Industrial control systems having input/output circuits with programmable input/output characteristics |
US6225825B1 (en) * | 1998-09-30 | 2001-05-01 | Rockwell Technologies, Llc | Industrial control systems having input/output circuits with programmable input/output characteristics |
US6298393B1 (en) | 1998-09-30 | 2001-10-02 | Rockwell Technologies, Llc | Industrial control systems having input/output circuits with programmable input/output characteristics |
US6184729B1 (en) * | 1998-10-08 | 2001-02-06 | National Semiconductor Corporation | Low ground bounce and low power supply bounce output driver |
US6380770B1 (en) | 1998-10-08 | 2002-04-30 | National Semiconductor Corporation | Low ground bounce and low power supply bounce output driver with dual, interlocked, asymmetric delay lines |
US6091260A (en) * | 1998-11-13 | 2000-07-18 | Integrated Device Technology, Inc. | Integrated circuit output buffers having low propagation delay and improved noise characteristics |
US6242942B1 (en) | 1998-11-13 | 2001-06-05 | Integrated Device Technology, Inc. | Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics |
US6356102B1 (en) | 1998-11-13 | 2002-03-12 | Integrated Device Technology, Inc. | Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals |
US6762621B1 (en) * | 1998-12-31 | 2004-07-13 | Actel Corporation | Programmable multi-standard I/O architecture for FPGAs |
US6172528B1 (en) | 1999-01-20 | 2001-01-09 | Fairchild Semiconductor Corporation | Charge sharing circuit for fanout buffer |
US6347367B1 (en) * | 1999-01-29 | 2002-02-12 | International Business Machines Corp. | Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures |
US6281729B1 (en) | 1999-06-07 | 2001-08-28 | Sun Microsystems, Inc. | Output driver with improved slew rate control |
US6278306B1 (en) | 1999-06-07 | 2001-08-21 | Sun Microsystems, Inc. | Method for an output driver with improved slew rate control |
US6339351B1 (en) | 1999-06-07 | 2002-01-15 | Sun Microsystems, Inc. | Output driver with improved impedance control |
US6366139B1 (en) | 1999-06-07 | 2002-04-02 | Sun Microsystems, Inc. | Method for an output driver with improved impedance control |
US6285215B1 (en) * | 1999-09-02 | 2001-09-04 | Micron Technology, Inc. | Output driver having a programmable edge rate |
US6294924B1 (en) * | 1999-09-20 | 2001-09-25 | Sun Microsystems, Inc. | Dynamic termination logic driver with improved slew rate control |
US6297677B1 (en) | 1999-09-20 | 2001-10-02 | Sun Microsystems, Inc. | Method for a dynamic termination logic driver with improved slew rate control |
US6316957B1 (en) | 1999-09-20 | 2001-11-13 | Sun Microsystems, Inc. | Method for a dynamic termination logic driver with improved impedance control |
US6420913B1 (en) | 1999-09-20 | 2002-07-16 | Sun Microsystems, Inc. | Dynamic termination logic driver with improved impedance control |
US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US7051130B1 (en) | 1999-10-19 | 2006-05-23 | Rambus Inc. | Integrated circuit device that stores a value representative of a drive strength setting |
US6646953B1 (en) | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
JP3490368B2 (en) * | 2000-02-07 | 2004-01-26 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Signal output device, driver circuit, signal transmission system, and signal transmission method |
US7194037B1 (en) | 2000-05-23 | 2007-03-20 | Marvell International Ltd. | Active replica transformer hybrid |
USRE41831E1 (en) | 2000-05-23 | 2010-10-19 | Marvell International Ltd. | Class B driver |
US7433665B1 (en) | 2000-07-31 | 2008-10-07 | Marvell International Ltd. | Apparatus and method for converting single-ended signals to a differential signal, and transceiver employing same |
US7312739B1 (en) | 2000-05-23 | 2007-12-25 | Marvell International Ltd. | Communication driver |
US6775529B1 (en) | 2000-07-31 | 2004-08-10 | Marvell International Ltd. | Active resistive summer for a transformer hybrid |
US6329836B1 (en) * | 2000-05-26 | 2001-12-11 | Sun Microsystems, Inc. | Resistive arrayed high speed output driver with pre-distortion |
US6496037B1 (en) * | 2000-06-06 | 2002-12-17 | International Business Machines Corporation | Automatic off-chip driver adjustment based on load characteristics |
US6256235B1 (en) * | 2000-06-23 | 2001-07-03 | Micron Technology, Inc. | Adjustable driver pre-equalization for memory subsystems |
US7606547B1 (en) | 2000-07-31 | 2009-10-20 | Marvell International Ltd. | Active resistance summer for a transformer hybrid |
US6618786B1 (en) * | 2000-08-28 | 2003-09-09 | Rambus Inc. | Current-mode bus line driver having increased output impedance |
US7079775B2 (en) | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
US6559690B2 (en) | 2001-03-15 | 2003-05-06 | Micron Technology, Inc. | Programmable dual drive strength output buffer with a shared boot circuit |
KR100383262B1 (en) * | 2001-03-19 | 2003-05-09 | 삼성전자주식회사 | Semiconductor memory device and data output method thereof |
US6597233B2 (en) | 2001-05-25 | 2003-07-22 | International Business Machines Corporation | Differential SCSI driver rise time and amplitude control circuit |
US6563337B2 (en) * | 2001-06-28 | 2003-05-13 | Intel Corporation | Driver impedance control mechanism |
US6359478B1 (en) | 2001-08-31 | 2002-03-19 | Pericom Semiconductor Corp. | Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor |
KR100401520B1 (en) | 2001-09-20 | 2003-10-17 | 주식회사 하이닉스반도체 | Low power operating mode type internal voltage-down power drive circuit |
US6525569B1 (en) | 2001-09-21 | 2003-02-25 | International Business Machines Corporation | Driver circuit having shapable transition waveforms |
US6657906B2 (en) * | 2001-11-28 | 2003-12-02 | Micron Technology, Inc. | Active termination circuit and method for controlling the impedance of external integrated circuit terminals |
DE10163461A1 (en) * | 2001-12-21 | 2003-07-10 | Austriamicrosystems Ag | Circuit arrangement for providing an output signal with adjustable slope |
US6639433B1 (en) | 2002-04-18 | 2003-10-28 | Johnson Controls Technology Company | Self-configuring output circuit and method |
US7119549B2 (en) * | 2003-02-25 | 2006-10-10 | Rambus Inc. | Output calibrator with dynamic precision |
US6737894B1 (en) | 2003-05-01 | 2004-05-18 | International Business Machines Corporation | Method and apparatus for generating impedance matched output signals for an integrated circuit device |
US7627790B2 (en) * | 2003-08-21 | 2009-12-01 | Credence Systems Corporation | Apparatus for jitter testing an IC |
US7173489B1 (en) | 2003-08-25 | 2007-02-06 | Marvell Semiconductor, Inc. | Programmable gain voltage buffer |
US6924660B2 (en) | 2003-09-08 | 2005-08-02 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
US7187206B2 (en) * | 2003-10-30 | 2007-03-06 | International Business Machines Corporation | Power savings in serial link transmitters |
US7019553B2 (en) * | 2003-12-01 | 2006-03-28 | Micron Technology, Inc. | Method and circuit for off chip driver control, and memory device using same |
US20050253744A1 (en) * | 2004-05-13 | 2005-11-17 | Johnson Controls Technology Company | Configurable output circuit and method |
US7088156B2 (en) * | 2004-08-31 | 2006-08-08 | Micron Technology, Inc. | Delay-locked loop having a pre-shift phase detector |
US7271626B1 (en) * | 2004-10-27 | 2007-09-18 | National Semiconductor Corporation | Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter |
KR100621770B1 (en) * | 2004-12-14 | 2006-09-19 | 삼성전자주식회사 | Semiconductor memory device and method for driving and testing the same |
US7215579B2 (en) | 2005-02-18 | 2007-05-08 | Micron Technology, Inc. | System and method for mode register control of data bus operating mode and impedance |
US7262637B2 (en) | 2005-03-22 | 2007-08-28 | Micron Technology, Inc. | Output buffer and method having a supply voltage insensitive slew rate |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
WO2007002324A2 (en) | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7580312B2 (en) | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US7590796B2 (en) | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US7312662B1 (en) | 2005-08-09 | 2007-12-25 | Marvell International Ltd. | Cascode gain boosting system and method for a transmitter |
US7577892B1 (en) | 2005-08-25 | 2009-08-18 | Marvell International Ltd | High speed iterative decoder |
GB2444663B (en) | 2005-09-02 | 2011-12-07 | Metaram Inc | Methods and apparatus of stacking drams |
KR100666177B1 (en) * | 2005-09-30 | 2007-01-09 | 삼성전자주식회사 | Out driver with mrs controlled preemphasis |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US20070205805A1 (en) * | 2006-03-03 | 2007-09-06 | Oliver Kiehl | Electrical system including driver that provides a first drive strength and a second drive strength |
WO2008001906A1 (en) | 2006-06-30 | 2008-01-03 | Nikon Corporation | Digital camera |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
JP4958719B2 (en) * | 2006-10-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
US7902875B2 (en) * | 2006-11-03 | 2011-03-08 | Micron Technology, Inc. | Output slew rate control |
US7646229B2 (en) * | 2006-11-03 | 2010-01-12 | Micron Technology, Inc. | Method of output slew rate control |
US7656209B2 (en) * | 2006-11-03 | 2010-02-02 | Micron Technology, Inc. | Output slew rate control |
KR100857854B1 (en) * | 2007-01-10 | 2008-09-10 | 주식회사 하이닉스반도체 | Semiconductor memory device with ability to effectively adjust operation time for on die termination |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
JPWO2010095378A1 (en) * | 2009-02-18 | 2012-08-23 | 株式会社アドバンテスト | Output device and test device |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
US9071243B2 (en) * | 2011-06-30 | 2015-06-30 | Silicon Image, Inc. | Single ended configurable multi-mode driver |
KR102021336B1 (en) * | 2012-12-20 | 2019-09-16 | 에스케이하이닉스 주식회사 | Semiconductor device and operating methode for the same |
US9391519B2 (en) | 2014-05-29 | 2016-07-12 | Analog Devices Global | Low quiescent current pull-down circuit |
KR102491576B1 (en) | 2017-11-08 | 2023-01-25 | 삼성전자주식회사 | Nonvolatile memory device |
US11114171B2 (en) | 2017-11-08 | 2021-09-07 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US10541013B1 (en) * | 2018-11-13 | 2020-01-21 | Advanced Micro Devices, Inc. | Headerless word line driver with shared wordline underdrive control |
US20210376827A1 (en) * | 2020-05-27 | 2021-12-02 | Nxp B.V. | Low emission electronic switch for signals with long transition times |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4829199A (en) * | 1987-07-13 | 1989-05-09 | Ncr Corporation | Driver circuit providing load and time adaptive current |
US4888498A (en) * | 1988-03-24 | 1989-12-19 | Texas Instruments Incorporated | Integrated-circuit power-up pulse generator circuit |
EP0382124A2 (en) * | 1989-02-10 | 1990-08-16 | National Semiconductor Corporation | Output buffer with ground bounce control |
EP0599631A1 (en) * | 1992-11-25 | 1994-06-01 | STMicroelectronics Limited | Controlled impedance transistor switch circuit |
JPH06326590A (en) * | 1993-05-14 | 1994-11-25 | Nec Corp | Semiconductor device and its manufacture |
Family Cites Families (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4096402A (en) * | 1975-12-29 | 1978-06-20 | Mostek Corporation | MOSFET buffer for TTL logic input and method of operation |
US4183095A (en) * | 1978-09-01 | 1980-01-08 | Ncr Corporation | High density memory device |
US4404474A (en) * | 1981-02-06 | 1983-09-13 | Rca Corporation | Active load pulse generating circuit |
US4638187A (en) * | 1985-10-01 | 1987-01-20 | Vtc Incorporated | CMOS output buffer providing high drive current with minimum output signal distortion |
GB2184622B (en) * | 1985-12-23 | 1989-10-18 | Philips Nv | Outputbuffer and control circuit providing limited current rate at the output |
JPS6337894A (en) * | 1986-07-30 | 1988-02-18 | Mitsubishi Electric Corp | Random access memory |
US4758743A (en) * | 1986-09-26 | 1988-07-19 | Motorola, Inc. | Output buffer with improved di/dt |
KR0141494B1 (en) * | 1988-01-28 | 1998-07-15 | 미다 가쓰시게 | High speed sensor system using a level shift circuit |
JPH01279631A (en) * | 1988-05-02 | 1989-11-09 | Toshiba Corp | Output circuit for semiconductor integrated circuit |
JPH02112317A (en) * | 1988-10-20 | 1990-04-25 | Nec Corp | Output circuit |
JPH02119427A (en) * | 1988-10-28 | 1990-05-07 | Nec Ic Microcomput Syst Ltd | Output buffer circuit |
JPH0666674B2 (en) * | 1988-11-21 | 1994-08-24 | 株式会社東芝 | Output circuit of semiconductor integrated circuit |
US5111075A (en) * | 1989-02-28 | 1992-05-05 | Vlsi Technology, Inc. | Reduced switching noise output buffer using diode for quick turn-off |
US4992676A (en) * | 1989-05-01 | 1991-02-12 | Motorola, Inc. | Output buffer having distributed stages to reduce switching noise |
US4961010A (en) * | 1989-05-19 | 1990-10-02 | National Semiconductor Corporation | Output buffer for reducing switching induced noise |
US4958088A (en) * | 1989-06-19 | 1990-09-18 | Micron Technology, Inc. | Low power three-stage CMOS input buffer with controlled switching |
US5165046A (en) * | 1989-11-06 | 1992-11-17 | Micron Technology, Inc. | High speed CMOS driver circuit |
JP2671538B2 (en) * | 1990-01-17 | 1997-10-29 | 松下電器産業株式会社 | Input buffer circuit |
US5239206A (en) * | 1990-03-06 | 1993-08-24 | Advanced Micro Devices, Inc. | Synchronous circuit with clock skew compensating function and circuits utilizing same |
US5023488A (en) * | 1990-03-30 | 1991-06-11 | Xerox Corporation | Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
US5243703A (en) * | 1990-04-18 | 1993-09-07 | Rambus, Inc. | Apparatus for synchronously generating clock signals in a data processing system |
US5134311A (en) * | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
US5001369A (en) * | 1990-07-02 | 1991-03-19 | Micron Technology, Inc. | Low noise output buffer circuit |
JPH0490620A (en) * | 1990-08-06 | 1992-03-24 | Seiko Epson Corp | Semiconductor device |
JPH04135311A (en) * | 1990-09-27 | 1992-05-08 | Nec Corp | Semiconductor integrated circuit |
US5122690A (en) * | 1990-10-16 | 1992-06-16 | General Electric Company | Interface circuits including driver circuits with switching noise reduction |
US5128563A (en) * | 1990-11-28 | 1992-07-07 | Micron Technology, Inc. | CMOS bootstrapped output driver method and circuit |
US5281865A (en) * | 1990-11-28 | 1994-01-25 | Hitachi, Ltd. | Flip-flop circuit |
US5150186A (en) * | 1991-03-06 | 1992-09-22 | Micron Technology, Inc. | CMOS output pull-up driver |
US5128560A (en) * | 1991-03-22 | 1992-07-07 | Micron Technology, Inc. | Boosted supply output driver circuit for driving an all N-channel output stage |
US5220208A (en) * | 1991-04-29 | 1993-06-15 | Texas Instruments Incorporated | Circuitry and method for controlling current in an electronic circuit |
US5194765A (en) * | 1991-06-28 | 1993-03-16 | At&T Bell Laboratories | Digitally controlled element sizing |
US5276642A (en) * | 1991-07-15 | 1994-01-04 | Micron Technology, Inc. | Method for performing a split read/write operation in a dynamic random access memory |
KR970005124B1 (en) * | 1991-08-14 | 1997-04-12 | 가부시끼가이샤 아드반테스트 | Variable delayed circuit |
JPH05136664A (en) * | 1991-08-14 | 1993-06-01 | Advantest Corp | Variable delay circuit |
US5220209A (en) * | 1991-09-27 | 1993-06-15 | National Semiconductor Corporation | Edge rate controlled output buffer circuit with controlled charge storage |
US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
DE4206082C1 (en) * | 1992-02-27 | 1993-04-08 | Siemens Ag, 8000 Muenchen, De | |
DE4345604B3 (en) * | 1992-03-06 | 2012-07-12 | Rambus Inc. | Device for communication with a DRAM |
US5355391A (en) * | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
JP3217114B2 (en) * | 1992-04-02 | 2001-10-09 | 富士通株式会社 | Semiconductor storage device |
US5278460A (en) * | 1992-04-07 | 1994-01-11 | Micron Technology, Inc. | Voltage compensating CMOS input buffer |
US5254883A (en) * | 1992-04-22 | 1993-10-19 | Rambus, Inc. | Electrical current source circuitry for a bus |
US5485490A (en) * | 1992-05-28 | 1996-01-16 | Rambus, Inc. | Method and circuitry for clock synchronization |
US5274276A (en) * | 1992-06-26 | 1993-12-28 | Micron Technology, Inc. | Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit |
US5311481A (en) * | 1992-12-17 | 1994-05-10 | Micron Technology, Inc. | Wordline driver circuit having a directly gated pull-down device |
US5347177A (en) * | 1993-01-14 | 1994-09-13 | Lipp Robert J | System for interconnecting VLSI circuits with transmission line characteristics |
JPH06282817A (en) * | 1993-03-29 | 1994-10-07 | Sharp Corp | Manufacturing apparatus of magnetic head |
US5488321A (en) * | 1993-04-07 | 1996-01-30 | Rambus, Inc. | Static high speed comparator |
US5347179A (en) * | 1993-04-15 | 1994-09-13 | Micron Semiconductor, Inc. | Inverting output driver circuit for reducing electron injection into the substrate |
US5367205A (en) * | 1993-05-13 | 1994-11-22 | Micron Semiconductor, Inc. | High speed output buffer with reduced voltage bounce and no cross current |
US5506814A (en) * | 1993-05-28 | 1996-04-09 | Micron Technology, Inc. | Video random access memory device and method implementing independent two WE nibble control |
US5428311A (en) * | 1993-06-30 | 1995-06-27 | Sgs-Thomson Microelectronics, Inc. | Fuse circuitry to control the propagation delay of an IC |
US5451898A (en) * | 1993-11-12 | 1995-09-19 | Rambus, Inc. | Bias circuit and differential amplifier having stabilized output swing |
JP3547466B2 (en) * | 1993-11-29 | 2004-07-28 | 株式会社東芝 | Memory device, serial-parallel data conversion circuit, method for writing data to memory device, and serial-parallel data conversion method |
JPH07153286A (en) * | 1993-11-30 | 1995-06-16 | Sony Corp | Non-volatile semiconductor memory |
US5400283A (en) * | 1993-12-13 | 1995-03-21 | Micron Semiconductor, Inc. | RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver |
KR0132504B1 (en) * | 1993-12-21 | 1998-10-01 | 문정환 | Data output buffer |
US5424672A (en) * | 1994-02-24 | 1995-06-13 | Micron Semiconductor, Inc. | Low current redundancy fuse assembly |
US5497115A (en) * | 1994-04-29 | 1996-03-05 | Mosaid Technologies Incorporated | Flip-flop circuit having low standby power for driving synchronous dynamic random access memory |
JPH07302144A (en) * | 1994-05-02 | 1995-11-14 | Hitachi Ltd | Interface circuit |
JP3553639B2 (en) * | 1994-05-12 | 2004-08-11 | アジレント・テクノロジーズ・インク | Timing adjustment circuit |
US5457407A (en) * | 1994-07-06 | 1995-10-10 | Sony Electronics Inc. | Binary weighted reference circuit for a variable impedance output buffer |
JP3537500B2 (en) * | 1994-08-16 | 2004-06-14 | バー−ブラウン・コーポレーション | Inverter device |
JP3176228B2 (en) * | 1994-08-23 | 2001-06-11 | シャープ株式会社 | Semiconductor storage device |
GB9417266D0 (en) * | 1994-08-26 | 1994-10-19 | Inmos Ltd | Testing a non-volatile memory |
US5486782A (en) * | 1994-09-27 | 1996-01-23 | International Business Machines Corporation | Transmission line output driver |
TW280027B (en) * | 1994-09-30 | 1996-07-01 | Rambus Inc | |
JPH08139572A (en) * | 1994-11-07 | 1996-05-31 | Mitsubishi Electric Corp | Latch circuit |
US5497127A (en) * | 1994-12-14 | 1996-03-05 | David Sarnoff Research Center, Inc. | Wide frequency range CMOS relaxation oscillator with variable hysteresis |
US5602494A (en) * | 1995-03-09 | 1997-02-11 | Honeywell Inc. | Bi-directional programmable I/O cell |
JP2783183B2 (en) * | 1995-03-09 | 1998-08-06 | 日本電気株式会社 | Output circuit |
US5621690A (en) * | 1995-04-28 | 1997-04-15 | Intel Corporation | Nonvolatile memory blocking architecture and redundancy |
JP3386924B2 (en) * | 1995-05-22 | 2003-03-17 | 株式会社日立製作所 | Semiconductor device |
US5581197A (en) * | 1995-05-31 | 1996-12-03 | Hewlett-Packard Co. | Method of programming a desired source resistance for a driver stage |
US5576645A (en) * | 1995-06-05 | 1996-11-19 | Hughes Aircraft Company | Sample and hold flip-flop for CMOS logic |
US5636173A (en) * | 1995-06-07 | 1997-06-03 | Micron Technology, Inc. | Auto-precharge during bank selection |
US5621340A (en) * | 1995-08-02 | 1997-04-15 | Rambus Inc. | Differential comparator for amplifying small swing signals to a full swing output |
JP3252666B2 (en) * | 1995-08-14 | 2002-02-04 | 日本電気株式会社 | Semiconductor storage device |
US5578941A (en) * | 1995-08-23 | 1996-11-26 | Micron Technology, Inc. | Voltage compensating CMOS input buffer circuit |
US5636174A (en) * | 1996-01-11 | 1997-06-03 | Cirrus Logic, Inc. | Fast cycle time-low latency dynamic random access memories and systems and methods using the same |
US5627791A (en) * | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
US5668763A (en) * | 1996-02-26 | 1997-09-16 | Fujitsu Limited | Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks |
US5838177A (en) * | 1997-01-06 | 1998-11-17 | Micron Technology, Inc. | Adjustable output driver circuit having parallel pull-up and pull-down elements |
-
1997
- 1997-01-06 US US08/779,344 patent/US5838177A/en not_active Expired - Lifetime
- 1997-12-18 AT AT00115868T patent/ATE227468T1/en not_active IP Right Cessation
- 1997-12-18 JP JP53091798A patent/JP4288708B2/en not_active Expired - Fee Related
- 1997-12-18 DE DE69707016T patent/DE69707016T2/en not_active Expired - Lifetime
- 1997-12-18 WO PCT/US1997/023801 patent/WO1998031017A1/en active IP Right Grant
- 1997-12-18 DE DE69716970T patent/DE69716970T2/en not_active Expired - Lifetime
- 1997-12-18 AU AU57170/98A patent/AU5717098A/en not_active Abandoned
- 1997-12-18 KR KR10-1999-7006128A patent/KR100489460B1/en not_active IP Right Cessation
- 1997-12-18 EP EP97953418A patent/EP0950247B1/en not_active Expired - Lifetime
- 1997-12-18 AT AT97953418T patent/ATE206240T1/en not_active IP Right Cessation
- 1997-12-18 EP EP00115868A patent/EP1056095B1/en not_active Expired - Lifetime
-
1998
- 1998-09-03 US US09/146,473 patent/US6069504A/en not_active Expired - Lifetime
-
2006
- 2006-03-20 JP JP2006076178A patent/JP2006180559A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4829199A (en) * | 1987-07-13 | 1989-05-09 | Ncr Corporation | Driver circuit providing load and time adaptive current |
US4888498A (en) * | 1988-03-24 | 1989-12-19 | Texas Instruments Incorporated | Integrated-circuit power-up pulse generator circuit |
EP0382124A2 (en) * | 1989-02-10 | 1990-08-16 | National Semiconductor Corporation | Output buffer with ground bounce control |
EP0599631A1 (en) * | 1992-11-25 | 1994-06-01 | STMicroelectronics Limited | Controlled impedance transistor switch circuit |
JPH06326590A (en) * | 1993-05-14 | 1994-11-25 | Nec Corp | Semiconductor device and its manufacture |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 095, no. 002 31 March 1995 (1995-03-31) * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6606705B1 (en) | 1999-09-15 | 2003-08-12 | Intel Corporation | Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level |
WO2002003553A1 (en) * | 2000-06-30 | 2002-01-10 | Intel Corporation | Buffer with compensating drive strength |
US6624662B1 (en) | 2000-06-30 | 2003-09-23 | Intel Corporation | Buffer with compensating drive strength |
Also Published As
Publication number | Publication date |
---|---|
EP1056095A2 (en) | 2000-11-29 |
JP4288708B2 (en) | 2009-07-01 |
DE69707016D1 (en) | 2001-10-31 |
AU5717098A (en) | 1998-08-03 |
KR100489460B1 (en) | 2005-05-16 |
EP0950247A1 (en) | 1999-10-20 |
DE69707016T2 (en) | 2002-02-14 |
ATE206240T1 (en) | 2001-10-15 |
KR20000069915A (en) | 2000-11-25 |
DE69716970D1 (en) | 2002-12-12 |
EP0950247B1 (en) | 2001-09-26 |
EP1056095A3 (en) | 2000-12-20 |
EP1056095B1 (en) | 2002-11-06 |
DE69716970T2 (en) | 2003-07-03 |
JP2006180559A (en) | 2006-07-06 |
US5838177A (en) | 1998-11-17 |
ATE227468T1 (en) | 2002-11-15 |
US6069504A (en) | 2000-05-30 |
JP2001508222A (en) | 2001-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5838177A (en) | Adjustable output driver circuit having parallel pull-up and pull-down elements | |
US5949254A (en) | Adjustable output driver circuit | |
US6133749A (en) | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance | |
US5391939A (en) | Output circuit of a semiconductor integrated circuit | |
JP6266514B2 (en) | Apparatus and method for transmitting differential serial signals including charge injection | |
US8471602B2 (en) | Output driver and semiconductor apparatus having the same | |
US7248088B2 (en) | Devices and methods for controlling a slew rate of a signal line | |
EP0228133A1 (en) | Outputbuffer and control circuit providing limited current rate at the output | |
US6366149B1 (en) | Delay circuit having variable slope control and threshold detect | |
US6963218B1 (en) | Bi-directional interface and communication link | |
US20030128047A1 (en) | Variable slew rate control for open drain bus | |
US6218854B1 (en) | Data line termination circuits and integrated circuit devices including attenuation circuit and charge/discharge circuit | |
US6373286B1 (en) | Integrated circuit with improved off chip drivers | |
US4933579A (en) | Output circuit for a semiconductor device for reducing rise time of an output signal | |
US6958626B2 (en) | Off chip driver | |
US8604828B1 (en) | Variable voltage CMOS off-chip driver and receiver circuits | |
JPH09238068A (en) | Output driver circuit with single through-rate resistor | |
US6294942B2 (en) | Method and apparatus for providing self-terminating signal lines | |
US5378950A (en) | Semiconductor integrated circuit for producing activation signals at different cycle times | |
US6191628B1 (en) | Circuit for controlling the slew rate of a digital signal | |
KR20000013843A (en) | Delay circuit in a semiconductor device | |
JPH10327133A (en) | Simultaneous two-way transmission system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW SD SZ UG ZW AT BE CH DE DK ES FI FR GB GR IE IT |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1997953418 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 1998 530917 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019997006128 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 1997953418 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWP | Wipo information: published in national office |
Ref document number: 1019997006128 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1997953418 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019997006128 Country of ref document: KR |