WO1998012849A1 - Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment - Google Patents
Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment Download PDFInfo
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- WO1998012849A1 WO1998012849A1 PCT/US1997/016349 US9716349W WO9812849A1 WO 1998012849 A1 WO1998012849 A1 WO 1998012849A1 US 9716349 W US9716349 W US 9716349W WO 9812849 A1 WO9812849 A1 WO 9812849A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
- H04L25/03133—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/003—Correction of carrier offset at baseband only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0053—Closed loops
Definitions
- the present invention relates to a demodulator for use in an asynchronous satellite communications system. More specifically, the present invention relates to a demodulator circuit and method for detection and transition sample estimation in a shared multi- carrier environment .
- the various carrier uplink transmissions are not clock-synchronous .
- the samples at the demultiplexer output are timed relative to the clock that controls the demultiplexer. Therefore, it is not possible to synchronize the demultiplexer output samples with the symbols of the various carriers.
- the number of samples used in the demodulator is ordinarily established by the need to sample the carrier signal appearing at the demodulator input at a rate that is a precise integer multiple of (e.g. usually twice) the symbol rate.
- the time phase of these samples must be adjusted to align the samples at the proper positions in each symbol.
- a sample interpolator has been typically used.
- the conventional interpolator function is computationally intensive, thus requiring a substantial amount of power.
- MCD multi- carrier demodulator
- DTSE Detection/Transition Sample Estimation
- DTSE utilizes the value and position of the two samples that bound the mid-symbol point to estimate the value of the detection sample, while the transition (end-of-symbol) sample is estimated in a similar manner.
- an additional stage of inter-symbol interference removal processing can be added to improve the value of the detection sample before symbol resolution.
- the above-cited paper contemplates the use of a high precision counter to keep track of relative sample position within a symbol, and then simply classifying each sample as L (left) , R (right) or ⁇ (unused) depending on the position within a symbol. It is a requirement for proper operation of a DTSE system that the first used sample be a left (L) sample and that the sample immediately following be a right (R) sample. However, due to timing corrections which may be made between samples, it is possible for the samples to be classified such that this requirement is not satisfied, e.g., with two successive samples being classified as L or R, an L sample followed by an unused sample, etc., resulting in faulty operation.
- a further problem with prior art in digital processing in general is that, in operation with multiple channels, there may be a significant time penalty in storing the register contents for one channel and retrieving from memory the information to be loaded into registers for continued processing of the next channel .
- the demodulator circuit includes an initial detection sample estimation circuit which receives the input data signal, takes a plurality of samples for each symbol of the input data signal and produces an estimated detection sample of the input data signal based on the plurality of samples, which may optionally be delivered to an inter-symbol interference (ISI) removal circuit. Also included in the demodulator circuit is a transition sample estimation circuit which receives the input data signal, takes a plurality of samples for each symbol of the input data signal and produces an estimated transition sample based on the plurality of samples.
- ISI inter-symbol interference
- the demodulator circuit also includes a clock loop error detection and loop filter circuit which receives the estimated transition sample and produces an estimated symbol timing correction value.
- the demodulator circuit further includes a relative position value generator circuit which produces a plurality of position values representing the position of each detection and transition sample in a symbol of the input data, the position values being determined in accordance with both the estimated symbol timing correction value produced by the clock loop error detection and loop filter circuit and in accordance with a known distance between successive samples .
- the demodulator circuit also includes a gate generator circuit which receives the plurality of position values and produces timing gate signals in accordance with a classification scheme. According to the present invention, when a sample is classified as being left of the mid-point, the next sample is forced to be classified as right of the mid-point, regardless of the position count. Similarly, after a sample that is classified as being before the transition point, the next sample will always be classified as after the transition point, regardless of the position count.
- the position values, together with the timing gate signals, are then used by various circuits of the demodulator circuit in order to control the selection of samples .
- the demodulator circuit may also be provided with a switching controller circuit which controls the demodulator circuit so that a plurality of channels may be processed by the demodulator circuit .
- each of the just-mentioned circuits in the demodulator circuit may be constituted by a plurality of shared register circuits which each include a register, an output device and a random access memory which stores data input from the register during a write cycle of the random access memory and outputs data to the output device for processing and storage in a subsequent register during a read cycle of the random access memory.
- the invention is also directed to a method of implementing and operating the demodulator described above .
- FIG. 1 is a block diagram of a multi-carrier demodulator (MCD) according to the present invention.
- FIG. 2 is a timing diagram showing symbol locations .
- FIG. 3A is a block diagram of an initial detection sample estimation circuit according to the present invention.
- FIG. 3B is a block diagram of a detection sample ISI removal circuit according to the present invention.
- FIG. 3C is a block diagram of a transition sample estimation circuit according to the present invention.
- FIG. 3D is a block diagram of a clock loop error detection and loop filter circuit according to the present invention.
- FIG. 3E is a block diagram of a P value and gate generator according to the present invention.
- FIG. 4 depicts a clock gate state machine diagram (LR) associated with an MCD which processes 2-3 samples/symbol in accordance with an aspect of the present invention.
- LR clock gate state machine diagram
- FIG. 5 depicts a clock gate state machine diagram (LR) associated with an MCD which processes 2-4 samples/symbol in accordance with another aspect of the present invention.
- LR clock gate state machine diagram
- FIG. 6 depicts a read gate state machine diagram according to the present invention.
- FIG. 7 depicts a read gate timing diagram according to the present invention.
- FIG. 8 depicts a shared register block diagram according to the present invention.
- the demodulator according to the present invention may be implemented as or included within an application specific integrated circuit (ASIC) for use as a multi- carrier demodulator (MCD) on-board a satellite.
- ASIC application specific integrated circuit
- MCD multi- carrier demodulator
- the demodulator can demodulate asynchronous samples in a multi-rate environment without the use of interpolating filters .
- the processing scheme can be used with asynchronous samples in the range of less than 2 to greater than 4 complex samples/symbol in a multi -rate environment of less than 64 kbits/s to greater than 25 Mbits/s.
- the inventive MCD may be made to operate in continuous or burst mode quadriphase-shi t keying (QPSK) , binary phase-shift keying (BPSK) or other modulation techniques.
- QPSK quadriphase-shi t keying
- BPSK binary phase-shift keying
- the inventive MCD also implements an all digital realization of carrier and clock synchronization.
- the present invention which incorporates aspects of the preliminary version of DTSE discussed in the above-mentioned paper, utilizes the value and position of the two samples that bound the mid-symbol point to estimate the value of the detection sample, while the transition (end-of-symbol) sample is estimated in a similar manner.
- an additional stage of inter-symbol interference removal processing is added to improve the value of the detection sample before symbol resolution.
- FIG. 1 which shows a block diagram of the MCD of the present invention
- a demultiplexed carrier signal associated with a specific channel, together with carrier signals for other channels is input to a digital carrier phase rotator circuit 100 in a time domain multiplexed fashion.
- the output of the carrier phase rotator circuit 100 which represents the phase and level corrected in-phase (I) and quadrature (Q) components of the input data signal, is passed to the initial detection sample estimation circuit 110 and the transition sample estimation circuit 120, which are both part of the above-mentioned DTSE scheme.
- Estimated in-phase and quadrature components associated with detection samples of the data input are output by the initial detection sample estimation circuit 110 to a carrier phase tracking circuit 130.
- the carrier phase tracking circuit 130 outputs a phase error signal in order to correct the phase of the in- phase and quadrature components of the data input .
- the carrier phase rotator circuit 100 removes the carrier phase and frequency offsets under the control of the carrier recovery loop included in the carrier phase tracking circuit 130, as follows. After the input samples are re-clocked, the carrier phase rotator circuit 100 performs the following well-known operations in order to facilitate the correction of the phase of the in-phase and quadrature components of the data input :
- the carrier phase tracking circuit 130, the AGC tracking circuit 140, and the clock loop error detection and loop filter circuit 170 may include the second order phase locked loop of the Joint Estimation and Detection (JED) demodulation scheme o described in detail in U.S. Patent 4,419,759, which is incorporated herein by reference .
- JED Joint Estimation and Detection
- An automatic gain control (AGC) tracking circuit 140 which also receives the output of the initial detection sample estimation circuit 110, outputs an s estimated level error signal which is used to correct the level of the in-phase and quadrature components of the data input.
- the AGC tracking circuit 140 can be implemented as a digital first order phase locked loop (PLL) .
- PLL phase locked loop
- a quadrature component generator 150 receives the phase error and estimated level error signals output by the carrier phase tracking circuit 130 and the AGC tracking circuit 140, respectively.
- the quadrature component generator 150 computes scaled cosine and sine 5 values and outputs them to the carrier phase rotator 100.
- the output of the carrier phase rotator 100 reflects the phase and level adjustments generated by the quadrature component generator 150.
- the in-phase and quadrature components of the estimated detection samples are also output from the initial detection sample estimation circuit 110 to a detection sample inter-symbol interference (ISI) removal circuit 160, which accounts for inter-symbol interference that adversely affects the values of the estimated detection samples generated by the initial detection sample estimation circuit 110.
- the output of the detection sample ISI removal circuit 160 corresponds to the final output of the MCD, the output being the in- phase and quadrature components of multi-bit soft decision output data.
- the transition sample estimation circuit 120 outputs estimated transition samples to a clock loop error detection and loop filter circuit 170, which, in turn, outputs an estimated symbol timing correction signal which is preferably at least 14 bits precision.
- the output of the clock loop error detection and loop filter circuit 170 is received by a P value and gate generator 180 which uses the estimated symbol timing correction signal to correct a free running P value.
- This corrected P value reflects the relative position of a sample in a symbol .
- the P value and gate generator 180 also receives an externally generated signal dP .
- the signal dP represents the expected distance between successive samples, i.e., the relative positioning of P values with respect to each other.
- Each P value associated with a sample will be spaced from the P value of the previous sample by an amount corresponding to the signal dP as adjusted by the timing correction signal .
- An externally generated signal, CASE provides information as to the range of samples per symbol in which the device is operating.
- the signal CASE is received by the initial detection sample estimation circuit 110, the detection sample ISI removal circuit 160 and the transition sample estimation circuit 120.
- the output of the P value and gate generator 180 includes P values and timing gate signals which are received by both registers and look-up tables .
- the timing gate signals determine whether symbols will be processed or ignored by the processing elements of the MCD of the present invention.
- the present invention includes internally closed carrier- and clock loops, which eliminates the need for external voltage controlled oscillators (VCOs) or numerically controlled oscillators (NCOs) .
- VCOs voltage controlled oscillators
- NCOs numerically controlled oscillators
- the initial detection sample estimation circuit 110, the detection sample ISI removal circuit 160, the transition sample estimation circuit 120, and the P value and gate generator 180 implement the DTSE scheme mentioned above, improved in accordance with the present invention.
- the DTSE scheme which relies on the use of the demodulation techniques discussed below, is an alternative to a conventional interpolating filter, and allows the MCD to operate directly on a non- integer number of samples per symbol .
- FIG. 2 depicts one example of a time diagram showing the available sample locations, the mid-symbol s sample location, and the symbol-edge sample locations associated with a specific symbol .
- the time diagram of FIG. 2 is for 2.718 samples per symbol which corresponds to about a 36.8% symbol separation between samples.
- An accumulator within the P value and gate generator 180 o (FIG. 1) keeps track of the relative sample position P within a symbol . Corrections to the accumulator are provided at regular intervals from the clock loop error detection and loop filter circuit 170 of FIG. 1.
- the symbol period is s taken as one unit and the sample locations within a symbol are expressed in Fig. 2 as a percentage of a symbol which corresponds to a P value.
- the mid-symbol sample has a P value of 50.
- the samples are classified as L 0 (Left of center) , R (Right of center) and z (not used) .
- the samples denoted z are the ones that are far from the mid-point of a symbol.
- there is little loss in performance in not including the z samples in the detection scheme because they are at the symbol edges.
- the sample can be classified as an L, R, or z, subject to the control of the Clock Gate State Machine and P Delay chain discussed below which are included in the P value and gate generator 180.
- a P value falling between 0 and 12, inclusive may be classified as a z .
- a P value falling between 13 and 49, inclusive may be classified as an L.
- the subsequent sample is then classified as R by the clock gate state machine.
- the transition samples are classified as "A" (After symbol edge) , "B" (Before symbol edge) or "x" (not used) .
- Samples which are classified as A or B are used to obtain a rough indication of zero crossings.
- the sample can be classified as A, B, or x, again subject to the control of the Clock Gate State Machine and P Delay chain included in the P value and gate generator 180.
- a P value falling between 0 and 37 will be classified as A.
- a P value falling between 38 and 62, inclusive may be classified as x
- a P value falling between 63 and 99, inclusive may be classified as B.
- the MCD of the present invention utilizes the Clock Gate State Machine and P Delay chain to ensure the proper classification.
- the detection scheme is a two-stage process. In the first stage, a preliminary decision is made regarding the value of the in-phase and quadrature (I and Q) components of the detection samples. This decision is rendered in the initial sample estimation circuit (element 110 of FIG. 1) and then refined in the second stage. The first stage is necessary due to the use of a non-integer number of samples per symbol. In essence, it represents a "simplified" interpolation process .
- the internal constitution of the initial sample estimation circuit 110 (FIG. 1) is shown in FIG. 3A.
- the key shown in FIG. 3A should also be used for FIGS. 3B-3E.
- the phase and level corrected in- phase and quadrature components of the data input from the carrier phase rotator circuit 100 (FIG. l) are routed through registers 25-28 in order to compensate for delays in the derivation of the P values for a DSE look-up table (LUT) which is embodied in a 256x8 ROM 300.
- the 256x8 ROM 300 receives as input a P value, the externally generated signal CASE, and an LRS signal output by the P value and gate generator 180 (FIG. 1) .
- the delayed in-phase and quadrature components of the data input are then applied to multipliers 310 and 320 together with detection sample estimation (DSE) coefficients output from the 256x8 ROM 300.
- DSE detection sample estimation
- W kl is a coefficient
- I kl and I kr are the left and right in- phase components of the detection path samples, respectively.
- the coefficient W kl or (1-W kl ) is selected by the LRS input to the 256x8 ROM which tells the LUT whether the L or R sample is at the multiplier input. The same operation is performed for the quadrature components of the L and R detection path sample.
- the coefficients kl and (1-W kl ) are preferably determined in accordance with the formulae for VI, and W r set forth later herein.
- the intermediate results, tl and t2 , for both the in-phase and quadrature components of the detection samples are provided to adders 330 and 340.
- An LR state signal (received from the Clock Gate State Machine discussed below) resets the adders 330 and 340 at the beginning of each symbol as required to give the correct sum operation.
- the outputs of the adders 330 and 340 are received by registers 31 and 32, with the outputs of the registers 31 and 32 being fed back to the input of the adders 330 and 340 to form accumulators 331 and 341 which produce an initial detection path estimated symbol .
- Registers 33 and 34 receive the outputs of the accumulators as inputs, re-clock the results at the symbol rate, and source the data pick-off for the carrier phase tracking circuit 130 (FIG. 1) , the AGC tracking circuit 140 (FIG. 1) and the detection sample ISI removal circuit 160 (FIG. 1) .
- the second stage of the above-mentioned detection scheme addresses two sources of degradation which result when the detection samples diverge from the mid-point sample position. These sources of degradation affect the estimated values of the in-phase and quadrature components of the detection samples which are output by the initial detection sample estimation circuit 110 (FIG. 1) .
- One source of degradation is inter-symbol interference (ISI) while the other is a loss of signal to noise ratio (SNR) .
- the second stage of the detection process is performed by the detection sample ISI removal circuit 160.
- the detection sample ISI removal circuit 160 With respect to the loss of SNR which results from the detection scheme of the present invention, consider a single pulse (no ISI) at the receiver after matched filtering. The matched filter maximizes the output SNR at the mid-symbol instant. If the mid-symbol sample value is not known and only the values and positions within the pulse of samples L and R are known, then the linear combination of L and R that maximizes the SNR in the decision is given by:
- h( ) is the impulse response of a raised cosine filter.
- the loss in SNR resulting from the use of the L and R samples instead of the mid-symbol sample is less than 0.1 dB. Therefore, the main source of degradation when using a combination of samples which are not at the detection point in the actual case of multiple pulse transmission is the ISI factor and not the loss of SNR. Accordingly, only a detection sample ISI removal circuit (element 160 of FIG. 1) is included in the MCD of the present invention, with no SNR signal loss compensation circuit. Nevertheless, if optimal performance is desired, a SNR signal loss compensation circuit could be incorporated in the MCD .
- the preliminary estimate of the n th detection sample S p (n) is revised, and a new estimate S(n) is computed as follows:
- D p (n) is the polarity of S p (n)
- is the magnitude of the ISI contribution to S p (n) from the proceeding symbol
- is the magnitude of the ISI contribution to S p (n) from the next symbol.
- the MCD of the present invention operates in an asynchronous system, in which the phase error estimate must be determined using the estimated in-phase and quadrature components of the detection samples .
- FIG. 1 shows the output of the initial detection sample estimation circuit 110 (FIG. 1) being used to obtain a phase error estimate
- the output of the detection sample ISI removal circuit 160 may be used instead.
- the estimated or ISI corrected in-phase and quadrature components of the detection samples both provide adequate results when estimating phase errors.
- the advantage in using the estimated in-phase and quadrature components of the detection sample is that the phase error estimate can be determined faster and the loops will be more stable, whereas the advantage of using the ISI corrected in-phase and quadrature components of the detection sample is that reduced noise is present in the estimated values so that the resulting phase errors are more accurate. Simulation results show that the rms jitter is almost identical in both cases.
- FIG. 3B shows the internal constitution of the detection sample ISI removal circuit of FIG. 1 which embodies the second stage of the above-mentioned detection scheme.
- Registers 35 and 36 receive the estimated in-phase and quadrature components of the detection samples (i.e. the next symbols I k and Q k ) and output the current symbols I k . ! and Q k . x to the registers 37 and 38, which, in turn, output the previous symbols I k _ 2 and Q k . 2 .
- the outputs of the registers 37 and 38 are received by 256x8 ROMs 345 and 350, respectively.
- the 256x8 ROMs 345 and 350 also receive the inputs (i.e. the next symbols I k and Q k ) of the registers 35 and 36, respectively.
- P values are also input to the 256x8 ROMS 345 and 350 along with the externally generated signal CASE.
- the P values are generated by the P value and gate generator 180 of FIG. 1 in the manner discussed below.
- the symbols I k _ 2 , I k , Q k _ 2 and Q k are used to address ISI look-up tables (LUTs) stored in the 256x8 ROMs 345 and 350.
- the ISI LUT has an offset compensation factor built in, to make up for the net effects of the offsets resulting from certain truncation operations and arithmetic compromises in the detection path.
- standard logic gates may also be configured by synthesis to perform the equivalent functions of the ISI look-up tables so that no ROMs are required.
- the outputs of the 256x8 ROMs 345 and 350 are received by adders 355 and 360 which also receive the output of the registers 35 and 36, respectively.
- the outputs of the adders 355 and 360 are received by registers 39 and 40, respectively.
- the registers 39 and 40 merely re-clock the in-phase and quadrature components of the multi-bit soft decision output data at a predetermined symbol rate for delivery to the outside world.
- the ROM 300 provides a coefficient output in accordance with the P value of the left sample and the CASE variable C.
- the address input could be four bits for a left sample P value and four bits for a right sample P value, for a total of 8 bits, and such an implementation is contemplated as an alternative within the scope of the present invention.
- the address could instead be a concatenation of the left sample P value and the inter-sample distance dP.
- the CASE variable C is used instead of the inter- sample distance dP.
- the performance of the MCD is not very sensitive to the precision of the value of the externally generated signal CASE.
- the signal CASE is represented in only 3 bits.
- the reduced number of bits allocated for the signal CASE cuts the size of the LUT in half, compared to the use of four bits which would be necessary if a separate P value where used for the right sample R.
- the CASE values may be selected as follows : sample/symbol CASE
- Data precision is held to 8 bits throughout the detection path while the gain is held to one as well. This is necessary to maintain maximum precision throughout and to avoid saturation during AGC transients. Eight bit precision was selected on the basis of early simulations as adjusted by considerations regarding AGC and dynamic range .
- FIG. 3C depicts the internal constitution of the transition sample estimation circuit 120 of FIG. 1.
- the transition sample estimation circuit shown in FIG. 3C computes the estimated transition sample described above. This step is necessary due to the use of a non- integer number of samples per symbol .
- the theory underlying the design of the transition sample estimation circuit is as follows. Since the positions of A and B are known quite accurately during tracking, then a very crude estimate of E, the value at the transition, can be readily obtained by assuming that A, B and E fall on a straight line. However, this will produce a biased estimate of zero crossings, because even in the absence of noise and inter-symbol interference caused by pulses before N or after N+l, A, B and E do not fall on a straight line. This bias is on the order of 2% of a symbol interval. However, it is possible to remove this bias since the filter shape is known (and thus the curve on which A, B and E fall in the absence of noise and ISI) .
- the hardware implementation of the transition sample estimation circuit is based upon the straight line approximation. However, it would be a straight forward matter to incorporate the above-mentioned bias removal .
- phase and level corrected in-phase and quadrature components of the data input from the carrier phase rotator circuit 100 of FIG. 1 are routed through registers 41-44 in order to compensate for delays in the derivation of the P values and passed to a TSE look-up table which is embodied in a 256x8 ROM 365.
- Registers 41-44 must be duplicated since they are gated with the BA gate instead of the LR gate to select the timing path samples instead of the detection path samples .
- the delayed in-phase and quadrature components of the data input are then applied to multipliers 370 and 375 together with TSE coefficients output from the 256x8 ROM 365.
- the coefficient A kb or (1- A kb ) is selected by a BAS signal which is input to the 256x8 ROM 365.
- the BAS signal tells the LUT whether the B or A sample is at the multiplier input.
- the BA state input is generated by the P value and gate generator 180, as discussed below.
- the same operations are performed for the quadrature components of the before and after transition path sample.
- the coefficients A kb and (1-A t ,) can be calculated based on a simple assumption of a value of -1 a half symbol before the transition to +1 at a half symbol after the transition, or can be adjusted to compensate for the 2% bias discussed above in manner that will be apparent to those of skill in the art.
- the outputs of the multipliers 370 and 375 are fed to adders 380 and 390, respectively.
- the outputs of the adders 380 and 390 are input to registers 45 and 46, respectively, with the outputs of registers 45 and 46 fed back to adders 380 and 390 to form accumulators 381 and 391.
- the adders 380 and 390 and the registers 45 and 46 also receive a BA state signal which is output by the P value and gate generator 180 in the manner discussed below.
- the outputs of the registers 45 and 46 are received by registers 47 and 48 which output an estimated transition sample EST to the clock loop error detection and loop filter circuit 170 of FIG. 1.
- the clock loop error detection and loop filter circuit 170 shown in FIG. 3D performs a well known differentiation operation with some simple logic gates 395 and 400 (XOR/0's) for the in-phase and quadrature component of the estimated transition sample.
- the logic associated with the in-phase component of the transition sample is derived from the following description:
- i k represents the current in-phase component of the transition sample
- i k . x represents the previously sampled in-phase component of the transition sample
- v ⁇ ' indicates bit inversion.
- This method of negation introduces a single least significant bit (LSB) error which has been shown by the emulation to be insignificant in this application.
- LSB least significant bit
- the symbol timing accumulator completes the front end of the first order clock recovery loop.
- This accumulator is 16 bits in size although only 14 bits are used at the output .
- a programmable barrel shifter which is represented by the jog in the bus which extends from the register 49 and the symbol timing accumulator 409.
- This barrel shifter sets the gain of the clock loop by scaling the error value fed to the adder.
- the nominal value for the scaling which is externally set by factors of two, is 3 bits. Taken together with fixed shifts in the path, this corresponds to a gain of 1/16 and a loop bandwidth of about 64 (Rs/Bl) . Note that the loop bandwidth is normalized by the reduction of the data to about 2 samples/symbol and does not need to change significantly from carrier to carrier.
- FIG. 3E depicts the internal constitution of the P value and gate generator 180 of FIG. 1.
- the P value and gate generator 180 of FIG. 1 embodies the clock gate state machine and P delay chain which together generate the gates necessary to select the appropriate samples at every stage of processing in the remaining portions of the MCD, thereby closing the clock loop.
- a free-running P value generator shown in FIG. 3E is comprised of an adder 415 and a register 2 which receives the output of the adder 415.
- the adder 415 receives as input the output of the register 2 and the externally generated signal dP.
- the value of dP is a function of the number of samples per symbol, and, indirectly, the carrier bit rate.
- dP is computed by the following formula:
- the value 16384 is a function of the fact that dP is represented in 14 bits.
- 14 bits are preferably used to represent the signal dP, a larger or smaller number of bits may also be used without departing from the scope of the invention.
- the externally generated signal dP is simply the change in position from one sample to the next as described in detail in the references.
- An adder 420 receives the output of the register 2 along with the signal PEST generated by the clock loop error detection and loop filter circuit 170 of FIG. 1. Initially, the P value assumes a random value. The timing correction signal is introduced in order to account for the fact that the estimated transition sample detected by the transition sample estimation circuit 120 at FIG. 1 may not be located at the actual transition point between samples. Thus, the sum of the output of the free running P generator and the timing correction signal generated by the clock loop error detection and loop filter circuit 170 of FIG. 1 yields the exact position or P value for the 'current' sample once the clock loop is locked.
- the current P value is output by a register 4 which receives the output of the adder 420.
- the current position or P value is applied to the clock gate state machine 425 and used to determine which samples are Left, Right, Before, and After values and which samples will be discarded.
- the current P value is also delayed by the P delay chain including registers 5 and 12-16 in order to derive the appropriate input values for the look-up tables mentioned above.
- the values in the P chain are treated as unsigned numbers by the clock gate state machine and for the purpose of selecting LUT addresses.
- the precision of registers 2, 4 and 5, and the related adders 415 and 420 shown in FIG. 3E are preferably 14 bits, while the registers 12-16 of the P delay chain are just wide enough to pass the required precision (generally 4 bits) .
- the adder 420 included in the free running P generator, rolls over by implementing modulo arithmetic in order to start each symbol over again nominally at zero (as adjusted by the timing offset from the timing accumulator) .
- the clock gate state machine 425 is designed to ensure that once a sample is selected as L or B, the next sample will always be used for R or A, respectively. Conventional methods of sample selection, including that contemplated in the 1990 paper by Soheil Sayegh, did not always fulfill this requirement.
- the clock gate state machine 425 takes as its inputs the current P value output by the register 4 and previous P value from register 5 and produces the LR and BA gate outputs . As indicated in the key for each register shown in FIGS. 3A-3E (the key is actually only shown in FIG. 3A, even though it corresponds to FIGS.
- XPLR and NewSymLR are generated from 14 bit comparators which are internal to the clock gate state machine 425 (8192 is a constant and is hard wired) .
- XPLR indicates a P value that is in front of the actual detection point by a distance of more than dP' and therefore will not be used (or, in other words, will be 'X'ed out), while NewSymLR indicates that a new symbol has begun as indicated by the fact that the current P value is smaller than the previous one.
- the state machine specification shown graphically in FIG. 4, is as follows: State XPBL; ⁇ See element 500 of FIG. 4 ⁇
- the symbols XPBA and NewSymBA are used to ensure that the correct BA and BAS gates are generated by a BA state machine designed in the same manner as the above- mentioned LR state machine.
- the clock gate state machine 425 may also be designed to handle from 2 to 4 samples per symbol in accordance with LR state machine specification provided below.
- the LR state machine specification for 2-4 samples per symbol processing is shown graphically in FIG. 5.
- clock gate state machine eliminates the need for a VCO or NCO in the clock recovery loop where the original clock does not have to be recreated. This can result in significant cost savings in high volume applications.
- the MCD must accommodate multiple carriers associated with different channels, it must swap intermediate results associated with a specific channel from a register to RAM on a channel switch signal. Nearly all of the registers in the device have such a RAM associated with them. Due to the complex relationship of sample and symbol clocks for different data rates, a sophisticated controller and read gate state machine are required to manage the above-described sharing operation.
- This on-chip RAM and control circuitry is embodied in the switching controller 190 and allows the single- chip MCD to demodulate an arbitrarily large number of QPSK continuous mode channels in a time shared fashion.
- tri-state outputs can be provided in order to allow multiple chips to be shared in order to handle still more channels and to provide for redundancy, while soft decision outputs can be provided which allow for the use of external Viterbi decoders.
- the operation of the switching controller 190 will be described in greater detail below.
- additional circuitry would be necessary to allow the demodulator hardware to handle a large number (e.g., up to 24) of carriers in a time shared fashion.
- This circuitry consists mainly of a number of, e.g., 24-word deep memories attached to almost every register in the device (indicated by the key shown in FIGS. 3A-3E) and the state machine to sequence the memory reads and writes at channel switch time.
- This process is controlled by the switching controller 190 (FIG. 1) , is orthogonal to the demodulation process and is shown in a separate block diagram and discussed at length below, including a detailed description of the shared register design and requisite state machines .
- the switching controller 190 receives externally generated control inputs or signals, block sync (BS) and switch (SW) . Internally, the switching controller 190 includes a channel address counter (not shown) and four read gate state machines (RGSMs) (not shown) . Switching controller 190 produces outputs to control reading, writing and addressing of the shared registers.
- BS block sync
- SW switch
- RGSMs read gate state machines
- the channel address counter included in the switching controller 190 is simply cleared by BS and incremented by SW. This sequences the address applied to the shared registers when the MCD is operating in non-DCS (dynamic channel switching) mode. When the MCD is operating in DCS mode, the channel address is supplied externally.
- the read gate state machines are required because, whenever a channel processing slot begins in shared mode, it is necessary not only to read the RAMs associated with the shared registers but also to hold the RAMs in read mode until their outputs can be clocked into the next stage. In other words, the simplest case would be to write the last value from channel N-l during the last clock time of channel N-l and to read the stored value for channel N during the first clock time of channel N.
- each read gate state machine takes as inputs the respective clock gate and the switch signal and outputs the related read gate signal . Only one RGSM will be described since they are duplicated four times, with only their inputs and outputs differing in each case.
- Each read gate state machine uses a truth table implementation to establish the state sequence.
- the logic realization of the truth table is combined with a simple register to complete the implementation.
- the switching controller 190 is not itself shared.
- An exemplary state diagram embodying the operation of each read gate state machine is shown is shown in Fig. 6 (expressions followed by an asterisk are merely included for completeness) .
- Each gate signal, LR, LRS, BA and BAS is active low. In normal operation, if the gate signal is low, it stays low until GIN (gate in) goes high. However, if the gate signal is high, it stays high until SW goes low. A clear always sets the gate to low (enabled) .
- the switching controller 190 is able to hold the read gate low until the clock has been enabled for the gate in question.
- FIG. 7 shows that a BARd signal (or BA read pulse) goes high one cycle after a BA signal goes high, while an LRRd signal does the same.
- the BASRd signal goes high one cycle later, only after a BAS signal has gone high, and the LRSRd signal goes high still another cycle later to reflect the even longer delay in the LRS signal .
- Ungated, but shared, registers are supplied with a switch (SW) signal delayed by one, which is, in effect, a read gate that is always one clock period long. The operation of the read gate at the destination is discussed below in conjunction with the shared register. All shared registers are passed the SW signal as the write strobe.
- SW switch
- the channel address is supplied by an external controller instead of the internal counter. Delays are matched to keep everything lined up.
- the SW signal is still supplied to the sharing controller to initiate reads and writes, however the generation of the WR strobe is inhibited when the chip is not selected (by RS, also generated by the external controller) to prevent the overwriting of data for channels of the same address that are being accessed on some other chip.
- RS also controls tri-stating the outputs to allow sharing of ASICs in the mid band. Finally, RS forces DV low to disable clocking on the chips that are not being used to reduce power consumption to minimal levels.
- the shared register is the heart of the multi- carrier capability of the MCD of the present invention.
- the shared register 700 may be implemented as four 8-bit registers 705-708 with a 24-by-32 bit RAM 710 attached thereto.
- the shared register 700 includes four multiplexers 715-718 and two AND logic gates 720 and 725. All but one of the shared registers in the MCD are set up to allow use as four separate 8-bit registers, while one is modified to be used in the carrier loop as two separate registers, one of 14 bits, and the other of 18 bits.
- the 32-bit-wide overall organization is dictated by efficiency of RAM utilization.
- RAMs larger than 32 bits wide might possibly have been more efficient, however they were not supported by the ASIC vendor memory compiler.
- all of the registers 705-708 of the shared register 700 act as ordinary latches when an input * a' of the corresponding multiplexer 715-718 is selected.
- input x b' is selected, and the outputs of the RAM 710 are available at the shared register output.
- all of the four 8-bit registers 705-708 have their gates and read inputs separately controlled. This allows them to be used in different places within modules with different gating requirements .
- the write enable (WEN) input of the RAM 710 is gated with the clock to ensure that timing requirements are met.
- the address for the RAMs is the channel ID input (CHID) , which selects the appropriate channel for writing or reading.
- the registers are effectively clock gated by the gate input .
- the circuitry shown supports gating by either DV or the LR, BA, LRS, or BAS gates. When either of these gate inputs are low, the register holds its contents constant, effectively freezing operation.
- this approach provides another significant advantage. Note that during the read cycle, the output of the RAM 710 is fed forward to the next stage rather than back into the present register. This allows the read cycle to also function as a processing cycle, reducing overhead significantly in applications with high channel switching rates. This is different from the classic time shared computer equivalent wherein the registers are restored with their original contents before processing resumes, effectively taking at least 2 cycles for every swapping operation (one write and one read) rather than one (the write cycle) as in this case.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97942485A EP0920764A4 (en) | 1996-09-20 | 1997-09-19 | Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment |
US09/269,241 US6278754B1 (en) | 1996-09-20 | 1997-09-19 | Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment |
AU44172/97A AU4417297A (en) | 1996-09-20 | 1997-09-19 | Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment |
CA002263679A CA2263679C (en) | 1996-09-20 | 1997-09-19 | Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2643196P | 1996-09-20 | 1996-09-20 | |
US60/026,431 | 1996-09-20 |
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WO1998012849A1 true WO1998012849A1 (en) | 1998-03-26 |
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PCT/US1997/016349 WO1998012849A1 (en) | 1996-09-20 | 1997-09-19 | Demodulation of asynchronously sampled data by means of detection-transition sample estimation in a shared multi-carrier environment |
Country Status (4)
Country | Link |
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EP (1) | EP0920764A4 (en) |
AU (1) | AU4417297A (en) |
CA (1) | CA2263679C (en) |
WO (1) | WO1998012849A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001059980A1 (en) * | 1999-03-19 | 2001-08-16 | Comsat Corporation | Dtse at less than two complex samples per symbol |
US7154971B2 (en) | 1999-03-19 | 2006-12-26 | Comsat Corporation | DTSE at less than two complex samples per symbol |
US8401108B1 (en) | 2008-09-11 | 2013-03-19 | L-3 Communications Corp | Modulation and demodulation of band-limited signals using near-Nyquist sampling |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5228062A (en) * | 1990-04-16 | 1993-07-13 | Telebit Corporation | Method and apparatus for correcting for clock and carrier frequency offset, and phase jitter in multicarrier modems |
US5317734A (en) * | 1989-08-29 | 1994-05-31 | North American Philips Corporation | Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies |
US5537435A (en) * | 1994-04-08 | 1996-07-16 | Carney; Ronald | Transceiver apparatus employing wideband FFT channelizer with output sample timing adjustment and inverse FFT combiner for multichannel communication network |
-
1997
- 1997-09-19 EP EP97942485A patent/EP0920764A4/en not_active Withdrawn
- 1997-09-19 AU AU44172/97A patent/AU4417297A/en not_active Abandoned
- 1997-09-19 CA CA002263679A patent/CA2263679C/en not_active Expired - Lifetime
- 1997-09-19 WO PCT/US1997/016349 patent/WO1998012849A1/en not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5317734A (en) * | 1989-08-29 | 1994-05-31 | North American Philips Corporation | Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies |
US5228062A (en) * | 1990-04-16 | 1993-07-13 | Telebit Corporation | Method and apparatus for correcting for clock and carrier frequency offset, and phase jitter in multicarrier modems |
US5537435A (en) * | 1994-04-08 | 1996-07-16 | Carney; Ronald | Transceiver apparatus employing wideband FFT channelizer with output sample timing adjustment and inverse FFT combiner for multichannel communication network |
Non-Patent Citations (1)
Title |
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See also references of EP0920764A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001059980A1 (en) * | 1999-03-19 | 2001-08-16 | Comsat Corporation | Dtse at less than two complex samples per symbol |
US7154971B2 (en) | 1999-03-19 | 2006-12-26 | Comsat Corporation | DTSE at less than two complex samples per symbol |
US8401108B1 (en) | 2008-09-11 | 2013-03-19 | L-3 Communications Corp | Modulation and demodulation of band-limited signals using near-Nyquist sampling |
Also Published As
Publication number | Publication date |
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CA2263679A1 (en) | 1998-03-26 |
EP0920764A1 (en) | 1999-06-09 |
EP0920764A4 (en) | 2006-03-01 |
AU4417297A (en) | 1998-04-14 |
CA2263679C (en) | 2003-07-08 |
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