WO1997050281A1 - Filter chip - Google Patents

Filter chip Download PDF

Info

Publication number
WO1997050281A1
WO1997050281A1 PCT/IL1996/000029 IL9600029W WO9750281A1 WO 1997050281 A1 WO1997050281 A1 WO 1997050281A1 IL 9600029 W IL9600029 W IL 9600029W WO 9750281 A1 WO9750281 A1 WO 9750281A1
Authority
WO
WIPO (PCT)
Prior art keywords
smd
circuit device
metal layer
passive circuit
passive
Prior art date
Application number
PCT/IL1996/000029
Other languages
French (fr)
Inventor
Pierre Badehi
Original Assignee
Shellcase Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shellcase Ltd. filed Critical Shellcase Ltd.
Priority to PCT/IL1996/000029 priority Critical patent/WO1997050281A1/en
Priority to AU62395/96A priority patent/AU6239596A/en
Publication of WO1997050281A1 publication Critical patent/WO1997050281A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041—Printed circuit coils
    • H01F41/042—Printed circuit coils by thin film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Disclosed is a technique for producing a multiple element SMD passive circuit device (200) having formed thereon a plurality of passive circuit elements (206) including waferwise forming a multiplicity of groups of passive circuit elements on a wafer, each group including a plurality of passive circuit elements having contact pads (214), waferwise forming SMD connection pads by depositing conductive material over the wafer in electrical conductive engagement with the passive circuit elements, and thereafter dividing the wafer into a multiplicity of multiple element SMD passive circuit devices.

Description

FILTER CHIP
The present invention relates to circuit de¬ vices generally and more particularly to surface mounted devices.
Various types of surface mounted circuit de¬ vices (SMDs) are known. The following U.S. Patents are believed to represent the state of the art: 4,453,199 and 5,166,656. Reference is also made to the following arti¬ cle: Electroless Bumping for TAB and Flip Chip by J. Simon et al ISHM '93 Proceedings, pp 439 - 444.
The present invention seeks to provide improved surface mounted circuit devices.
There is thus provided in accordance with a preferred embodiment of the present invention a technique for producing a multiple element SMD passive circuit device having formed thereon a plurality of passive circuit elements comprising: waferwise forming a multiplicity of groups of passive circuit elements on a wafer, each group including a plurality of passive circuit elements; waferwise forming at least one protective layer of material over the multiplicity of groups of passive circuit elements; waferwise forming SMD connection pads by depos¬ iting conductive material over the wafer in electrical conductive engagement with the passive circuit elements; and thereafter dividing the wafer into a multiplic¬ ity of multiple element SMD passive circuit devices.
Preferably, the step of waferwise forming a multiplicity of groups of passive circuit elements com¬ prises depositing at least one metal layer on a substrate and the step of waferwise forming at least one protective layer of material leaves at least one region of the at least one metal layer exposed, the technique also com¬ prising anti-corrosion treatment of the at least one region.
There is also provided in accordance with a preferred embodiment of the present invention a technique for producing an SMD circuit device comprising: forming at least one circuit element on a substrate including portions of exposed metal; carrying out anti-corrosion treatment of the portions of exposed metal; and forming SMD connection pads by depositing conductive material over the portions of exposed metal following the anti-corrosion treatment thereof, in elec¬ trical conductive engagement with the circuit elements.
Further in accordance with a preferred embodi¬ ment of the present invention there is provided a multi¬ ple element SMD passive circuit device having a 0603 size.
Additionally in accordance with a preferred embodiment of the present invention there is provided a multiple element SMD passive circuit device having a multiplicity of pads.
Further in accordance with a preferred embodi¬ ment of the present invention there is provided a SMD circuit device comprising: at least one circuit element on a substrate including portions of exposed metal subjected to anti- corrosion treatment; and
SMD connection pads formed by depositing con¬ ductive material over the portions of exposed metal following the anti-corrosion treatment thereof, in elec¬ trical conductive engagement with the circuit elements.
Preferably the SMD circuit device has a 0603 size and a multiplicity of SMD connection pads.
In accordance with a preferred embodiment of O 97/50281 PCML96/00029
the present invention, the SMD passive circuit device has formed thereon a plurality of passive circuit elements, such as resistors, capacitors and inductors.
Preferably, the SMD passive circuit device includes multiple pads arranged to have a pitch not exceeding 0.5 mm.
In accordance with one embodiment of the present invention, the circuit device comprises a plural¬ ity of capacitors and a plurality of resistors. Prefera¬ bly, certain portions of the plurality of capacitors also form part of the plurality of resistors.
There is also provided m accordance with a preferred embodiment of the present invention an SMD circuit device comprising: a first metal layer defining a plurality of disconnected segments of an induction coil; and a second metal layer, insulated from the first metal layer and defining interconnections for the plural¬ ity of disconnected segments.
Preferably, the second metal layer also defines a capacitance plate which, together with the first metal layer defines a capacitor. In accordance with a preferred embodiment of the present invention, the second metal layer also defines an induction coil.
Additionally in accordance with a preferred embodiment of the present invention there is provided an SMD circuit device comprising: a first metal layer; and a second metal layer, insulated from the first metal layer, the first and second metal layers being configured to define at least one inductor, at least one capacitor and at least one resistor and wherein certain portions of the at least one capacitor also form part of the at least one resistor and the at least one inductor.
The present invention will be understood more fully from the following detailed description, taken in conjunction with the drawings in which:
Figs. 1 and 2 are generalized flow chart illus¬ trations of a method for producing surface mounted cir¬ cuit devices constructed and operative in accordance with a preferred embodiment of the present invention;
Figs. 3A and 3B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in an induction circuit construct¬ ed and operative in accordance with a preferred embodi¬ ment of the present invention;
Figs. 4A and 4B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in an induction and capacitance circuit constructed and operative in accordance with a preferred embodiment of the present invention;
Fig. 4C is an illustration of the equivalent circuit corresponding to Figs. 4A and 4B;
Figs. 5A and 5B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a double induction and capaci¬ tance circuit constructed and operative in accordance with a preferred embodiment of the present invention;
Fig. 5C is an illustration of the equivalent circuit corresponding to Figs. 5A and 5B;
Figs. 6A and 6B are respective simplified illustrations of a conductive layer formed on a substrate and thus providing a resistance circuit constructed and operative in accordance with a preferred embodiment of the present invention;
Fig. 6C is an illustration of the equivalent circuit corresponding to Figs. 6A and 6B;
Figs. 7A and 7B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a resistance and capacitance circuit constructed and operative in accordance with a preferred embodiment of the present invention;
Fig. 7C is an illustration of the equivalent circuit corresponding to Figs. 7A and 7B;
Figs. 8A and 8B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a multiple capacitance network circuit constructed and operative in accordance with a preferred embodiment of the present invention;
Fig. 8C is an illustration of the equivalent circuit corresponding to Figs. 8A and 8B;
Figs. 9A and 9B are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a multiple inductance network circuit constructed and operative in accordance with a preferred embodiment of the present invention; and
Fig. 9C is an illustration of the equivalent circuit corresponding to Figs. 9A and 9B.
Reference is now made to Figs. 1 and 2, which are generalized flow chart illustrations of two varia¬ tions on a method for producing surface mounted circuit devices constructed and operative in accordance with a preferred embodiment of the present invention.
In accordance with a preferred embodiment of the present invention, one begins with a silicon wafer or other substrate and proceeds by waferwise forming a multiplicity of groups of active or passive circuit elements on the substrate, each .group including a plural¬ ity of circuit elements having contact pads.
Anti-corrosion treatment is applied to the contact pads. In a usual case, where the pads are formed of aluminum, the anti-corrosion treatment comprises conventional chromating.
Following the anti-corrosion treatment, at least one protective layer of photoimageable material, such as a suitable polyimide, is formed over the multi¬ plicity of groups of circuit elements and is imagewise exposed so as to provide physical access to the contact pads.
The next principal step is waferwise forming SMD connection pads by depositing aluminum over the wafer in electrical conductive engagement with the contact pads of the circuit elements. The SMD connection pads are not necessarily or normally the same size as the contact pads and accordingly they are preferably defined by photoli¬ thography.
In accordance with a preferred embodiment of the present invention, the SMD connection pads are thick¬ ened by electroless plating of zinc and subsequently nickel over the aluminum pads.
Following the electroless plating, the sub¬ strate is either solder dipped or electroless gold plat¬ ed. Following this step the substrate is typically divid¬ ed, as by sawing, into a multiplicity of multiple element SMD passive circuit devices.
The embodiment shown in Fig. 2 is identical to that shown in Fig. 1 with the following exception: The aluminum deposition of the SMD pads here precedes the formation of the protective polyimide layer. In this latter case, the electroless zinc and nickel coating takes place via openings in the polyimide layers.
Reference is now made to Figs. 3A and 3B, which are respective simplified illustrations of a first metal layer 50 and a second metal layer 52 formed thereover in an induction circuit constructed and operative in accord¬ ance with a preferred embodiment of the present inven¬ tion. An insulation layer 54 such as glass or polyimide is formed between the layers 50 and 52.
The first metal layer 50 defines a discontinu¬ ous induction coil 56 formed on a substrate 57. It can be seen that the second metal layer 52 defines jumper con¬ nections 58, which when joined to the discontinuous coil 56 define a continuous induction coil 60, having contact pads 62 and 64, as seen in Fig. 3B. It is appreciated that insulation layer 54 is necessary to prevent unwanted short circuits which would otherwise be caused by the jumper connections 58. Holes 66 are formed in layer 54 to permit electrical connections between the jumper connec¬ tions 58 and the discontinuous coil 56.
Reference is now made to Figs. 4A and 4B, which are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in an induction and capacitance circuit constructed and opera¬ tive in accordance with a preferred embodiment of the present invention.
The first metal layer 70 defines a discontinu¬ ous induction coil 72 formed on a substrate 74. It can be seen that a second metal layer 76 defines jumper connec¬ tions 78, which when joined to the discontinuous coil 72 define a continuous induction coil 80, having contact pads 82 and 84, as seen in Fig. 4B. It is a particular feature of the present invention that the second metal layer 76 also defines a partially cut away capacitor plate 86, which operates together with the first metal layer to provide a predetermined capacitance. It is appreciated that an insulation layer 88 is provided between the first and second metal layers 70 and 76 to prevent unwanted short circuits. Holes (not shown) are formed in layer 88 to permit electrical connections between the jumper connections 78 and the discontinuous coil 72. An electrical contact 92 is formed on the second metal layer 76.
Fig. 4C is an illustration of the LC equivalent circuit corresponding to Figs. 4A and 4B. It is seen that contact pads 82 and 84 define two ends of an inductor which is in capacitive relationship with a capacitor plate whose contact is defined by contact 92.
Reference is now made to Figs. 5A and 5B, which are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a double induction and capacitance circuit constructed and operative in accordance with a preferred embodiment of the present invention.
The first metal layer 100 defines a discontinu¬ ous induction coil 102 formed on a substrate 104. It can be seen that a second metal layer 106 defines jumper connections 108, which when joined to the discontinuous coil 102 define a continuous induction coil 110, having contact pads 112 and 114, as seen in Fig. 5B. It is a particular feature of the present invention that the second metal layer 106 not only defines a partially cut away capacitor plate 116, which operates together with the first metal layer to provide a predetermined capaci¬ tance, but also defines a continuous induction coil 118. It is appreciated that an insulation layer 120 is provid¬ ed between the first and second metal layers 100 and 106 to prevent unwanted short circuits. Holes (not shown) are formed in layer 120 to permit electrical connections between the jumper connections 108 and the discontinuous coil 102. An electrical contact 124 is formed on the second metal layer 106.
Fig. 5C is an illustration of the L-LC equiva¬ lent circuit corresponding to Figs. 5A and 5B. It is seen that contact pads 112 and 114 define two ends of an inductor which is in capacitive relationship with an inductor-capacitor circuit whose contact is defined by contact 124. The coil 118 is seen to be in parallel electrical relationship with the capacitor defined by the two metal layers 100 and 106.
Reference is now made to Figs. 6A and 6B, which are respective simplified illustrations of a conductive layer formed on a substrate and defining a resistance circuit constructed and operative in accordance with a preferred embodiment of the present invention. The conductive layer 130 may be formed of a metal or alterna- tively of a non-metallic conductor and defines a succes¬ sion of resistors 132 having contact pads 134 therebe¬ tween. When the conductive layer 130 is not formed of metal, the contact pads 134 should be metallized.
Fig. 6C is an illustration of the equivalent circuit corresponding to Figs. 6A and 6B. It is seen that the particular arrangement shown in Figs. 6A - 6C pro¬ vides resistance values at each successive pair of con¬ tact pads which are double those at the preceding pair of contact pads. Any other suitable arrangement of resistors may alternatively be provided.
Reference is now made to Figs. 7A and 7B, which are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a resistance and capacitance circuit constructed and opera¬ tive in accordance with a preferred embodiment of the" present invention.
The first metal layer 140 defines a resistor 142 of any suitable type having contact pads 144 and 146. It can be seen that a second metal layer 148 defines a capacitor plate 150 formed on a substrate 152, which is in capacitive relationship with resistor 142, across an insulative layer 154. Insulative layer 154 defines a via 156 through which electrical contact can be made to capacitor plate 150 at a contact location 158.
Fig. 7C is an illustration of the RC equivalent circuit corresponding to Figs. 7A and 7B. It is seen that contact pads 144 and 146 define two ends of a resistor which is in capacitive relationship with a capacitor plate whose contact is defined by contact location 158.
Reference is now made to Figs. 8A and 8B, which are respective simplified illustrations of a first metal layer and a second metal layer formed thereover in a multiple capacitance network circuit constructed and operative in accordance with a preferred embodiment of the present invention. O 97/50281 PCML96/00029
10
A first metal layer 180 defines a capacitor plate 182 which is in capacitive relationship across an insulative layer 184 with a second metal layer 186, having defined thereon a plurality of capacitor plates 188 of various sizes, having contact locations 189. The insulative layer 184 is formed with a via 190 in order to permit electrical contact with a contact location 192 on the capacitor plate 182.
Fig. 8C is an illustration of the equivalent circuit corresponding to Figs. 8A and 8B. It is seen that a plurality of parallel capacitors having differing capacitances are provided.
Reference is now made to Figs. 9A and 9B, which are respective simplified illustrations of a first metal layer 200 and a second metal layer 202 formed thereover in an induction circuit constructed and operative in accordance with a preferred embodiment of the present invention. An insulation layer 204 such as glass or polyimide is formed between the layers 200 and 202.
The first metal layer 200 defines a series of discontinuous induction coils 206 formed on a substrate 208. It can be seen that the second metal layer 202 defines jumper connections 210, which when joined to the discontinuous coils 206 define a series of induction coils 212, interconnected by respective contact pads 214, as seen in Fig. 9B. It is appreciated that insulation layer 204 is necessary to prevent unwanted short circuits which would otherwise be caused by the jumper connections 210. Holes 216 are formed in layer 204 to permit electri¬ cal connections between the jumper connections 210 and the discontinuous coils 206.
Fig. 9C is an illustration of the equivalent circuit corresponding to Figs. 9A and 9B. It is seen that a plurality of inductors 212 are interconnected by con¬ tact pads 214.
It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims which follow:

Claims

C L A I M S
1. A technique for producing a multiple element SMD passive circuit device having formed thereon a plu¬ rality of passive circuit elements comprising: waferwise forming a multiplicity of groups of passive circuit elements on a wafer, each group including a plurality of passive circuit elements having contact pads; waferwise forming at least one protective layer of material over said multiplicity of groups of passive circuit elements; waferwise forming SMD connection pads by depos¬ iting conductive material over said wafer in electrical conductive engagement with said passive circuit elements; and thereafter dividing the wafer into a multiplic¬ ity of multiple element SMD passive circuit devices.
2. A technique according to claim 1 wherein: said waferwise forming a multiplicity of groups of passive circuit elements comprises depositing at least one metal layer on a substrate; and said waferwise forming at least one protective layer of material leaves at least one region of said at least one metal layer exposed, said technique also com¬ prising anti-corrosion treatment of said at least one region.
3. A technique for producing an SMD circuit device comprising: forming at least one circuit element on a substrate including portions of exposed metal; carrying out anti-corrosion treatment of said portions of exposed metal; and forming SMD connection pads by depositing conductive material over said portions of exposed metal following said anti-corrosion treatment thereof, in electrical conductive engagement with said circuit ele¬ ments.
4. A multiple element SMD passive circuit device having a 0603 size.
5. A multiple element SMD passive circuit device having a multiplicity of pads.
6. A multiple element SMD passive circuit device according to claim 1 having a multiplicity of SMD connec¬ tion pads.
7. An SMD circuit device comprising: at least one circuit element on a substrate including portions of exposed metal subjected to anti- corrosion treatment; and
SMD connection pads formed by depositing con¬ ductive material over said portions of exposed metal following said anti-corrosion treatment thereof, in electrical conductive engagement with said circuit ele¬ ments.
8. An SMD circuit device according to claim 7 and having a 0603 size.
9. An SMD circuit device according to claim 7 and having a multiplicity of SMD connection pads.
10. A multiple element SMD passive circuit device according to claim 7 and having formed thereon a plurali¬ ty of passive circuit elements.
11. An SMD circuit device according to any of claims 4 - 10 and wherein the circuit device comprises a plurality of resistors.
12. An SMD circuit device according to any of claims 4 - 11 and including multiple pads arranged to have a pitch not exceeding 0.5 mm.
13. An SMD circuit device according to any of claims 4 - 10 and 12 and wherein the circuit device comprises a plurality of capacitors.
14. An SMD circuit device according to any of claims 4 - 13 and wherein the circuit device comprises a plurality of capacitors and a plurality of resistors.
15. An SMD circuit device according to claim 14 and wherein certain portions of said plurality of capacitors also form part of said plurality of resistors.
16. An SMD circuit device comprising: a first metal layer defining a plurality of disconnected segments of an induction coil; and a second metal layer, insulated from said first metal layer and defining interconnections for said plu¬ rality of disconnected segments.
17. An SMD circuit device according to claim 16 and wherein said second metal layer also defines a capaci¬ tance plate which, together with said first metal layer defines a capacitor.
18. An SMD circuit device according to claim 16 or claim 17 and wherein said second metal layer also defines an induction coil.
19. An SMD circuit device comprising: a first metal layer; and a second metal layer, insulated from said first metal layer, said first and second metal layers being configured to define at least one inductor, at least one capacitor and at least one resistor and wherein certain portions of said at least one capacitor also form part of said at least one resistor and said at least one inductor.
PCT/IL1996/000029 1996-06-27 1996-06-27 Filter chip WO1997050281A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/IL1996/000029 WO1997050281A1 (en) 1996-06-27 1996-06-27 Filter chip
AU62395/96A AU6239596A (en) 1996-06-27 1996-06-27 Filter chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IL1996/000029 WO1997050281A1 (en) 1996-06-27 1996-06-27 Filter chip

Publications (1)

Publication Number Publication Date
WO1997050281A1 true WO1997050281A1 (en) 1997-12-31

Family

ID=11061662

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL1996/000029 WO1997050281A1 (en) 1996-06-27 1996-06-27 Filter chip

Country Status (2)

Country Link
AU (1) AU6239596A (en)
WO (1) WO1997050281A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342143A (en) * 1974-02-04 1982-08-03 Jennings Thomas A Method of making multiple electrical components in integrated microminiature form
US4383886A (en) * 1980-11-14 1983-05-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor element
US4486738A (en) * 1982-02-16 1984-12-04 General Electric Ceramics, Inc. High reliability electrical components
US4494100A (en) * 1982-07-12 1985-01-15 Motorola, Inc. Planar inductors
US4543553A (en) * 1983-05-18 1985-09-24 Murata Manufacturing Co., Ltd. Chip-type inductor
US4890383A (en) * 1988-01-15 1990-01-02 Simens Corporate Research & Support, Inc. Method for producing displays and modular components
US4905358A (en) * 1989-01-18 1990-03-06 Motorola, Inc. Thin film active trimmable capacitor/inductor
US5398400A (en) * 1991-12-27 1995-03-21 Avx Corporation Method of making high accuracy surface mount inductors

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342143A (en) * 1974-02-04 1982-08-03 Jennings Thomas A Method of making multiple electrical components in integrated microminiature form
US4383886A (en) * 1980-11-14 1983-05-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor element
US4486738A (en) * 1982-02-16 1984-12-04 General Electric Ceramics, Inc. High reliability electrical components
US4494100A (en) * 1982-07-12 1985-01-15 Motorola, Inc. Planar inductors
US4543553A (en) * 1983-05-18 1985-09-24 Murata Manufacturing Co., Ltd. Chip-type inductor
US4890383A (en) * 1988-01-15 1990-01-02 Simens Corporate Research & Support, Inc. Method for producing displays and modular components
US4905358A (en) * 1989-01-18 1990-03-06 Motorola, Inc. Thin film active trimmable capacitor/inductor
US5398400A (en) * 1991-12-27 1995-03-21 Avx Corporation Method of making high accuracy surface mount inductors

Also Published As

Publication number Publication date
AU6239596A (en) 1998-01-14

Similar Documents

Publication Publication Date Title
KR100229572B1 (en) Laminar stackable circuit board structure and manufacture
US5398400A (en) Method of making high accuracy surface mount inductors
US7557014B2 (en) Semiconductor system-in-package
EP0013460B1 (en) Miniaturized multi-layer flat electrical coil
CA1182583A (en) Thin film discrete decoupling capacitor
US6285542B1 (en) Ultra-small resistor-capacitor thin film network for inverted mounting to a surface
US5197170A (en) Method of producing an LC composite part and an LC network part
US4629681A (en) Method of manufacturing multilayer circuit board
WO1999041019A1 (en) Individual, embedded capacitors for laminated printed circuit boards
US20040150966A1 (en) Integrated library core for embedded passive components and method for forming electronic device thereon
US6545225B2 (en) Module with thin-film circuit
US20210298172A1 (en) Circuit board
EP0788121A1 (en) Staggered horizontal inductor for use with multilayer substrate
US7023073B2 (en) Noise shield type multi-layered substrate
US5196089A (en) Multilayer ceramic substrate for mounting of semiconductor device
EP0713358A2 (en) Circuit board
WO1997050281A1 (en) Filter chip
JPH05509198A (en) Method for manufacturing multilayer thin film structure
US20010004314A1 (en) Module with thin-film circuit comprising a trimmable capacitor
US6597056B1 (en) Laminated chip component and manufacturing method
JP2699980B2 (en) Wiring board with a film element inside
KR100673537B1 (en) A low temperature cofired ceramic on metal and method of producing the same
JPH08288102A (en) Electronic component and its manufacture
RU2629714C2 (en) Multilayer multifunction gis board and method of its manufacture
JPH0572177U (en) Circuit module with multi-layer substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IL IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG US UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 98502623

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase