WO1997039596A1

WO1997039596A1 - Adapter for data transmission between a mobile telephone and a data terminal

Info

Publication number: WO1997039596A1
Application number: PCT/BE1997/000046
Authority: WO
Inventors: Johan Van Daele; Serge Gommers; Ben Cober
Original assignee: Option International
Priority date: 1996-04-15
Filing date: 1997-04-15
Publication date: 1997-10-23
Also published as: BE1010266A4; AU2376497A

Abstract

The present invention relates to an adapter for data tarnsmission between a mobile telephone and a data terminal, which adapter comprises a card and a cable, which card is provided to be connected to the data terminal, which cable is provided to be connected, on the one hand, to the mobile telephone and, on the other hand, to the card and wherein the telephone is provided with a generator for generating clock and synchronisation signals. According to the invention, the adapter comprises an interface which is provided, on the one hand, for receiving data characters from the card independently from said clock signals and for differentiating synch characters and data characters from each other and for transmitting each of the data characters in an assigned time slot to the telephone, and which interface is provided, on the other hand, for providing a predetermined number of clock signals to the card, under control of a synchronisation signal.

Description

"Adapter for data transmission between a mobile telephone and a data terminal."

The present invention relates to an adapter for data transmission between a mobile telephone and a data terminal, which adapter comprises a card and a cable, which card is provided to be connected to the data terminal, which cable is provided to be connected, on the one hand, to the mobile telephone and, on the other hand, to the card and wherein the telephone is provided with a generator for generating clock and synchronisation signals Such an adapter is known from EP-A-0 655 873 and is provided to be used in modern digital cellular systems, such as for example the known GSM system ("Global System for Mobile communication") In such a system, different services are offered to the user, which are subdivided in three categories telecommunication, transmission and additional services

Telecommunication services are services which enable users to perform data transmission such as telephone calls, emergency calls, automatic fax messages and services for short messages

The bearer services are provided on the card and enable to use the telecommunication services These are subdivided according to protocols which are used for data transmission An example therefor is the circuit switched data transfer

The known adapter according to EP-A-0 655 873 is provided with a buffer for storing data, originating from the mobile telephone, respectively the data terminal Means are further provided for feeding the buffer from the adapter so that the mobile telephone battery is saved as much as possible

A drawback of the adapter according to EP-A-0 655 873 is that the adapter must be provided with the required hardware interfaces and have sufficient processing capacity available for enabling data transmission For this required processing capacity, a number controllers are available on the market, such as i a MC68302 from Motorola ® These controllers are relatively powerful and therefore also relatively expensive to buy With less powerful controllers, which i a have less processing capacity available, data transmission is hitherto very difficult to realise

An object of the invention is to realise an adapter, which enables to perform data transmission with less powerful processing capacity without reducing the transmission quality According to the invention, the adapter is characterised in that the adapter comprises an interface which is provided, on the one hand, for receiving data characters from the card independently from said clock signals and for differentiating synch characters and data characters from each other and for transmitting each of the data characters in an assigned time slot to the telephone, and which interface is provided, on the other hand, for providing a predetermined number of clock signals to the card, under control of a synchronisation signal

The invention will now be described in detail referring to the annexed figures, wherein Figure 1 illustrates the configuration of hardware and software in a telephone and an adapter,

Figure 2 illustrates the state of the art, Figure 3 illustrates a block diagram of the interface according to the invention with the telephone and the card, Figure 4 shows a time diagram for communication between telephone and card,

Figures 5 and 6 show time diagrams for communication between card and telephone, Figures 7 and 8 show time diagrams for synchronisation and bus enabling,

Figure 9 is a flowchart for starting up, Figure 10 is a detailed view of the interface signals, Figure 11 is a detailed view of the interface circuit In the adapter according to the invention, use is made of a serial bus, connecting two processors with each other This bus is a fast synchronous link with bit rates up to 500 000 bits per second

In order to achieve this, there has to be assumed that both processors are equipped with the required hardware interfaces and processing capacity This is not always evident

In order to solve this problem, use is not only made of an active bus, but also of a converter the buffer from Figure 2 is replaced by an intelligent interface This can be an ordinary processor or a programmable logic from the type PAL ("Programmable Array Logic"), GAL or EPLD ("Erasable and Programmable Logic Device")

The interface provides not only the electrical separation of the two processors, but will also take care that the second processor (the processor in the card or adapter) can run off synchronisation and will only receive relevant data, without synch characters Electrical separation means that current does not run directly from the telephone to the card and vice versa The card is provided with an asynchronous UART delivering asynchronous pulses to the bus In the interface, means are provided for translating these asynchronous pulses in synchronous, in order to provide synchronous pulses to the telephone and vice versa Operation of the interface :

The operation of this adapter is independent from the data and can therefore be used both for data and for control messages The bits run contiguously from the telephone to the adapter The processor from the adapter checks by counting the number of bits if the bits are data bits or synch bits

Since not all the processors are provided with a synchronous serial port, the signals from Figure 1 are processed in the following way Receive data (RxD), i e from the telephone to the card

(Figure 4) from the entire train of clock pulses (HCIk), only the 8 flanks (PRCIk), wherein data characters (HDATA-Tx) are effectively present on the RxD line, are selected In this way, the PRCLK can be used as interrupt for bits to be received (HDATA-Tx) The UART in the card is only active under control of PRCIk

Transmit data (TxD), i e from the card to the telephone (Figure 5) the data (PDATA-Tx) is first buffered in a latch from the interface and is only transmitted to the telephone (HDATA-Rx) in the assigned time slot if HCIk and Hsync are active In this way, it is not necessary having the processor executing this time critical task The data characters are thus sent independently from Hclk Care has only to be taken that the data characters are sent between two successive Hsync pulses

Clock (Clk) signal is converted to a digital compatible level, for example TTL

Sync signal is not transmitted in a time critical manner any more Description of the block diagram (Figure 3) :

• buffer and signal shape part all signals from and to the telephone are buffered, (see above) in order to make them free from disturbances and also for adapting the levels (CMOS, TTL, 3 3 V, ) to the levels from the used processor in the data adapter card The clock signal HCIk is moreover amplified (sinus to block) in order to obtain precise flanks For this purpose, part A from the circuit shown in Figure 1 1 is used In this way, the operation of the interface is rendered less noise and high frequency sensible For this purpose, a resistance R4 is i a used between the output I/08 and the input CLK 1 /12 (Figure 10) The resistance suppresses under- and overshoot with high speed signals

• clock counter 7 or 8 pulses (Figure 7) the clock is controlled in a continuous stream of pulses

Since an ordinary UART, i e an UART which is not bit synchronously, can work byte asynchronously, such as in the Rockwell ® L1300 series, cannot work with a synchronisation signal only the usable clock pulses (i e the clock pulses for which data is available on the RxD line) are transmitted In the case of 8 bits per character, there are 8 clock pulses

If use is made of a Rockwell ® processor type L1300, and this is particular for the invention, then, for the first character to be received after a hardware reset, only 7 clock pulses may be transmitted For this purpose, use is made of a 7 or 8 counter The set up is performed with one of the control lines (Cntrl) Figure 7 mentions also the first series of PRCLK 7 pulses and the second 8 pulses This is realised by sending on PIDLE a toggle signal and by switching PCLR from high to low The toggle is taken over by PRCLK and the transition of PCLR makes PRCLK high The successive HSYNC enables the first series on PRCLK to pass • TxD enable latch

Data comes from the telephone to the data adapter This information is buffered, brought to a digital level, and sent via a switch (part B in Figure 1 1 ) to the adapter This switch switches only the data upon duration of the character, then the RxD line is kept high or low, depending on the way of programming The pulses PRCLK enable that the buffered data HDATA-Tx is transferred to the card (PDATA-Rx) Possibly present interference signals on HDATA-Tx, which are received by the telephone, will also not be transmitted (PDATA-RX) to the card

• RxD data latch and synchroniser

Data comes from the data adapter to the telephone (Figure 5) Since the processor in the data adapter has not always the required processing capacity or the specific hardware available, the data stream to the telephone in this unit and this is specific for this invention, is stored in the interface and only transmitted upon request of the telephone, thus within the assigned time slot, i e with the exact clock pulses and directly after the sync signal (HSync) The processor can then store between two sync pulses, with a lower tempo, the subsequent character in the interface The processor must however take care of that between two pulses, data characters are effectively transmitted

• reset control & timing verification (Figure 7)

This unit takes care of that timing occurs synchronously with the telephone, after turning on the first clock train consists of 7 pulses, the wake-up procedure from the telephone is initiated and difference is made between sync characters and data characters

The wake-up from the handset occurs by clamping the TxD line to a high level (PCLR) Since the UART in the Rockwell ® processor cannot send data without the presence of any clock pulses, this must be solved here by adding an additional control line

Wake-up procedure (Fig 7 and 8) PCLR reset reset signal for interface

HSYNC sync signal signal from the telephone

HCLK clock signal buffered and amplified clock signal from the telephone which becomes active only after PSTART and the subsequent

HSYNC pules become low HDATA-TX transmit line from the telephone

PRCLK clock, 7 or 8 pulses, to the data interface

PSYNC sync signal buffered from the telephone to the data interface

PDATA-RX transmit line to the data interface This diagram shows clearly how the clock pulses are transmitted in a filtered manner to the data adapter The received data on PDATA-RX is the buffered data, only released during PCLK, to the data adapter

Figure 5 sync characters from the card to the telephone

PIDLE I/O line data adapter indicates that sync characters must be sent to the telephone

PTCLK clock, inverse value from HCLK, used for time controlling data transmission to buffer PDATA-TX data from data adapter to buffer

HDATA-RX data from buffer to telephone according to timing requested by the telephone bus

If the IDLE line is kept low then the data (HDATA-RX) is also low during the SYNC pulses This is a possibility for the data adapter for generating a sync character Figure 6 data characters from the card to the telephone PIDLE I/O line data adapter indicates that sync characters must be sent to the telephone PTCLK clock, inverse value from HCLK, used for time controlling data transmission to buffer PDATA-TX data from data adapter to buffer

HDATA-RX data from buffer to telephone, according to timing requested by the telephone bus If the IDLE line is kept high, then the data (HDATA-RX) is also high during the SYNC pulses The characters now transmitted are considered as real data characters

After starting up the data adapter, PCLR is active high (Figure 7) The data adapter switches the PIDLE line high and low, and in this way also PRCLK until the data adapter is in synchronisation with the bus

PCLR is then switched low, and after a SYNC pulse, the continuous operation of the buffer starts 7 or 8 clock pulses are transmitted to the data adapter

Figure 8 wake-up handset PSTART I/O line from the data adapter, in this way HDATA-RX becomes high, without requiring clock pulses for this purpose

Since use is made of a synchronous EPLD (buffer) no output can be modified from level without clock pulses PIDLE, PCLR and PSTART can obviate this If the handset is connected it will send clock and sync pulses

In Figure 9, this wake-up procedure is clarified by means of a flowchart First of all, PIDLE and PCLR are low (20) since the telephone is not active On PSTART, a pulse is now generated (21 ) by means of which a timer is started A HSYNC must now be supplied by the telephone which starts HCLK which is monitored (22,23) If a clock pulse is not received within the set-up time (24), then it is established (26) that the telephone is not turned on If a clock pulse is received (23 Y), then it is established (25) that the telephone is turned on and the transmission is enabled

Claims

1 . An adapter for data transmission between a mobile telephone and a data terminal, which adapter comprises a card and a cable, which card is provided to be connected to the data terminal, which cable is provided to be connected, on the one hand, to the mobile telephone and, on the other hand, to the card and wherein the telephone is provided with a generator for generating clock and synchronisation signals, characterised in that the adapter comprises an interface which is provided, on the one hand, for receiving data characters from the card independently from said clock signals and for differentiating synch characters and data characters from each other and for transmitting each of the data characters in an assigned time slot to the telephone, and which interface is provided, on the other hand, for providing a predetermined number of clock signals to the card, under control of a synchronisation signal.

2. The adapter according to claim 1 , characterised in that it comprises a serial bus

3 The adapter according to claim 1 or 2, characterised in that said interface is provided for electrically separating said card from said telephone

4 The adapter according to any one of the preceding claims, characterised in that said interface is provided for amplifying said clock signals