WO1997037309A1 - Mass storage devices utilizing high speed serial communications - Google Patents

Mass storage devices utilizing high speed serial communications Download PDF

Info

Publication number
WO1997037309A1
WO1997037309A1 PCT/US1997/004995 US9704995W WO9737309A1 WO 1997037309 A1 WO1997037309 A1 WO 1997037309A1 US 9704995 W US9704995 W US 9704995W WO 9737309 A1 WO9737309 A1 WO 9737309A1
Authority
WO
WIPO (PCT)
Prior art keywords
mass storage
storage device
digital signals
computer
digital signal
Prior art date
Application number
PCT/US1997/004995
Other languages
French (fr)
Inventor
Eric C. Hannah
Richard L. Coulson
Jerrold V. Hauck
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of WO1997037309A1 publication Critical patent/WO1997037309A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • This invention relates to the field of mass storage devices for computer systems
  • Mass storage devices such as hard disks, CD-ROMS, CD-Rs (Compact Disc - Recordable), tape dnves etc. are capable of storing significant amounts of digital signals, e g , well into the Gigabyte range
  • a conventional mass storage device such as mass storage device
  • storage medium 11 such as a magnetic platter or tape for storing digital signals as magnetic fields, or a medium which may be pitted for storing digital signals as a series of pitted and unpitted regions in a flat surface for reading by a laser
  • Buffer 12 is provided for temporary, interim storage of digital signals being written to or read from storage medium 11
  • an application on computer 20, havmg microprocessor 22 and main memory 24 might invoke transmission of digital signals over bus 15 to mass storage device 10 for storage on storage medium 11
  • bus 15 likely has latency and bandwidth limitations that prevent substantially immediate transmission of all digital signals destined for a particular sector or area on storage medium 11
  • the digital signals are temporarily stored and reassembled in buffer 12 as they are received by mass storage device 10
  • this method is efficient in that it avoids a need to intermittently write digital signals to a same sector or area as they are intermittently received by mass storage device 10, it requires relatively expensive hardware, such as buffer 12 and processor 13.
  • Bus 15 Signals delayed by the bandwidth and latency limitations of bus 15 can be written to storage medium 11 as they are received, but this requires many time-wasting revolutions of a disk or platter or positioning of a tape to continuously bring the desired sector or area into a position to be written to as the signals are intermittently received.
  • An application on computer 20 also might request that signals on storage medium 11 be read and transmitted over bus 15. Instructions typically are provided to mass storage device 10 to acquire digital signals stored on storage medium 11 and to transmit the signals over bus
  • bus 15 to computer 20. Because of the typically high latency of bus 15, digital signals from storage medium 11 are often read and ready for transmission to computer 20 before bus 15 has been acquired. Therefore the signals are temporarily stored in buffer 12 until bus 15 is acquired. This is inefficient with respect to time and hardware requirements. Even if bus 15 is timely acquired, bandwidth limitations of bus 15 often prevent real ⁇ time transmission of the digital signals to computer 20. In such cases bus 15 becomes a bottleneck at which digital signals back-up. Backed-up signals typically are stored in buffer
  • Processor 13 controls the interim storage of the digital signals in buffer 12.
  • processor 13 preferably also can processes digital signals being written to or read from storage medium 11.
  • processor 13 can compress signals being written to storage medium 11 and decompress signals being read from storage medium 11.
  • Processor 13 also can perform error correction to correct signals corrupted during transmission between computer 20 and mass storage device 10 and coding correction to ensure that signals being written to storage medium 11 are formatted correctly for compatibility with storage medium 11.
  • a mass storage device having a storage medium on which digital signals can be stored.
  • the mass storage device is coupleable to a computer through a high-speed serial bus.
  • the high-speed serial bus has a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer without interim storage of the digital signals in a buffer inside the mass storage device.
  • Fig. 1 is a block diagram of a conventional mass storage device coupled to a computer using a conventional bus
  • Fig. 2 is a block diagram of the mass storage device of the invention coupled to a computer using a high-speed serial bus.
  • a substantial cost reduction in mass storage devices is possible through the use of a new high-speed serial bus which provides low latency and high bandwidth.
  • a bus of this type is disclosed in U.S. Provisional Applications Nos. 60/006,431, filed on November 10, 1995; 60/011 ,320, filed on February 8, 1996; and (to be provided), filed on March 8, 1996 as attorney docket no. 366431-122P3, the teachings of all three being inco ⁇ orated herein by reference.
  • Mass storage device 30 includes storage medium 31 , as is known in the art.
  • Storage medium 31 can be a magnetic disk, platter or tape for storing digital signals as magnetic fields, or a medium which may be pitted for reading by a laser, such as in the case of CD- ROMs and CD-Rs, as discussed above with reference to storage medium 11 of conventional mass storage device 10 of Fig. 1.
  • mass storage device 30 is constructed without an embedded processor for digital signal processing or on-board buffer memory, such as processor 13 and buffer 12, which are part of conventional mass storage device 10 of Fig. 1.
  • Bus 25 is a high-speed, full duplex, serial bus having guaranteed very low latency. Bus 25 has a bandwidth (transmission speed) of around 800 Mbps.
  • Bus 25 further has an ability to directly access memory 24 of computer 20 to help ensure substantially immediate access by mass storage device 30 to host memory 24 and digital signals stored on host memory 24.
  • bus 25 enable substantially real-time transfer of signals from host memory 24 of computer 20 to mass storage device 30. Entire packets of signals which are to be written onto a same sector or area of storage medium 31 can be transmitted together as a unit in real time. Buffers are not needed in mass storage device 30 for temporary interim storage of digital signals from computer 20, such as to reassemble packets of digital signals destined for storage on a same sector or area of storage medium 31.
  • bus 25 The high bandwidth and guaranteed low latency of bus 25 combine to enable real-time transmission of signals which have been read from storage medium 31 of mass storage device
  • the low latency, high bandwidth and DMA capabilities of high-speed serial bus 25 further enable real-time processing by microprocessor 22 of computer 20 of the digital signals being transmitted between mass storage device 30 and computer 20.
  • This feature eliminates a need for an on-board, embedded processor for digital signal processing in mass storage device 30, as was known in conventional mass storage devices, such as processor 13 in mass storage device 10 of Fig. 1.
  • high ⁇ speed bus 25 enables real-time signal transmission between mass storage device 30 and computer 20
  • digital signals may be processed by microprocessor 22 of computer 20 as if it were a closely-coupled processor on-board mass storage device 30. Therefore, digital signals being written to storage medium 31 can be processed by microprocessor 22 of computer 30 first and transmitted over bus 25 in real-time for storage on storage medium 31. Similarly, digital signals being read from storage medium 31 of mass storage device 30 can be sent in real-time over guaranteed low latency, high-bandwidth bus 25 for real-time processing by microprocessor 22 of computer 20.
  • Microprocessor 22 can perform all of the processing chores previously accomplished by an on-board processor, such as processor 13 of conventional mass storage device 10, including digital signal compression and decompression, digital signal transforming, error correction and coding correction. Whereas processor 13 of conventional mass storage device
  • microprocessor 22 can be a modern, fast, relatively sophisticated processor which can execute various, diverse and complex software routines loaded into memory 24 for processing of the digital signals being written to or read from storage medium 31.
  • microprocessors and digital signal processing routine technology continues to advance, so will the quantity and quality of processing which can be performed on digital signals being transmitted between computer 20 and mass storage device 30.
  • Mass storage device 30 represents a significant improvement over conventional mass storage technology. Substantial cost savings can be realized by the elimination of on-board hardware, such as control processors and buffers. Furthermore, signal processing improvements no longer are dependent on expensive improvements or upgrades of hardware and software in a mass storage device but essentially are wholly reliant on improvements to, for example, microprocessor 22 in computer 20 and software running on microprocessor 22. Significantly, computer processor technology continues to rapidly advance, and as it does, so will improvements to the quality and flexibility of processing which may be performed on the digital signals being read from or written to storage medium 31 of mass storage device 30. It should be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as expressed in the following claims.

Abstract

A mass storage device (30) having a storage medium (31) on which digital signals can be stored. The mass storage device (30) is coupleable to a computer (20) through a high-speed serial bus (25). The high-speed serial bus has a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer without interim storage (12 and 13) of the digital signals in a buffer (13) inside the mass storage device (10). The computer has a processor (22) capable of processing the digital signals and the digital signals may be transmitted between the mass storage device and the computer without processing of the digital signals by a processor (13) in the mass storage device.

Description

MASS STORAGE DEVICES UTILIZING HIGH SPEED SERIAL COMMUNICATIONS
CROSS-REFERENCES TO RELATED APPLICATIONS
This non-provisional U S national application, filed under 35 U S C §111(a) claims, under 35 U S C §119(e)(1), the benefit of the filing date of provisional U S applications nos 60/006,431. filed under 35 U S C §111(b) on November 10. 1995. 60/011 ,320, filed under 35 U S C §11 Kb) on February 8, 1996. and (to be provided), filed under 35 U S C §111(b) on March 8. 1996 as attorney docket no 366431-122P3, the teachings of all three being incorporated herein by reference
BACKGROUND OF THE INVENTION
1 Field of the Invention This invention relates to the field of mass storage devices for computer systems
2 Description of the Related Art
Mass storage devices, such as hard disks, CD-ROMS, CD-Rs (Compact Disc - Recordable), tape dnves etc. are capable of storing significant amounts of digital signals, e g , well into the Gigabyte range A conventional mass storage device, such as mass storage device
10 shown in Fig 1 , typically includes storage medium 11 , such as a magnetic platter or tape for storing digital signals as magnetic fields, or a medium which may be pitted for storing digital signals as a series of pitted and unpitted regions in a flat surface for reading by a laser
Buffer 12 is provided for temporary, interim storage of digital signals being written to or read from storage medium 11 For example, an application on computer 20, havmg microprocessor 22 and main memory 24 might invoke transmission of digital signals over bus 15 to mass storage device 10 for storage on storage medium 11 Because bus 15 likely has latency and bandwidth limitations that prevent substantially immediate transmission of all digital signals destined for a particular sector or area on storage medium 11 , the digital signals are temporarily stored and reassembled in buffer 12 as they are received by mass storage device 10 After buffer 12 accumulates a complete group of digital signals, they are written to the designated sector or area Buffer 12 of mass storage device 10 accepts and temporarily holds the signals until all signals to be stored in a particular sector or area have been received by mass storage device 10 Although this method is efficient in that it avoids a need to intermittently write digital signals to a same sector or area as they are intermittently received by mass storage device 10, it requires relatively expensive hardware, such as buffer 12 and processor 13.
Signals delayed by the bandwidth and latency limitations of bus 15 can be written to storage medium 11 as they are received, but this requires many time-wasting revolutions of a disk or platter or positioning of a tape to continuously bring the desired sector or area into a position to be written to as the signals are intermittently received.
An application on computer 20 also might request that signals on storage medium 11 be read and transmitted over bus 15. Instructions typically are provided to mass storage device 10 to acquire digital signals stored on storage medium 11 and to transmit the signals over bus
15 to computer 20. Because of the typically high latency of bus 15, digital signals from storage medium 11 are often read and ready for transmission to computer 20 before bus 15 has been acquired. Therefore the signals are temporarily stored in buffer 12 until bus 15 is acquired. This is inefficient with respect to time and hardware requirements. Even if bus 15 is timely acquired, bandwidth limitations of bus 15 often prevent real¬ time transmission of the digital signals to computer 20. In such cases bus 15 becomes a bottleneck at which digital signals back-up. Backed-up signals typically are stored in buffer
12 of mass storage device 10 and transmitted over time as allowed by the bandwidth constraints of bus 15. The continuing growth of the rate at which digital signals can be written to and read from storage media exacerbates the bottlenecking problem caused by conventional bus 15.
Processor 13 controls the interim storage of the digital signals in buffer 12. Processor
13 preferably also can processes digital signals being written to or read from storage medium 11. For example processor 13 can compress signals being written to storage medium 11 and decompress signals being read from storage medium 11. Processor 13 also can perform error correction to correct signals corrupted during transmission between computer 20 and mass storage device 10 and coding correction to ensure that signals being written to storage medium 11 are formatted correctly for compatibility with storage medium 11. SUMMARY OF THE INVENTION
A mass storage device having a storage medium on which digital signals can be stored.
The mass storage device is coupleable to a computer through a high-speed serial bus. The high-speed serial bus has a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer without interim storage of the digital signals in a buffer inside the mass storage device.
BRIEF DESCRIPTION OF THE DRAWINGS
The following detailed description will be more fully understood with reference to the accompanying drawings in which:
Fig. 1 is a block diagram of a conventional mass storage device coupled to a computer using a conventional bus; and Fig. 2 is a block diagram of the mass storage device of the invention coupled to a computer using a high-speed serial bus.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Fig. 2, a substantial cost reduction in mass storage devices is possible through the use of a new high-speed serial bus which provides low latency and high bandwidth. A bus of this type is disclosed in U.S. Provisional Applications Nos. 60/006,431, filed on November 10, 1995; 60/011 ,320, filed on February 8, 1996; and (to be provided), filed on March 8, 1996 as attorney docket no. 366431-122P3, the teachings of all three being incoφorated herein by reference.
Mass storage device 30 includes storage medium 31 , as is known in the art. Storage medium 31 , can be a magnetic disk, platter or tape for storing digital signals as magnetic fields, or a medium which may be pitted for reading by a laser, such as in the case of CD- ROMs and CD-Rs, as discussed above with reference to storage medium 11 of conventional mass storage device 10 of Fig. 1. However, mass storage device 30 is constructed without an embedded processor for digital signal processing or on-board buffer memory, such as processor 13 and buffer 12, which are part of conventional mass storage device 10 of Fig. 1. Bus 25 is a high-speed, full duplex, serial bus having guaranteed very low latency. Bus 25 has a bandwidth (transmission speed) of around 800 Mbps. This is fast enough to send digital signals between mass storage device 30 and computer 20 at a rate sufficient for high performance input/ output (I/O). Bus 25 further has an ability to directly access memory 24 of computer 20 to help ensure substantially immediate access by mass storage device 30 to host memory 24 and digital signals stored on host memory 24.
The high bandwidth, guaranteed low latency and, in certain instances, the direct memory accessing (DMA) capabilities of bus 25 enable substantially real-time transfer of signals from host memory 24 of computer 20 to mass storage device 30. Entire packets of signals which are to be written onto a same sector or area of storage medium 31 can be transmitted together as a unit in real time. Buffers are not needed in mass storage device 30 for temporary interim storage of digital signals from computer 20, such as to reassemble packets of digital signals destined for storage on a same sector or area of storage medium 31.
The high bandwidth and guaranteed low latency of bus 25 combine to enable real-time transmission of signals which have been read from storage medium 31 of mass storage device
30 to computer 20. This is true even though modern mass storage devices tend to deliver vast amounts of digital signals to a bus in a very short time for transmission to a computer. For example, once the designated sector or area of storage media which is to be read is mechanically located, large amounts of digital signals are read and are ready for transmission. The very low latency of bus 25 allows mass storage device 30 to quickly acquire a signal transmission path for signals to be transmitted to computer 20. The high bandwidth (800 Mbps) allows for a large quantity of digital signals to be sent in a very short time over the bus, thereby preventing any signal bottlenecks and back-ups in mass storage device 30. The DMA capabilities ensure there are no delays in storing the signals into memory 24. The high bandwidth and low latency, especially, eliminate a need for an on-board buffer for interim storage of the digital signals, since the digital signals may be sent to computer 20 essentially as they are read from storage medium 31 of mass storage device 30.
The low latency, high bandwidth and DMA capabilities of high-speed serial bus 25 further enable real-time processing by microprocessor 22 of computer 20 of the digital signals being transmitted between mass storage device 30 and computer 20. This feature eliminates a need for an on-board, embedded processor for digital signal processing in mass storage device 30, as was known in conventional mass storage devices, such as processor 13 in mass storage device 10 of Fig. 1. Conventional mass storage devices, such as mass storage device 10 coupled to computer 20 through conventional bus 15, require an on-board, closely coupled processor, such as processor 13, to process the digital signals in a timely fashion. Since high¬ speed bus 25 enables real-time signal transmission between mass storage device 30 and computer 20, digital signals may be processed by microprocessor 22 of computer 20 as if it were a closely-coupled processor on-board mass storage device 30. Therefore, digital signals being written to storage medium 31 can be processed by microprocessor 22 of computer 30 first and transmitted over bus 25 in real-time for storage on storage medium 31. Similarly, digital signals being read from storage medium 31 of mass storage device 30 can be sent in real-time over guaranteed low latency, high-bandwidth bus 25 for real-time processing by microprocessor 22 of computer 20.
Microprocessor 22 can perform all of the processing chores previously accomplished by an on-board processor, such as processor 13 of conventional mass storage device 10, including digital signal compression and decompression, digital signal transforming, error correction and coding correction. Whereas processor 13 of conventional mass storage device
10 typically is relatively unsophisticated and uses a fixed algorithm to minimize costs, microprocessor 22 can be a modern, fast, relatively sophisticated processor which can execute various, diverse and complex software routines loaded into memory 24 for processing of the digital signals being written to or read from storage medium 31. As microprocessors and digital signal processing routine technology continues to advance, so will the quantity and quality of processing which can be performed on digital signals being transmitted between computer 20 and mass storage device 30.
Mass storage device 30 represents a significant improvement over conventional mass storage technology. Substantial cost savings can be realized by the elimination of on-board hardware, such as control processors and buffers. Furthermore, signal processing improvements no longer are dependent on expensive improvements or upgrades of hardware and software in a mass storage device but essentially are wholly reliant on improvements to, for example, microprocessor 22 in computer 20 and software running on microprocessor 22. Significantly, computer processor technology continues to rapidly advance, and as it does, so will improvements to the quality and flexibility of processing which may be performed on the digital signals being read from or written to storage medium 31 of mass storage device 30. It should be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as expressed in the following claims.

Claims

CLAIMSWhat we claim is:
1. A mass storage device, comprising:
(a) storage medium on which digital signals can be stored, wherein: the mass storage device is coupleable to a computer through a high-speed serial bus, the high-speed serial bus having a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer without interim storage of the digital signals in a buffer inside the mass storage device.
2. The mass storage device of claim 1, wherein the computer has a processor capable of processing the digital signals and the digital signals may be transmitted between the mass storage device and the computer without processing of the digital signals by a processor in the mass storage device.
3. The mass storage device of claim 1, wherein the high-speed serial bus has a bandwidth high enough and a latency low enough to transmit the digital signals in real time.
4. The mass storage device of claim 2, wherein the processor in the computer processes the signals in real time.
5. The mass storage device of claim 2, wherein the processor can perform at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction.
6. The mass storage device of claim 1, wherein the high-speed serial bus has a bandwidth of at least 750 Megabits per second.
7. The mass storage device of claim 2, wherein the high-speed serial bus has a bandwidth high enough and a latency low enough to transmit the digital signals in real time and the processor in the computer can perform at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction in real time.
8. The mass storage device of claim 1 , wherein the mass storage device is one of a hard disk, CD-ROM, CD-R and tape drive.
9. The mass storage device of claim 1, wherein the high-speed serial bus has direct memory accessing capability .
10. A mass storage device, comprising:
(a) means for storing digital signals, wherein: the mass storage device is coupleable to a computer means through a means for high¬ speed serial digital signal transmission, the means for high-speed serial digital signal transmission having a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer means without interim storage of the digital signals in buffer means inside the mass storage device.
11. The mass storage device of claim 10, wherein the computer means has a means for processing capable of processing the digital signals and the digital signals may be transmitted between the mass storage device and the computer means without processing of the digital signals by processing means in the mass storage device.
12. The mass storage device of claim 10, wherein the means for high-speed serial digital signal transmission has a bandwidth high enough and a latency low enough to transmit the digital signals in real time.
13. The mass storage device of claim 11 , wherein the means for processing in the computer means processes the signals in real time.
14. The mass storage device of claim 11 , wherein the means for processing in the computer means can perform at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction.
15. The mass storage device of claim 10, wherein the means for high-speed serial signal transmission has a bandwidth of at least 750 Megabits per second.
16. The mass storage device of claim 11, wherein the means for high-speed serial signal transmission has a bandwidth high enough and a latency low enough to transmit the digital signals in real time and the means for processing in the computer means can perform at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction in real time.
17. The mass storage device of claim 10, wherein the mass storage device is one of a hard disk. CD-ROM, CD-R and tape drive.
18. The mass storage device of claim 10, wherein the means for high-speed digital signal transmission has a direct memory accessing capability.
19. A method for transmitting digital signals between a computer and a mass storage device, comprising the steps of:
(a) at least one of reading digital signals from and writing digital signals to a storage medium of the mass storage device; and (b) transmitting the digital signals over a high-speed serial bus between the computer and the mass storage device without prior local interim storage of the digital image signals in a buffer in the mass storage device.
20. The method of claim 19, wherein the computer has a processor capable of processing the signals and step (b) further comprises the step of transmitting the digital signals between the mass storage device and the computer without processing of the digital signals by a processor in the mass storage device.
21. The method of claim 19, wherein the high-speed serial bus has a bandwidth high enough and a latency low enough to transmit the digital signals in real time, and step (b) comprises the step of transmitting the signals in real time.
22. The method of claim 20, further comprising the step of processing the signals in real¬ time by the processor in the computer.
23. The method of claim 22 , wherein the processing comprises at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction.
24. The method of claim 19, wherein the high-speed serial bus has a bandwidth of at least 750 Megabits per second.
25. The method of claim 20, wherein the high-speed serial bus has a bandwidth high enough and a latency low enough to transmit the digital signals in real time, and step (b) comprises the step of transmitting the digital signals in real time, further comprising the step of at least one of digital signal compression, digital signal decompression, digital signal transforming, error correction and coding correction in real time by the processor in the computer.
26. The method of claim 19, wherein the mass storage device is one of a hard disk, CD- ROM, CD-R and tape drive.
27. The mass storage device of claim 19, wherein the high-speed serial bus has direct memory accessing capability .
PCT/US1997/004995 1996-03-29 1997-03-27 Mass storage devices utilizing high speed serial communications WO1997037309A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/623,759 US5809337A (en) 1996-03-29 1996-03-29 Mass storage devices utilizing high speed serial communications
US08/623,759 1996-03-29

Publications (1)

Publication Number Publication Date
WO1997037309A1 true WO1997037309A1 (en) 1997-10-09

Family

ID=24499306

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/004995 WO1997037309A1 (en) 1996-03-29 1997-03-27 Mass storage devices utilizing high speed serial communications

Country Status (2)

Country Link
US (1) US5809337A (en)
WO (1) WO1997037309A1 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064497A (en) * 1996-03-08 2000-05-16 Intel Corporation Low cost digital scanners
US6098146A (en) 1997-04-11 2000-08-01 Dell Usa, L. P. Intelligent backplane for collecting and reporting information in an SSA system
US5931958A (en) * 1997-04-11 1999-08-03 Dell Usa, L.P. Processor controlled link resiliency circuit for serial storage architectures
US6216182B1 (en) * 1998-07-30 2001-04-10 Fore Systems, Inc. Method and apparatus for serving data with adaptable interrupts
KR100342977B1 (en) * 1998-09-28 2002-09-18 주식회사 하이닉스반도체 Control circuit of address in a semiconductor memory device
US6624761B2 (en) 1998-12-11 2003-09-23 Realtime Data, Llc Content independent data compression method and system
US6546489B1 (en) 1999-03-04 2003-04-08 Western Digital Ventures, Inc. Disk drive which provides a secure boot of a host computer system from a protected area of a disk
US6604158B1 (en) 1999-03-11 2003-08-05 Realtime Data, Llc System and methods for accelerated data storage and retrieval
US6601104B1 (en) 1999-03-11 2003-07-29 Realtime Data Llc System and methods for accelerated data storage and retrieval
US6499083B1 (en) 1999-09-15 2002-12-24 Western Digital Ventures, Inc. Disk-based storage system responsive to a direction-selection signal for autonomously controlling seeks in a sequence determined by the direction-selection signal and a locally-stored doubly linked list
US20010047473A1 (en) 2000-02-03 2001-11-29 Realtime Data, Llc Systems and methods for computer initialization
US7417568B2 (en) 2000-10-03 2008-08-26 Realtime Data Llc System and method for data feed acceleration and encryption
US8692695B2 (en) 2000-10-03 2014-04-08 Realtime Data, Llc Methods for encoding and decoding data
US9143546B2 (en) 2000-10-03 2015-09-22 Realtime Data Llc System and method for data feed acceleration and encryption
US7386046B2 (en) 2001-02-13 2008-06-10 Realtime Data Llc Bandwidth sensitive data compression and decompression
US7275135B2 (en) * 2001-08-31 2007-09-25 Intel Corporation Hardware updated metadata for non-volatile mass storage cache
US20030074524A1 (en) * 2001-10-16 2003-04-17 Intel Corporation Mass storage caching processes for power reduction
US6898655B1 (en) 2001-11-16 2005-05-24 Marvell International Ltd. Multiport high speed communications integrated circuit
US7308521B1 (en) 2001-11-16 2007-12-11 Marvell International Ltd. Multi-port communications integrated circuit and method for facilitating communication between a central processing chipset and multiple communication ports
JP2005063351A (en) * 2003-08-20 2005-03-10 Matsushita Electric Ind Co Ltd Device and method for transferring data
US8676876B2 (en) * 2006-06-27 2014-03-18 International Business Machines Corporation Synchronizing an active feed adapter and a backup feed adapter in a high speed, low latency data communications environment
US8296778B2 (en) * 2006-06-27 2012-10-23 International Business Machines Corporation Computer data communications in a high speed, low latency data communications environment
US8122144B2 (en) * 2006-06-27 2012-02-21 International Business Machines Corporation Reliable messaging using redundant message streams in a high speed, low latency data communications environment
US8695015B2 (en) * 2006-12-06 2014-04-08 International Business Machines Corporation Application message conversion using a feed adapter
US8850451B2 (en) * 2006-12-12 2014-09-30 International Business Machines Corporation Subscribing for application messages in a multicast messaging environment
US8327381B2 (en) 2006-12-12 2012-12-04 International Business Machines Corporation Referencing message elements in an application message in a messaging environment
KR101317528B1 (en) * 2007-01-10 2013-10-15 엘지전자 주식회사 Image signal processing apparatus to which a plurality of module devices are connected and controlling method thereof
US7917912B2 (en) * 2007-03-27 2011-03-29 International Business Machines Corporation Filtering application messages in a high speed, low latency data communications environment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124888A (en) * 1975-12-24 1978-11-07 Computer Automation, Inc. Peripheral-unit controller apparatus
US5450548A (en) * 1991-03-07 1995-09-12 Fujitsu Limited Apparatus for performing data transfer synchronously or asynchronously between device channels
US5568192A (en) * 1995-08-30 1996-10-22 Intel Corporation Method and apparatus for processing digital video camera signals

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344132A (en) * 1979-12-14 1982-08-10 International Business Machines Corporation Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus
US5359713A (en) * 1989-06-01 1994-10-25 Legato Systems, Inc. Method and apparatus for enhancing synchronous I/O in a computer system with a non-volatile memory and using an acceleration device driver in a computer operating system
KR950010770B1 (en) * 1993-11-29 1995-09-22 대우전자주식회사 Error detect & correction method of wide data transmition
US5563961A (en) * 1994-03-03 1996-10-08 Radius Inc. Video data compression method and system which measures compressed data storage time to optimize compression rate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124888A (en) * 1975-12-24 1978-11-07 Computer Automation, Inc. Peripheral-unit controller apparatus
US5450548A (en) * 1991-03-07 1995-09-12 Fujitsu Limited Apparatus for performing data transfer synchronously or asynchronously between device channels
US5568192A (en) * 1995-08-30 1996-10-22 Intel Corporation Method and apparatus for processing digital video camera signals

Also Published As

Publication number Publication date
US5809337A (en) 1998-09-15

Similar Documents

Publication Publication Date Title
US5809337A (en) Mass storage devices utilizing high speed serial communications
US6883079B1 (en) Method and apparatus for using data compression as a means of increasing buffer bandwidth
US6381659B2 (en) Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses
US5652917A (en) System for transmitting and receiving combination of compressed digital information and embedded strobe bit between computer and external device through parallel printer port of computer
US4949245A (en) Intermediate memory system for connecting microcomputers to a rotating disk memory
US6964008B1 (en) Data checksum method and apparatus
EP1068734B1 (en) Method and apparatus for controlling data flow between devices connected by a memory
US7146494B2 (en) High speed data transfer between mainframe storage systems
KR100324154B1 (en) Compression and data processing chips for storage subsystems providing superior data integrity and methods
US5944802A (en) Dynamic speed matching of host channel and device data transfers
US6044431A (en) Data buffer using dummy data
US4903195A (en) Method for controlling data transfer
US5459838A (en) I/O access method for using flags to selectively control data operation between control unit and I/O channel to allow them proceed independently and concurrently
US6101575A (en) Tape drive data buffering
US6430652B1 (en) Method and apparatus for streaming data in a data processing system
US7353298B2 (en) Data transfer processing method
EP3826015B1 (en) Method for writing in a volatile memory and corresponding integrated circuit
US6205141B1 (en) Method and system for un-tagged command queuing
US6233628B1 (en) System and method for transferring data using separate pipes for command and data
EP0974910A2 (en) Apparatus and method for storing retrievable boundary information into a buffer memory of a receiving device
US6961801B1 (en) Method and apparatus for accessing video data in memory across flow-controlled interconnects
US6854037B2 (en) Recording/reproduction apparatus and recording/reproduction control method
US20050128624A1 (en) System for improving performance writing streaming tapes
US6535935B1 (en) Method of sending data streams using a refetchable first-in-first-out memory which is read in a sequence that backs-up
JPH1091575A (en) Digital video storage server and its data transfer method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: CA

NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97535417

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase