WO1996037841A1

WO1996037841A1 - Dram controller that reduces the time required to process memory requests

Info

Publication number: WO1996037841A1
Application number: PCT/US1996/005411
Authority: WO
Inventors: David Weinman
Original assignee: National Semiconductor Corporation
Priority date: 1995-05-26
Filing date: 1996-04-16
Publication date: 1996-11-28

Abstract

The time required to retrieve information from a dynamic random-access-memory (DRAM) is reduced by utilizing a DRAM controller that independently controls multiple address ranges at the same time, and determines whether a memory request to one of the address ranges is to the same page of memory as the last memory request to that same address range.

Description

DRAM CONTROLLER

THAT REDUCES THE ΗME REQUIRED

TO PROCESS MEMORY REQUESTS

BACKGROUND OF THE INVENTION 1. Field of the Invention.

The present invention relates to a dynamic random-access-memory (DRAM) controller and, more particularly, to a DRAM controller that reduces the time required to process memory requests.

2. Description of the Related Art.

A dynamic random-access-memory (DRAM) controller is a microprocessor peripheral device that controls memory requests to the DRAMs associated with the processor to insure that the DRAMs are periodically refreshed. Between each refresh cycle, the DRAM controller processes each memory request by first determining whether the address associated with the request is to the same page of memory as the last request.

When the memory request is to a different page of memory, the row address strobe must be raised and then held high for a predetermined period of time. DRAM controllers typically consume one-half of a clock period to raise the row address strobe and, once raised, hold the row address strobe at a logic high for one to one and a half clock periods.

After being held high for the predetermined period of time, the row address strobe is dropped and, after another clock period, the column address strobe is dropped. Once the column address strobe is lowered, data is typically available one-half of a clock period to one clock period later. As a result, conventional DRAMs typically require three-to-four clock cycles to process each memory request when the request is to a different page of memory.

To minimize the time consuming process of obtaining information from the DRAMs, conventional processors utilize an on-chip cache memory to store a limited amount of information. The principle advantage of a cache memory is that information can typically be read from or written to the cache in one clock cycle.

Although a cache memory can dramatically reduce the time required to read information from or write information to memory, the required time is increased when the information is not stored in the cache. As is well known, conventional processors first attempt to retrieve information from the cache memory. If the needed information is not in the cache memory, only then does the processor retrieve the information from the DRAM. As a result, each cache miss effectively increases the time required to obtain information from a DRAM to four-to-five clock cycles.

One solution to this problem is to simply increase the size of the cache memory, thereby increasing the likelihood that the needed information will be stored in the cache. The primary drawback to this solution is that a larger cache memory increases the size, cost, and complexity of the resulting circuit. Thus, there is a need for other techniques which reduce the time required to obtain information stored in a DRAM.

SUMMARY OF THE INVENTION In a conventional microprocessor-based computer system, three-to-four clock cycles are typically required to read information from or write information to a dynamic random-access-memory (DRAM) when the address associated with the request is to a different page of memory.

In the present invention, the time required to read information from or write information to a DRAM is reduced by utilizing a DRAM controller that independently controls multiple address ranges at the same time, and determines whether a memory request to an address range is to the same page of memory as the last memory request to that address range.

By independently controlling multiple address ranges at the same time, the DRAM controller increases the likelihood that the memory requests to each address range will be to the same page of memory. For example, if a page of memory in one address range stores related data, and a page of memory in another address range stores related instructions, then a series of memory requests seeking to obtain the related data or instructions will be to the same page of memory, even if the requests are alternately for data and instructions, since the data and instructions stored in the two address ranges are independently controlled.

When the memory requests are to the same page of memory, the DRAM controller can omit outputting the row address, as long as the row address strobe remains in the same logic state, thereby saving two-to-three clock cycles. Thus, in the present invention, information can be retrieved from a DRAM in one-to-two clock cycles when successive memory requests to the same address range are to the same page of memory.

A DRAM controller in accordance with the present invention includes a memory space register and a plurality of chip select circuits. The memory space register defines a plurality of address ranges for the plurality of chip select circuits so that each address range corresponds with one chip select circuit. Each chip select circuit, in turn, asserts a chip select signal when an input address falls within the corresponding address range and a first series of control signals are set to predefined logic states. The DRAM controller also includes a plurality of page hit circuits that correspond with the plurality of chip select circuits. Each page hit circuit asserts a page hit signal when the chip select signal from the corresponding chip select circuit is asserted, a second series of control signals are set to predefined logic states, and the input address is to the same page of memory within the address range as the last input address to that address range.

Control over the memory requests to the plurality of address ranges is performed by a plurality of sequencers. Each sequencer, which corresponds with one chip select circuit and one page hit circuit, sequentially sets a row address strobe and a column address strobe to predefined logic states in response to each memory request when the corresponding chip select signal is asserted, and the corresponding page hit signal is deasserted. On the other hand, when both the corresponding chip select signal and the corresponding page hit signal are asserted and the row address strobe is in the predefined logic state, each sequencer only sets the column address strobe to the predefined logic state.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS FIGs. 1A-1C is a block diagram illustrating a dynamic random access memory (DRAM) controller 100 in accordance with the present invention.

FIG. 2 is a block diagram illustrating the operation of chip select circuit 110. FIG. 3 is a block diagram illustrating page hit circuit 130 in accordance with the present invention.

FIG. 4 is a block diagram illustrating a circuit 400 for forming the page pointer signal PGP0. FIG. 5 is a block diagram illustrating page hit circuit 140 in accoidance with the present invention. FIG. 6 is a block diagram illustrating the address path for controller 100. FIG. 7 is a block diagram illustrating address multiplexer circuit 190. FIGs. 8A and 8B are a state machine illustrating the operation of sequencer 210.

FIGs. 9A-9F are timing diagrams illustrating read and write cycle timing for a three cycle and four cycle page miss memory access.

FIGs. 10A and 10B are block diagrams illustrating the data path for DRAM writes and reads, respectively.

DETAILED DESCRIPTION FIGs 1A-1C show a block diagram of a dynamic random access memory (DRAKl) controller 100 in accordance with the present invention As descπbed in greater detail below, controller 100 divides the address space controlled by controller 100 into multiple address ranges or banks of memory

The size of each bank, in turn, is preferably programmable so that each bank of memory can be configured to define one of several memory sizes, such as one-half, one, two, four, or eight Mbytes

Thus, for example, controller 100 can be configured to control 16 Mbytes of memory by configunng two banks of memory to each define eight Mbytes of memory

The address space controlled by controller 100 can be located anywhere within the total addressable memory space In the embodiment shown in FIGs 1A-1C, the address space is located within the first 128 Mbytes of memory Each bank, in turn, can be located anywhere within the first 128 Mbytes of memory space as long as the banks do not overlap In the preferred embodiment, one bank of memory always begins at address zero hexadecimal

As shown in FIGs 1A-1C, controller 100 includes a chip select circuit 110 that indicates when a valid DRAM request is directed to a first bank of memory by asserting a chip select signal SEL0 when the input address ADD falls within the address space defined by controller 100 as the first bank of memory, and a first series of control signals are set to predefined logic states

In operation, chip select circuit 110 receives an address strobe ADS that indicates whether the current input address ADD is valid, a memory/IO signal M IO that indicates whether the request is to memory or an I/O device, a data/code signal D/C that indicates whether the request is for data or code, and a read/write signal R/W that indicates whether the request is for a read or a write

When the logic state of the ADS signal indicates that the input address ADD is valid, and the logic states of the M/IO, D/C and R/W signals indicate that data is to be written to memory or that the memory is to be read, chip select circuit 110 outputs the chip select signal SEL0 when the row address bit pattern of the mput address ADD is equal to or greater than the row address bit pattern that identifies the starting address, and is equal to or less than the ending address In addition to outputting the select signal SEL0, chip select circuit 110 also asserts a pipeline signal PIP0 each time the input address ADD is to the first bank of memory

In those cases where the memory space controlled by controller 100 does not coincide with the top end of the total addressable memory space, the row address comparison can be simplified because one or more of the most significant address bits will always be zero For example, when controller 100 controls the first 128 Mbytes of address space, the 28th and greater address bits will always be zero

As a result, address bits [31 27] of a 32-bit address can be quickly checked to make an initial determination of whether the input address ADD is to the address space controlled by controller 100 FIG 2 illustrates a zero check of the five most significant address bits of a 32-bit address ^' Similarly, controller 100 also includes a chip select circuit 120 that indicates when a valid DRAM request is directed to a second bank of memory by asserting a chip select signal SEL1 when the input address ADD falls within the address space defined by controller 100 as the second bank of memory, and the first seπes of control signals are set to the predefined logic states Chip select circuit 120, which also asserts a pipeline signal PIP1, operates in the same manner as does circuit 110 The set up of the memory space controlled by controller 100, including the enable ent of the banks, the selection of the bank sizes, and the definition of the starting and ending addresses of each bank, is defined by a register block 125 that includes a seπes of control registers The registers are set by writing one or more control words to register block 125 which, in turn, outputs a seπes of control words to the internal circuitry of controller 100 The control words are written to a specific register within block 125, as defined by a register address RADD, via a register data bus RBUS when a register wπte signal WC and a chip enable signal CE are set to predefined logic states The control words can also be read from the registers, as defined by the register address RADD, via the register data bus RBUS when a register read signal RC and the chip enable signal CE are set to predefined logic states

Refemng back to FIGs 1A-1C, controller 100 also includes a first-bank page hit circuit 130 that outputs a page hit signal PHO when the chip select signal SELO indicates that the input address ADD is to the first bank of memory, a second series of control signals are set to predefined logic states, and the input address ADD is to the same page of memory in the first bank as the last memory address to the first bank.

In the preferred embodiment, controller 100 supports several programmable page sizes for each bank of memory, such as 8 bits (256 bytes), 9 bits (512 bytes), 10 bits (1024 bytes), 11 bits (2048 bytes), and 12 bits (4096 bytes). In addition, controller 100 preferably allows each bank to have a different page size. Thus, for example, the first bank of memory can be configured to have a 256 byte page size, while the second bank of memory can be configured to have a 512 byte page size.

FIG. 3 shows a block diagram that illustrates page hit circuit 130 in accordance with the present invention. As shown in FIG. 3, page hit circuit 130 includes a first address latch 132 that latches the row address bits each time a page pointer signal PGP0 is asserted, and then outputs the latched row address bits each time the page pointer signal PGP0 is deasserted.

Similarly, a second address latch 134 latches the row address bits each time the page pointer signal PGPO is deasserted, and outputs the latched row address bits each time the page pointer signal PGPO is asserted. As a result, latches 132 and 134 toggle back and forth between captuπng the current row address bits to outputting the previous row address bits in response to the logic state of the page pointer signal PGPO.

FIG. 4 shows a block diagram that illustrates a circuit 400 for forming the page pointer signal PGPO. As shown in FIG. 4, a logic block 410 inverts the logic state of the page pointer signal PGPO to form an output signal INVPO each time the address strobe ADS indicates that the input address ADD is valid and the chip select signal SELO indicates that the input address ADD is to the first bank of memory, and passes the page pointer signal PGPO as the output signal INVPO at all other times.

The output signal INVPO, in turn, is passed by a multiplexer 420 when a terminate signal TERM, which is discussed in greater detail below, is in a first logic state, and passes the page pointer signal PGPO when the terminate signal TERM is in a second logic state. The signal output from multiplexer 420 is then latched by a flip-flop 430 with each processor clock edge. Thus, the page pointer signal

PGPO changes logic state each time a valid input address ADD is to the first bank of memory, unless the terminate signal TERM is in a predefined logic state.

Referring back to FIG. 3, page hit circuit 130 also includes a comparator 136 that compares the current row address bit pattern input to the first bank of memory with the last row address bit pattern input to the first bank, as held by either the first or second address latches 132 or 134. In operation, each time the current row address bit pattern matches the last row address bit pattern, page hit circuit 130 outputs the page hit signal PHO.

The number of row address bits-that are actually compared by comparator 136 is determined by the page size of the bank of memory For example, if the bank size is set to eight Mbytes, then 23 bit positions, i.e., bits [22:0], are required to define the eight Mbyte range If the page size is set to 1024 bytes, then ten bit positions, i.e., bits [9.0], are required to define the page Thus, in a 32-bit address, bits [22:10] must be compared

In the embodiment shown in FIGs. 1A-1C, rather than organizing the memory space as N Mbytes long by one byte wide, the address space is organized as N/2 Mbytes long by two bytes wide. Thus, an eight Mbyte bank size is only four Mbytes long since each address identifies two bytes of information A four Mbytes memory range, in turn, only requires 22 bit positions Thus, in the embodiment shown in FIGs 1A- 1C, bit [0], in combination with a byte-high enable signal BHE, identifies whether both bytes, only the low byte, or only the high byte is to be accessed, while bits [22 1] are utilized to identify the four Mbyte address range

As a result, continuing the above example, if the page size is set to 1024 bytes, then ten bit positions, l e , bits [10 1], are required to define the page Thus, in a 32-bit address, bits [22 11] must be compared

Referring back to FIGs 1A-1C, controller 100 additionally includes a second-bank page hit circuit 140 that outputs a page hit signal PHI when the chip select signal SEL1 indicates that the input address ADD is to the second bank of memory, the second series of control signals are set to predefined logic states, and the input address ADD is to the same page of memory in the second bank as the last memory address to the second bank Page hit circuit 140, which is shown in FIG 5, operates in the same manner as does circuit 130

Set up and control of the page size for each bank of memory is defined by a register within block 125 As shown in FIGs 1A-1C, block 125 outputs a first-bank page size word PS0 and a second-bank page size word PS1 which define the page sizes of the first and second banks of memory, respectively As stated above, the registers are set by wπting one or more control words to register block 125 Controller 100 further includes a RAS low timer 150 that corresponds with the first bank of memory, and a RAS low timer 160 that corresponds with the second bank of memory In operation, RAS low timer 150 measures the time that a first-bank row address strobe RAS0 is held low, and outputs a RAS high signal RASH0 each time timer 150 times out Similarly, RAS low timer 160 measures the time that a second-bank row address strobe RAS1 is held low, and outputs a RAS high signal RASH1 each time timer 160 times out As is well known, DRAMs frequently limit the amount of time that a row address strobe can be held low without corrupting the information stored in the DRAM

The RAS low time out penod is conventionally specified by the DRAM As a result, controller 100 preferably supports a programmable RAS low time out penod for both ϋmers 150 and 160 In the embodiment shown in FIGs 1A-1C, the time out penod for timers 150 and 160 is the same Alternately, timers 150 and 160 can be set to different time out periods

Set up and control of the RAS low time out period are defined by a register within block 125 As shown m FIGs 1A-1C, block 125 outputs a bank time out word TS which defines the RAS low time out penod for the first and second banks of memory If the RAS low timeout penod is greater than the refresh penod, however, the RAS low timeout penod may be set to any value greater than the refresh penod As stated above, the registers are set by wπting one or more control words to register block 125 As further shown in FIGs 1A-1C, controller 100 also includes a counter circuit 170 that outputs a start signal SRT a predetermined warm-up time after a system reset signal SYSRST is received, and that "outputs a refresh complete signal RCS after a predetermined number of refresh cycles are completed following receipt of the system reset signal SYSRST As is well-known, when first poweπng up, conventional DRAMs typically require that both a warm-up penod expire, and that a predetermined number of refresh cycles be run before information can be stored in the memory In the preferred embodiment, the predetermined warm-up time is approximately lOOμsec, while the predetermined number of refresh cycles is eight

Controller 100 further includes a refresh circuit 180 that measures a refresh penod to insure that the DRAMs controlled by controller 100 are peπodically refreshed In operation, refresh circuit 180 starts a refresh timer in response to a refresh acknowledge signal RFK, and outputs a refresh signal RFS each time a refresh time expires In the embodiment shown in FIGs 1A-1C the refresh time is set to expire multiple times each refresh penod to support an interval-type refresh mode where different groups of cells are refreshed in response to each refresh signal RFS Alternately the refresh time can be set to expire once each refresh penod to support a burst-type refresh mode where all of the cells are refreshed at one time Although any refresh technique can be utilized, controller 100 preferably supports the conventional CAS-before-RAS refresh timing. In addition, controller 100 also preferably supports a self-refresh mode. As is well known, more recent DRAMs can be commanded to enter a low-power self refresh state where, when in this state, the DRAM refreshes itself. This, in turn, allows controller 100 to be powered down, thereby saving power, without losing information stored in the DRAM.

Set up and control of the refresh period is defined for both banks of memories by a refresh rate register within fegister block 125. As shown in FIGs. 1A-1C, block 125 outputs a refresh rate word RR which defines the refresh rate for controller 100. As stated above, the registers are set by writing one or more control words to register block 125. In the present invention, the input address ADD is multiplexed so that the row and column addresses are output to the DRAMs during different clock cycles. FIG. 6 shows a block diagram that illustrates the address path for controller 100.

As shown in FIG. 6, the entire input address ADD is input to controller 100 while only bits [12:1] of the input address ADD are input to a multiplexer 610. (As stated above, the first bit position, i.e., bit [0], identifies which byte of each two byte address location is to be accessed). Multiplexer 610, in turn, passes bits [12:1], which represent the column address, when a row/column signal COL is in one logic state, and passes a row address RA output from controller 100 when the row/column signal COL is in the opposite logic state.

Multiplexer 610 can pass bits [12:1] even though all of the bits may not be needed to identify the column address because once the page sizes of the DRAMs are defined, the DRAMs will ignore the address bits that are more significant than those needed to address the page. Further, although multiplexer 610 is shown outside of controller 100, this functionality can alternately be incorporated within controller 100.

The row address bits are output from controller 100 by an address multiplexer circuit 190 that translates the input address ADD into the row address RA. FIG. 7 shows a block diagram that illustrates address multiplexer circuit 190.

As shown in FIG. 7, multiplexer circuit 190 includes a first translator 192 that translates the input address ADD into a first-bank row address RAO in response to the page size and the bank size of the first bank of memory. Similarly, a second translator 194 translates the input address ADD into a second- bank row address RAl in response to the page size and the bank size of the second bank of memory. For example, if the page size of the bank of memory coπesponding with translator 192 is 2 Kbytes, then 11 bit positions, i.e., bits [11:1], are required to define each page of memory. As a result, the thirteenth bit position, i.e., bit [12], defines the first bit of the row address of the first bank. The bank size, on the other hand, defines the upper bit limit. Thus, if the bank size is four Mbytes, then 22 bit positions, i.e., bits [21 :1], are required to define the bank of memory.

As a result, in operation, translator 192 translates bits [21:12] of the input address ADD to bits [12:1] of the output row address RA. (Since only bits [11:1] are required to define the row address, the logic state of bit [12] remains the same to save the power which would be required to change logic states). As further shown in FIG. 7, multiplexer circuit 190 also includes a multiplexer 196 that selects between the row address RAO output from translator 192, and the row address RAl output from translator 194 in response to the logic state of an access signal ACC. The access signal ACC, in turn, is derived from sequencer 220. Multiplexer 196 selects row address RAO when the access signal ACC is deasserted, and row address RAl when asserted. Set up and control of the page size for each bank of memory is defined by the first and second page size words PS0 and PS1, respectively. Set up and control of the bank size for each bank of memory, as well as the starting and ending addresses of each bank, are defined by a bank register within block 125. As shown in FIGs. 1A-1C, block 125 outputs a first bank size word BK0 and a second bank size word BK1 which define the bank sizes of the first and second banks of memory, respectively In addition, block 125 outputs a bank word BW that identifies the starting and ending addresses of each bank As stated above, the registers are set by writing one or more control words to register block 125 Refemng again to FIGs 1A-1C, controller 100 further includes a sequencer 210 that controls the operation of the first bank of memory FIGs 8A and 8B show a state machine that illustrates the operation of sequencer 210

As shown in FIGs 8A and 8B, operation begins in the startup stage at state S(0) with the assertion of a system reset signal SYSRST which indicates that controller 100 has been powered on or reset The reset signal SYSRST starts the timer in counter circuit 170 which, after timing out, outputs the start signal SRT which causes operation to move to state S(l) and then to state S(2)

In addition, the startup stage synchronizes the controller clock signal, which preferably oscillates at twice the frequency of the system clock signal, with the system clock signal In addition to aligning the edges of the clock signals, the synchronization process also aligns the pulses of the controller clock signal with the phases of the system clock signal so that operation transfers to state S(2) only dunng the first half-peπod of the system clock signal

After the clock signals are synchronized, operation transitions to state S(2), the first state of the refresh stage, then on to states S(3), S(4), and S(5) with the next three controller clock cycles As stated above, the refresh stage preferably supports the well-known CAS-before-RAS refresh timing

When supporting CAS-before-RAS, the refresh stage drops the column address strobe(s) in state S(5), and then drops the row address strobe RASO in state S(6) As descnbed in greater detail below, sequencer 210 outputs both an even-byte column address strobe CASL0 and an odd-byte column address strobe CASH0 when the column address strobe(s) are dropped dunng refresh

With the next controller clock cycle, operation moves to state S(7) where the refresh stage checks the state of a self-refresh signal SRF output from a register in block 125 The self-refresh signal SRF is set when a user intends to place the DRAMs controlled by controller 100 in a self-refresh mode of operation As stated above, the registers m block 125 are set by wnting one or more control words to register block 125

When the self-refresh signal SRF is deasserted, operation advances to state S(8), where the column address strobes CASL0 and CASH0 are raised, and then on to states S(9)-S(13) where, at state S(13), an enable signal EN, which disables controller 100, is checked

When the enable signal EN is asserted, operation passes to state S(14) where the row address strobe RASO is raised in accordance with the CAS-before-RAS timing conventions In addition, the refresh stage also checks the logic state of the refresh complete signal RCS output from counter circuit 170 As stated above, the refresh complete signal RCS indicates when a predetermined number of efresh cycles have been completed following a system reset

Thus, if the refresh complete signal RCS indicates that less than the required number of refresh cycles have been run, then operation returns to state S(3) However, if the required number of refresh cycles have been run, operation transitions to state S(15), the first state in the pagemiss stage

As shown in FIGs 8A and 8B, operation shifts back and forth between stages S(15) and S(16) until the chip select signal SELO is asserted in state S(16), and the terminate address signal TERM is deasserted In the present invention, the terminate address signal TERM indicates whether the DRAM memory request is to be abandoned Thus, when the terminate address signal TERM is asserted, operation continues to shift between states S(15) and S(16) even if the chip select signal SELO is asserted When t ^o chip select signal SELO is asserted and the terminate address signal TERM is deasserted operation moves to state S(17) where the row/column signal COL is deasserted The row/column signal COL indicates whether the row address RA or the column address is valid In addition, while in state S(17), the pagemiss stage also checks the state of an extended row high signal ERH which, as descnbed in greater detail below, indicates whether the high logic state of the row address strobe RASO is to be extended.

When the extended row address signal is deasserted, operation moves directly to state S(18) where the row address strobe RASO is deasserted. When, on the other hand, the high logic state of the row address strobe RASO must be extended, operation moves to state S(18) via states S(38) and S(39).

From state S(18), operation moves to state S(19), then to state S(20) where the row/column signal COL is reasserted, which indicates that the column address is valid. In addition, the state of an extended column low signal ECL is checked. The extended column low signal ECL signal, which is also described in greater detail below, indicates whether the low logic state of the column address strobes CASLO and CASHO are to be extended.

When the extended column low signal is deasserted, operation shifts to state S(21) where both the column address strobes CASLO and CASHO are deasserted when both bytes of information are requested. However, when only the even-byte or odd-byte is requested, sequencer 210 outputs only the even-byte column address strobe CASLO or the odd-byte column address strobe CASHO, respectively. The logic state of bit [0] and the byte-high enable signal BH determine whether the low, the high, or both bytes are to be accessed.

With the next clock cycle, operation moves from state S(21) to state S(26) where the column address strobes CASLO and CASHO (or CASLO or CASHO only) are reasserted. In addition, a ready signal RDYO, which indicates to the CPU that valid information is on the data bus DBUS, is also asserted in state S(26).

As shown in FIGs. 8A and 8B, when the extended column low signal ECL is asserted, operation moves from state S(20) to state S(26) via states S(22)-S(25), thereby leaving the column address strobes CASLO and CASHO low for one additional controller clock cycle, and high for one additional controller clock cycle. In the present invention, controller 100 preferably supports a series of timing options. FIGs. 9A-

9F show timing diagrams that illustrate these options. For example, as shown in FIG. 9A, with a three cycle option, the row address strobe RAS is held high for one clock cycle following a page miss while, as shown in FIG. 9D, the row address strobe RAS is held high for one and a half clock cycles with a four cycle option. Similarly, with the three cycle option, the column address strobes CASLO and CASHO fall one clock cycle after the row address strobe RAS falls while, with the four cycle option, the column address strobes CASLO and CASHO fall one and a half clock cycles later.

As shown in FIGs. 9A and 9D, the column address strobes CASLO and CASHO are held low for one-half of a clock cycle. However, when the extended column low signal ECL is asserted, the column address strobes CASLO and CASHO are held low for one clock cycle.

As described below, a long miss signal indicates whether the row address strobe RAS should be held high for one clock cycle or one and a half clock cycles. If the extended row high signal ERH is also asserted, then the row address strobe can be held high for an additional clock cycle. As a result, various combinations are possible which, in turn, allow controller 100 to accommodate a wide variety of DRAMs.

As further shown in FIG. 9A, information is valid for a read a delay time after the column address strobes CASLO and CASHO are lowered, the row address strobe RAS is lowered, or the column address becomes valid, depending on which DRAM specification is controlling. In addition, the information remains valid until the column address strobes CASLO and CASHO rise (plus some asynchronous hold time). Thus, v hen the column address strobes CASLO and CASHO are held low for on!^{* *} one-half of a clock period, the information remains valid for only a short period of time.

Thus, referring again to FIGs. 1A-1C, to insure that the CPU can capture the information during the short time that the information is valid, controller 100 further includes a capture and parity circuit

SUBSTITUTE SHEET (RULE 6Ϊ 230 that captures valid information on the data bus DBUS one controller clock cycle after the column address strobes CASLO and CASHO fall, and that redπves the information on a processor bus PBUS so that the CPU can capture the information The CPU is notified that the information is valid via the ready signal RDYO FIGs 10A and 10B show block diagrams that illustrate the data path for DRAM writes and reads, respectively As shown in FIG 10A, capture and parity circuit 230 captures data from the processor bus PBUS when a panty enable signal PEN is set to a predefined logic state and, in response, generates and outputs a data panty-out signal PBO The panty enable signal PEN is set to a predetermined logic state by a control word input to register block 125 (see FIGs 1A-1C) FIG 10B shows a block diagram that illustrates the data path for DRAM reads As shown in FIG

10B, data is latched by the capture and panty circuit 230 from the data bus DBUS, and redπven to the processor on the processor data bus PBUS In addition to captunng and redπving information on the data and processor busses DBUS and PBUS, respectively, capture and panty circuit 230 also receives and checks a data paπty-in signal PBI when panty checking is enabled by the panty enable signal PEN Further, as shown in FIGs 1A-1C, when a panty error is detected, capture circuit 230 outputs a panty error signal PRR to register block 125 which sets a panty error bit in a panty register Parity error can then be detected by reading the panty register within register block 125 In addition, capture and panty circuit 230 can be configured to output a panty interrupt signal INT in response to the panty error signal PRR Refemng again to FIGs 8A and 8B, from state S(26), operation moves back to state S(21) if the chip select signal SELO remains asserted, thereby indicating that another memory request is pending, and the page hit signal PHO is asserted, thereby indicating that the memory request is to the same page of memory

On the other hand, if the chip select signal SELO is asserted and the page hit signal PHO is deasserted, thereby indicating that the memory request is to a different page of memory, operation shift- to state S(33), and then to state S(32) where the long miss signal is checked As descnbed above, the long miss signal indicates whether the row address strobe RAS is to be held high for an additional controller clock cycle Operations then advances to state S(19), or state S(17), depending on whether the logic high of the row address strobe RAS is to be extended If, however, the chip select signal SELO is deasserted in state S(26), thereby indicating that no additional memory request is pending, operation transitions to state S(29) From state S(29), operation passes to state S(30), and then moves back and forth between states S(29) and S(30) until the chip select signal SELO and the page hit signal PHO are received

If the chip select signal SELO and the page hit signal PHO are asserted, thereby indicating a valid memory request to the same page of memory, operation transitions to state S(21) and continues as descnbed above If, on the other hand, the page hit signal PHO is deasserted, thereby indicating that the memory request is to a different page of memory, operation transitions to state S(33) and continues as descnbed above

As further shown in FIGs 8A and 8B, the refresh stage, via state S(31 ), can be entered from states S(16), S(26), or S(30) In states S(16) and S(30), if the refresh signal RFS is received at substantially the same time that the chip select signal SELO is received, operation first transitions to state S(31) where the refresh cycle is performed before the memory request In state S(26), however the memory access is completed before the refresh cycle is begun

In state S(31), as well as in state S(2), the logic state of a busy signal BYO is set to indicate that a refresh cycle is in operation The busy signal BYO, in turn, is utilized by chip select circuit 1 10 to hold the chip select signal SELO when the chip select signal SELO is asserted dunng a refresh cycle The terminate signal TERM is also utilized along with the busy signal BYO such that the SELO signal is not held as descnbed above when the TERM signal is asserted The advantage of holding the chip select signal SELO is that, rather than inhibiting all bus traffic during a refresh cycle as is conventionally done, the bus is able to respond to other devices at the same time that a refresh cycle is occuring because the chip select signal SELO is held.

Referring again to state S(26), operation advances from state S(26) and state S(30) to state S(15) when the chip select signal SELO is deasserted and the RAS high signal RASHO is asserted, thereby indicating that the row address strobe RASO has been held low for the maximum period of time.

As stated above, the refresh stage checks the status of the self-refresh signal SRF during state S(7). If the self-refresh signal SRF is set to a predetermined logic state, operation passes to state S(34). Operation then moves to state S(35), state S(36), and back to state S(35) until the logic state of the self- refresh signal SRF is changed, or a wake-up interrupt signal WK is received, whereupon operation transitions back to state S(31) to perform one or more refresh cycles.

The advantage of feeding the wake-up interrupt signal WK, which represents any system interrupt, directly to sequencer 210 is that the processor can be completely powered down. Typically, the interrupt service routines are stored in the memory space controlled by the DRAM controller. If the wake-up interrupt were only fed to the processor, the processor would have to remain powered up to first wake up the DRAM controller, and then access the stored interrupt service routines.

Referring again to FIGs. lA-lC, controller 100 also includes a sequencer 220 that controls the operation of the second bank of memory. Sequencer 220 operates in the same manner as does sequencer 210. With respect to the operation of both sequencers 210 and 220, operation will not transfer from state S(15) or state S(30) to state S(31) to begin a refresh cycle unless both sequencers 210 and 220 can transition during the same controller clock cycle.

Thus, sequencers 210 and 220 each output other signals OTΗ0 and OTH1, respectively, which each indicate that the sequencer is engaged in a memory access. As a result, operation of both sequencers transfers to state S(31) when both of the other signals OTH0 and OTH1 are deasserted. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No. 08/ entitled "DISPLAY CONTROLLER

CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-62700); U.S. patent application Serial No. 08/ , entitled

"SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSCl-62800); U.S. patent application Serial No.

08/ entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS

(DMA) CONTROLLER" (atty. docket no. NSC 1-62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING

MINIMUM PULSE WIDTH" (atty. docket no. NSC 1-63000); U.S. patent application Serial No.

08/ entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING

MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSC1-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION

SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application

Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC 1-63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT

OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63500); U.S. patent application Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A

32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application Serial No.

08/ entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no.

NSC 1-63700); U.S. patent application Serial No. 08/ entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND

COUNTER" (atty. docket no. NSC 1-63800); U.S. patent application Serial No. 08/ , entitled

"AREA AND TIME EFFICIENT HELD EXTRACTION CIRCUIT" (atty. docket no. NSCl-63900);

U.S. patent application Serial No. 08/ , entitled "N ON- ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIReOTT^*(atfy. docket no. NSC 1-64000);

U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION

DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED

DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC1-64200); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR DESIGNATING INSTRUCTION

POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC1-64300); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR GENERATING A DEMAND-BASED

GATED CLOCK" (atty. docket no. NSC 1-64500); U.S. patent application Serial No. 08/ , entitled "INCREMENTOI-DECREMENTOR" (atty. docket no. NSC 1-64700); U.S. patent application Serial No. 08/ entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY

REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC 1-64800); U.S. patent application

Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC1-64900);

U.S. patent application Serial No. 08/ , entitled "TWO TIER PREFETCH BUFFER

STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application Serial No. 08/ , entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC 1-65100); U.S. patent application Serial No. 08/ , entitled "A PIPELINED

MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no.

NSC1-65200); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFHCIENT COMPUTAΗON OF A 486™ MICROPROCESSOR COMPATIBLE POP

INSTRUCTION" (atty. docket no. NSC 1-65700); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application

Serial No. 08/ entitled "METHOD OF IMPLEMENTING FAST 486™ MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC1-65900); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT

PREVENTS THECACHEFROM BEING READWHENTHECONTENTS OFTHECACHEARE

INVALID" (atty. docket no. NSCl-66000); U.S. patent application Serial No. 08/ , entitled

"DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY "REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application Serial No. 08/ , entitled

"INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN

COUNT" (atty. docket no. NSCl-66400); U.S. patent application Serial No. 08/ , entitled

"SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no.

NSCl-66500); U.S. patent application Serial No. 08/ entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC 1-66600); U.S. patent application Serial No. 08/ entitled "CONFIGURABLE

POWER MANAGEMENT SCHEME" (atty. docket no. NSC 1-66700); U.S. patent application Serial No.

08/ , entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no.

NSCl-67000); U.S. patent application Serial No. 08/ entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT" (atty. docket no. NSC1-671O0); U.S. patent application

Serial No. 08/ entitled "IN-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT" (atty. docket no. NSC1-67400 ; U.S. patent application Serial No. 08/ entitled "DISPLAY

CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC1-67500); U.S. patent application Serial No. 08/ entitled

"INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC 1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK

TEST METHOD AND APPARATUS" (atty. docket no. NSCl-68000).

It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

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SUBSTITUTE SHEET (RULE Ϊ

Claims

WHAT IS CLAIMED IS:

1. A dynamic random-access-memory (DRAM) controller for processing memory requests output by a processor to one or more DRAMs associated with the processor, and for insuring that the

DRAMs are periodically refreshed, the controller comprising: a memory space register that defines a plurality of address ranges, each address range having a starting address and an ending address; a plurality of chip select circuits, each chip select circuit having a corresponding address range, and asserting a chip select signal when an input address falls within the corresponding address range, and a first plurality of control signals are set to predefined logic states; a plurality of page hit circuits, each page hit circuit having a corresponding chip select signal and a corresponding address range, and asserting a page hit signal when the corresponding chip select signal is asserted, a second plurality of control signals are set to predefined logic states, and the input address is to a same page of memory within the corresponding address range as a last input address to the conesponding address range; and a plurality of sequencers, each sequencer having a corresponding chip select signal and a corresponding page hit signal, sequentially outputting a row address strobe and a column address strobe when the conesponding chip select signal is asserted and the corresponding page hit signal is deasserted, and outputting a column address strobe when both the corresponding chip select signal and the coπesponding page hit signal are asserted.