WO1996002042A1

WO1996002042A1 - Supporting component for use in chip cards or other data medium boards

Info

Publication number: WO1996002042A1
Application number: PCT/EP1995/002154
Authority: WO
Inventors: Frank Druschke; Roland Diemer; Gerhard Elsner; Wolfgang Schmid; Reinhold Braun; Harald Gruber; Wolfgang Beck; Rainer Kratzert
Original assignee: International Business Machines Corporation
Priority date: 1994-07-11
Filing date: 1995-06-06
Publication date: 1996-01-25
Also published as: DE4424396A1; DE4424396C2

Abstract

The proposal is the use of the prior art C4 technique to produce an electrical connection between an IC unit (2) and a substrate component (4) designed for inclusion in chip cards or other data medium boards. This results in facilities for contact between the IC unit (2) and the substrate component (4) permitting a high degree of integration of the IC unit (2) and a correspondingly large number of contacts between the IC unit (2) and its environment, makes contact possible over the entire surface of the IC unit (2) and, for the same requirements for contact between the IC unit (2) and the substrate (4), lower structural heights of the connection between said IC unit (2) and the substrate (4).

Description

DESCRIPTION

CARRIER ELEMENT FOR INSTALLATION IN CHIP CARDS OR OTHER DATA CARRIER CARDS

Field of the Invention

The invention relates to the establishment of an electrical connection between an IC component (chip) and a carrier element which is provided for installation in chip cards or other data carrier cards.

State of the art

The chip cards used recently for information processing (e.g. multifunctional chip cards or telephone cards) usually consist of a single or multi-layer insulated carrier element which e.g. carries the integrated semiconductor circuit (chip) in a recess. After contacting, the chip is cast with a casting resin to protect the chip from environmental influences.

The wiring of the chip with the external contacts can be carried out according to the teaching of the patent specification DE-C-3029667 via a contacting technique, the so-called "wire bonding". For this purpose, the connection points of the chip are connected to the contact surfaces of the carrier element via fine gold wires.

United States Patent US-A-4,474,292 discloses tape automated bonding (TAB) as a way of making contact between the chip and the contact surfaces of the carrier element. This involves wiring chips on a plastic carrier (dielectric), preferably in bulk articles, the wiring patterns being applied to an endless carrier tape. For contacting the chip with the respective Wiring, the wiring pattern contains contact fingers, which are guided in the form of a so-called contact spider from the outside towards the inside of the chip. The chip is then applied, for example by ultrasonic welding, to the ends of these contact fingers of the circuit. The teaching of this document forms the preamble of claim 1.

In the case of the contacting options for carrier elements for chip cards according to the prior art, such as TAB or "wire bonding", the respective contact surfaces can only be localized along the outer sides of the contact surface of the chip on the carrier element. This means that higher integration densities with a correspondingly large number of required connections cannot be achieved or can only be achieved with great difficulty.

Both contacting methods according to the state of the art also have in common that the contacts of the carrier element must be guided across the surface in the direction of the chip. For this reason, they cannot be expanded at will for future developments towards highly integrated chip cards, because then not all connections can be accommodated on the chip periphery. A higher need for information also leads to expanded lateral dimensions of the chips, but this is limited by the contacting.

Summary of the invention

It is therefore an object of the invention

Possibility of contact between the chip and the

Find carrier element that enables high integrations of the chip with a correspondingly high number of contacts for communication of the chip with its surroundings. It is a further object of the invention to find a contacting option which makes contacting possible over the entire contact surface of the chip.

It is a further object of the invention to find a contacting possibility which has no restrictive effect on the lateral dimensions of the chip and which has a smaller area for the application of the mechanical stress.

It is also an object of the invention to find a contacting possibility which, with the same conditions for contacting the chip with the carrier element, enables lower overall heights of the connection of the chip with the carrier element.

It is also an object of the invention to find, in addition to the known contacting options for chips on the carrier elements for installation in chip cards, a further contacting option which, like the known methods, can be carried out simply and inexpensively.

It is also an object of the invention to find a mechanically more favorable possibility of contacting chips on the carrier elements for installation in chip cards.

According to the invention, the objects are achieved in that the "Controlled Collapse Chip Connection" (C4) technique, known as such, is used to establish the electrical connection between the IC component and the carrier element.

This C4 technique is e.g. known from

LFMiller, Controlled Collapse Reflow Chip Joining, IBM J.Res.Develop.13, No.3, 239-250 (1969) and was developed to mount up to 120 chips on a multilayer ceramic carrier (MLC). With C4 technology, the wiring lengths between the chips become very short, which in turn leads to shorter signal delays. A correspondingly high chip packaging density cannot be achieved with "wire bonding" or TAB technology. In addition, the compact design of the contacts means that the C4 technology enables more favorable heat dissipation via the contacts into the substrate.

For the use according to the invention of the C4 technology for the production of the electrical connection between the IC component and the carrier element, however, the above-mentioned tasks of the C4 technology play only a subordinate role both for producing high chip packaging densities and for dissipating heat.

In contrast to the contacting options according to the prior art, the process according to the invention enables the use of the C4 technology to distribute the contact areas, both on the chip and on the carrier element, over the entire contact area of the chip on the carrier element and can be correspondingly realize any integration densities of the chips.

The use of the C4 technology also removes the limitation of the contacts to the outside of the chips. This results in the possibility, with the same required connection pattern on the contact side of the carrier element to the outside world, of extending the lateral dimensions of the chip beyond this connection pattern. In contrast, in the contacting methods according to the prior art, the lateral dimensions of the chip have to be caused by the process stay within the connection pattern.

The possibility of contacting according to the invention also enables the respective contact surfaces to be sharply delimited on the region imaged by the projection of the chip, perpendicular to the contact surface of the chip on the carrier element, on the carrier element. On the one hand, this reduces the risk of the electromagnetic interference of the contact surfaces and corresponding feeds with one another, especially since the overall contact surfaces can also be made smaller than in the prior art. On the other hand, the necessary further wiring to the contact side of the carrier element to the outside world is eliminated, in particular if so-called vias are exclusively used in the carrier element.

Furthermore, the sharp delimitation of the respective contact areas on the respective projection area of the chip enables a higher area compression of several chips next to one another on the carrier element. In this way, several small chips can be combined in the area, which in turn has a favorable effect on the mechanical durability of the overall arrangement. In this regard, it should be mentioned that the mechanical durability of chip cards plays an essential role, since these are mobile everyday objects. Overall, the process according to the invention results in mechanically more favorable contacting of the chip on the carrier element than is known from the prior art.

The contacting process according to the invention results in the contact areas on and on the chip describe the carrier element in approximately the same area. This in turn results in essentially uniform distributions of the current densities along the contacts, which likewise leads to more favorable electromagnetic behavior.

In a further embodiment of the invention, the carrier element has a non-conductive layer and a conductive layer, and the IC module can be inserted into a recess in the non-conductive layer. In another embodiment, plated-through holes are introduced into the non-conductive layer, on which the IC module is then placed. The vias can be recessed relative to a contact surface of the chip on the carrier element. All of these embodiments enable the production of carrier elements which are as flat as possible and assembled with chips, as is required for use in chip cards.

Description of the drawings

To explain the invention in more detail, the following are

Embodiments described with reference to the drawings.

La shows an inventive method for contacting a chip on a carrier element,

1b shows the process of contacting the chip with the contact plane,

1c shows the process of potting the chip soldered on the contact level, 2 shows the type of chip mounting on a flexible carrier element,

Figure 3a shows the process of applying the

Solder connection as individual components on the contact surfaces of the side of the chip to be contacted,

3b shows the solder balls formed on the contact surfaces by a heat process as lead / tin alloys,

Fig. 4 shows a further embodiment of the

Invention that enables a reduction in the total height of the connection between chip and insulator.

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 a shows a method according to the invention for contacting a chip 2 on a carrier element 4. The carrier element 4 consists of a contact plane 8, which is applied flat on an insulator 6, the insulator 6 having a recess 10 into which the Chip 2 is to be introduced. The insulator 6 is preferably made of fiber-reinforced polyimide. In a further step, which is not part of the invention, the carrier element 4 is inserted into a so-called chip card, on which data can be stored and processed. The contact plane 8 of the carrier element 4 then serves to contact the chip 2 with the outside world, e.g. a smart card reader, according to the applications of the smart card.

Through a process to be explained below, so-called solder balls 14 are applied to contact surfaces 16-24 on the side of the chip 2 to be contacted. As an alternative to this, the solder balls 14 can also be placed on those corresponding to the contact surfaces 16-24. Contact surfaces 26-34 are applied to the contact plane 8 of the carrier element 4. A combined application of the solder balls 14 is also possible both on contact surfaces of the chip 2 and on the contact plane 8.

Fig. Lb shows the process of contacting the chip 2 with the contact plane 8. First, the chip 2 is roughly aligned approximately on the contact plane 8, so that the contact surfaces of the chip 2 and the contact plane 8 to be contacted essentially opposite each other and each Include solder balls 14. Furthermore, at least as much heat is supplied by a soldering process until the solder balls 14 melt and a galvanic contact is established between the corresponding contact surfaces of the chip 2 and the contact plane 8. Due to the effect of equalizing and minimizing the total sum of the surface tensions of the solder balls, provided the geometry of the contact areas is essentially the same, the chip 2 adjusts itself independently on the contact plane 8. The contact surfaces to be contacted on the chip 2 and on the carrier element 4 are oriented in such a way that the respective contact surfaces of the chip 2 and the carrier element 4 are essentially centered. This ensures a simple and highly precise alignment process of the chip 2 on the carrier element 4, which can also automatically compensate for smaller inaccuracies in the contact geometries. The area between the contact surfaces to be contacted on the chip 2 and on the carrier element 4 form the contacts between the chip 2 and the carrier element 4. During the subsequent cooling step, a slight pulling apart of the chip 2 and the contact plane 8 perpendicular to the contact surface of the chip 2 on the contact plane 8, without the contact surfaces being detached from one another, can increase the mechanical strength of the resulting soldered connection.

In order to increase the mechanical strength of the overall arrangement, consisting of the chip 2 soldered on the contact plane 8, in particular the contacts, the latter is encased in an appropriate casting compound 36 in a process following the soldering process. The potting compound 36 must have such a viscosity that the chip 2 can be cast in and is thereby permanently fixed. 1c shows the process of potting the chip 2 soldered on the contact plane 8. The potting is carried out in such a way that the chip 2 lying in the recess 10 is completely embedded in the insulator 6 of the carrier element 4.

As an alternative to that shown in Figs. La-c embodiment shown, it is also possible not to mount the chip 2 in a recess 10 or an opening of the insulator 6, but directly on the surface of the carrier element 4. 2 shows this type of chip mounting on the flexible carrier element 4. The insulator 6 has so-called plated-through holes 38-40 for producing conductive connections between contacts on an upper side 42 and a lower side 44 of the insulator 6. Depending on the application, a further contact plane 52 corresponding to the contact plane 8 can be applied to the insulator 6 on the underside 44. The plated-through holes 38-40 now allow removal of those connected to the chip 2 on the surface 42. Contact surfaces 46-50 on the underside 44 of the carrier element 4. From there, these can be continued as desired.

At the contact surfaces 46-50 of the top 42 of the insulator 6, analog to that in FIGS. La-c shown method of chip 2 applied and sealed after soldering with a resin cap 54. This type of chip assembly is particularly advantageous for the production of flexible circuit cards.

An increased number of contacts, distributed over the entire contact surface of the chip 2, requires a corresponding distribution function of the contacts through the carrier element 4. Thus, the contacts from the surface 42 of the carrier element 2 either simply have to be on the underside, as shown in FIG. 2 44 of the carrier element 4 can be contacted, or possibly also guided outwards in the insulator 6 parallel to the upper side 42.

3a now shows the process of applying the soldered connection as individual components to the contact surfaces 16-24 of the side of the chip 2 to be contacted for an exemplary embodiment. A lead / tin metallurgy is vacuum coated onto those not covered by a mask 60. Brought contact surfaces 16-24. In a subsequent heating process, for example a reflow process, the solder balls 14 form as lead / tin alloys on the contact surfaces 16-24 due to the heat energy from the cylindrical lead and tin deposits (FIG. 3b). The chip can then be assembled and soldered analogously to the method described above. If the eutectic composition of lead / tin (63% Sn / 37% Pb) is used, the melting temperature of the eutectic is Composition about 183 ° C. Using a different composition of the lead / tin alloy than the eutectic, other desired melting temperatures can be set according to the lead-tin ratio. Because of these melting temperatures, materials for the insulator 6 are, in particular, polyimides or polycyanate esters or BT resins (bismaleimide triazine), which can also be fiber-reinforced.

FIG. 4 shows a further embodiment of the invention, which enables a reduction in the total height of the connection between chip 2 and insulator 6. The plated-through holes 38-40 are in this case made smaller than the thickness of the insulator 6 between the upper side 42 and the lower side 44. The plated-through holes 38-40 have further contact surfaces 60-64 on the side opposite the contact surfaces 46-50. These contact surfaces 60-64 are now approximately aligned with the underside 44 of the insulator 6, so that the contact surfaces 46-50 are no longer approximately aligned with the upper side 42 as in FIG. 2, but are recessed between the upper side 42 and the underside 44 lie. The solder balls 14 can now be dimensioned such that after the chip 2 and the insulator 6 of the carrier element 4 have been joined together, the chip 2 lies approximately on the insulator 6 or at least the total height of the chip 2 and carrier element 4 is reduced. Analogously to the embodiment shown in FIG. 4, the contact surfaces 16-24 can also be deepened relative to the contact surface of the contact side of the chip 2. For this purpose, the chip 2 would have to have a correspondingly designed shape of the connection side with the contact surfaces 16-24.

Claims

PATENT CLAIMS

1. Carrier element (4) for installation in chip cards or other data carrier cards, with

at least one IC module (2) and

Contacting in an area between the respective contact surfaces (16-24) to be contacted on the respective IC component (2) and contact surfaces (26-34) on the carrier element (4), which are used to produce conductive connections between the contact surfaces (16-24 ) of the respective IC component (2) and the contact surfaces (26-34) of the carrier element (4),

characterized in that

the contact surfaces (16-24) of the respective IC component (2) and the contact surfaces (26-34) of the carrier element (4) lie in the projection of the respective IC component (2) and describe approximately the same area.

2. Carrier element (4) according to claim 1, characterized in that the contact surfaces (16-24) can be distributed over the entire projection of the respective IC component (2).

3. Carrier element (4) according to one of the preceding claims, characterized by a, the respective IC component (2) enveloping (54) or in the carrier element (4) embedding (36), sealing compound.

4. Carrier element (4) according to one of the preceding claims, characterized in that the contact surfaces (16-24) of the IC component (2) and the contact surfaces (26-34) of the carrier element (4) are aligned opposite one another.

5. carrier element (4) according to any one of the preceding claims, characterized in that the contact surfaces (46-50 in Fig. 4) of the IC component (2) and / or the contact surfaces (26-34) of the carrier element (4) opposite a support surface (42) of the IC module (2) on the support element (4) are recessed.

6. A method for producing an electrical connection between an IC chip (2) and a carrier element (4) which is provided for installation in chip cards or other data carrier cards, characterized in that the C4 technology known as such is used.

7. The method according to claim 6, characterized in that the carrier element (4) has a non-conductive layer (6) and a conductive layer (8).

8. The method according to claim 7, characterized in that a recess (10) is introduced into the non-conductive layer (6) and the IC module (2) is inserted into the recess (10).

9. The method according to any one of claims 7 or 8, characterized in that vias (38-40) are introduced into the non-conductive layer (6) and the IC module (2) is placed on the vias (38-40).

10. The method according to claim 9, characterized in that the vias (38-40) compared to one Contact surface (42) of the IC module (2) on the support element (4) are recessed.

11. A method for establishing an electrical connection between an IC component (2) and a carrier element (4), which is intended for installation in chip cards or other data carrier cards, with:

a first step of applying a solderable connection (14) to the contact surfaces (16-24) of the IC component (2) and / or the contact surfaces (26-34) of the carrier element (4) between which the contacting is to take place;

a second step of bringing the contact surfaces (16-24) of the IC component (2) and the contact surfaces (26-34) of the carrier element (4) between them, at least until the solderable connection (14) is made with the contact the corresponding contact surfaces (16-24, 26-34) is connected and

a third step of heating the solderable connection, at least until the corresponding contact surfaces (16-24, 26-34) are completely wetted with the solderable connection (14).

12. The method according to any one of the preceding claims 6 to 11 with a step of at least partially casting or embedding the at least one IC module (2) with a casting compound (36, 54) in the carrier element (4).