WO1994027295A1

WO1994027295A1 - Non-volatile memory device and method for adjusting the threshold value thereof

Info

Publication number: WO1994027295A1
Application number: PCT/JP1994/000759
Authority: WO
Inventors: Hiroshi Gotou; Toshifumi Asakawa
Original assignee: Nkk Corporation
Priority date: 1993-05-11
Filing date: 1994-05-11
Publication date: 1994-11-24
Also published as: GB2283345A; US5748530A; KR950702326A; US5729494A; GB9424539D0; KR0156590B1; DE4493150T1; JPH07508121A; DE4493150C2; GB2283345B; TW357336B

Abstract

In a non-volatile semiconductor memory device including a floating gate type memory cell, after the drain or source is charged, it is placed in an electrically floating state and a signal with alternately changing positive and negative potentials is applied to the control gate of the memory cell so as to reduce the charges stored in the floating gate, thereby converging the threshold voltage of the memory cell into a predetermined voltage. Thus, a write/erase operation in the memory device can be carried out surely in a short time.

Description

NON-VOLATILE MEMORY DEVICE AND METHOD FOR ADJUSTING

THE THRESHOLD VALUE THEREOF

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile

semiconductor memory device which can electrically rewrite

information or data, and more particularly to a non-volatile

semiconductor memory device which can simply and surely perform write and erase operations.

2. Description of the Prior Art

In conventional non-volatile semiconductor memory

devices, the operation of rewriting stored data can be

classified into (1) a system of write by hot-electrons and erase by tunnelling currents and (2) a system of write and

erase by tunnelling currents.

The former rewrite system is directed to an electrical

erasing type flash EEPROM. The write operation is made as

follows. A write voltage Vpp is applied to both control gate and drain of a memory cell to inject hot electrons into

the floating gate. Therefore, the threshold voltage Vth for

in the memory cell depends on the channel length, the thickness of a tunnelling insulating film and a source-drain

voltage. This results in a wide distribution of the

threshold voltages Vth after write in memory cells as shown

in Figs. 38A and 38B.

The erase operation is made as follows. With the

control gate connected to ground, an erase voltage Vpp is

applied to a source (or drain) electrode of the memory cell

to extract the electrons trapped in the floating gate into the source (or drain) electrode. As in the write operation, in the erase operation also, the threshold voltage depends on the voltage on a word line, the drain voltage and the

tunnelling insulating film thickness. This results in a

wide distribution of the threshold voltages Vth after erase in memory cells as shown in Figs. 38A and 38B. The latter rewrite system is directed to an NAND type

EEPROM. In this non-volatile memory, the write and erase

operations are performed using the tunnelling current from

the entire floating gate. As in the above erase operation,

the threshold value Vth depends on the voltage on a word

line, the drain voltage and the tunnelling insulating film thickness. This results in a wide distribution of the

threshold voltages Vth after write and erase in memory cells

as shown in Fig. 38C. Incidentally, Fig. 38D shows the distribution of

threshold voltages Vth in an ultra-violet erasing type

UVEPROM. The write operation is performed in such a manner

that a write voltage Vpp is applied to both control gate and

drain electrode of a memory cell to inject hot-electrons

into the floating gate. This results in a wide distribution

of the threshold voltages Vth after write in the memory

cells as in the flash EEPROM. On the other hand, the erase operation is performed in such a manner that the electrons

trapped in the floating gate are extracted by irradiation of

ultra-violet rays. This results in a sharp distribution of

the threshold voltages Vth in the neighborhood of 0.8 V

after erase in the memory cells. In Figs. 38A to 38D showing the distributions of threshold voltages, it should

be noted that the ordinate denotes a threshold voltage Vth in a memory cell and the abscissa denotes its frequency

thereof, and noted that the state with charges stored in a

floating gate is referred to as "0" data whereas the state with no charges stored in the floating gate is referred as

to "1" data.

As described above, the conventional non-volatile

semiconductor memories are characterized by a relatively

wide distribution of threshold voltages Vth. Therefore, the write and erase operations cannot be executed with the same

threshold voltage Vth set. The threshold voltages fluctuate

in the same memory chip also. So, generally, the write time

is changed for each bit so that the threshold volatges are placed in a predetermined range. This takes a relatively

long write time.

Further, the conventional non-volatile semiconductor

memories are provided with a logic circuit for detecting the

write state or erasure state of a memory cell and modifying it. The logic circuit occupies a larger area in a semiconductor memory device. In many cases, the logic

circuit detects the write or erase state from the drain

current flowing through a memory cell.

For example, JP-A(Laid-open)-64-46297 filed by Intel

Corporation (Inventor: Winston K. M. Lee) proposes logic circuits as shown in Figs. 39A and 39B. The erasing for a non-volatile memory cell as shown can be executed by a

specific circuit which controls the final potential of the

floating gate.

As shown in Fig. 39A, a non-volatile memory cell 1 is provided with a control gate 2 and a floating gate 3. An

erasing voltage source 7 is provided to supply an erasing

voltage to the source S of the memory cell. A feedback amplifying circuit 4 is connected between the drain D and

control gate 2. In operation, when a drain voltage

increases, the potential at the control gate 2 also

increases. Then, electrons are discharged from the floating

gate. As a result, a further increased feedback voltage is

supplied to the control gate 2 to cancel the erase voltage.

Thus, the final potential of the floating gate can be

controlled by controlling the feedback amount of the feedback amplifying circuit 4.

As shown in Fig. 39A, the non-volatile memory cell 1 is provided with the control gate 2 and the floating gate 3. A

comparator 5 connected with a reference voltage source 6 is connected between the drain and the control gate 2 of the

non-volatile memory cell 1. Its output terminal is

connected to the erasing voltage source 7. In operation, when the drain voltage increases to exceed a reference

voltage VR, the output from the comparator 5 is inverted to

stop the operation of the erasing voltage source 7. This

prevents the non-volatile memory cell 1 from being

excessively erased to generate a negative threshold value. As described above, the conventional non-volatile memories,

which have predetermined distributions of threshold voltages

in an initial state, require a circuit for reducing the fluctuation of the threshold voltages in write to realize

the stabilized operation, and a feedback or logic circuit

for modifying the erasing state to prevent a memory cell

from being excessively erased to generate the negative

threshold value, thus reducing the fluctuation of threshold

voltages in the initial state of the memory cell. Thus, the

conventional non-volatile memories have a more complicated

circuit configuration, and are excessively bulky because of the presence of more circuits other than the memory cells.

Further, in the conventional non-volatile memory device, when the threshold voltages in memory cells

fluctuates in an initial state, the write time is changed so

that the threshold voltages are in a predetermined range. The non-volatile memory device has a defect that it requires

a relatively long write time.

Generally, the write/erase operation for a flash EEPROM

is executed in such a manner that charges are once

previously stored in the floating gate to write "0" data and

the stored charges are erased. The flash EEPROM, therefore,

has a defect that the erasing operation is complicate. For this reason, in the flash EEPROM, the erasing

operation is performed in such a manner that charges are

once stored in the floating gate and the stored charges are extracted. Further, in order to save the write time, data

are once stored in an RAM and thereafter written in a non¬

volatile memory cell.

This requires a large scale peripheral circuit. In

order to obviate such a defect, it has been proposed to

build a DRAM (dynamic RAM) into the peripheral region of the

non-volatile memory device while preserving the write/erase

function, in which data are written in the RAM and

thereafter successively the data are written in non-volatile memory cells.

Where floating charges stored in a subsidiary bit line

have a large leak (leakage current), the potential abruptly

lowers, thereby giving insufficient precharging of the sub-

bit line. This is an obstacle in reading the stored data. Further, where data are to be erased by storing charges in the floating gate of a non-volatile memory cell, if the charges stored on the pre-charged sub-bit line are

discharged due to the leakage current, the drain voltage

(charging voltage) of the non-volatile memory cell lowers.

This may make it impossible to perform the erasing operation. If the drain voltage, which is desired to be constant, varies greatly, the write/erasing operation cannot

be efficiently carried out. SUMMARY OF THE INVENTION

The first object of the present invention is to provide

a non-volatile semiconductor memory device which can easily

perform an erasing operation. The second object of the present invention is to

provide a non-volatile semiconductor memory device which can

surely perform a write/erase operation for a floating gate

type memory cell while holding the charges stored on a bit line.

The third object of the present invention is to provide a non-volatile semiconductor memory device which can stably

perform a write/erase operation for a short time.

The fourth object of the present invention is to provide a non-volatile semiconductor memory device which can surely perform a write/erase operation and also reduce power consumption.

In accordance with the first aspect of the present

invention, there is provided a non-volatile semiconductor

memory device comprising: a plurality of word lines, a plurality of bit lines and a plurality of source lines intersecting said word lines; a plurality of memory cells,

each composed of a source, a drain, a floating gate, and a

control gate, provided at the intersections between said word lines and said bit lines a d source lines, each of the

control gates, drains and sources of said memory cells being

connected to each of said word lines, each of said bit lines

and each of said source lines, respectively; means for

charging eiter one of said source and drain of a selected

memory cell and placing it in a floating state after a

predetermined time, and means for applying a signal varying

between a positive potential and a negative potential to the

control gate of said selected memory cell whereby its

threshold voltage is converged into a predetermined voltage. Now referring to Figs. IA and IB, an explanation will

be given of the non-volatile semiconductor memory device

according to the first aspect of the non-volatile memory

device.

In Fig. IA which is a view for explaining the principle

of the present invention, a non-volatile memory cell 1 has

source/drain diffused layers in a semiconductor substrate

and first and second insulating films (tunnelling oxide layers) formed their main surfaces. The memory cell 1 has

also a first electrode (floating gate) encircled by the

first and second insulating films and a second electrode

(control gate) formed on the first insulating film. The

memory cell 1 is connected to a switch MOS transistor 8 and the drain electrode thereof is connected to a capacitor 9.

The capacitor 9 has the total Co of the parasitic

capacitance of the bit line connected to plural memory cells and the portions electrically connected to the bit line

connected to the bit lines. Examples of the portions

connected to the bit lines are a selective switch element 8,

a memory cell. Ohter transisrors or wirings may be

depending on the circuit structure. Although the selective

switching element 8 and memory cell has at least one

transistor, the parasitic capracitance of the impurity diffused layer on the side where the transistor is connected to the bit line mainlly or substantially contributes to the

parasitic capacitance CO. Longer bit lines or larger number

of non-volatile memory cells increase the parasitic

capacitance CO. Where a larger number of non-voltile memory

cells connected to the bit line, the bit line generally becomes long, thus increasing the parasitic capacitance CO.

If the parasitic capacitance CO is not so large, another

capacitor element may be supplementarily onnected to the bit

line so that an insufficient amount of parasitic capacitance

can be sufficed.

Now it is assumed that charges are injected into the

floating gate 2 so that data is written in the cell, and the floating gate 2 is sufficiently charged to a negative

potential so that the threshold value of the memory cell is

sufficiently high.

First, as shown in Fig. IB, the drain electrode of the memory cell 1 is charged to a positive potential (5 V) and

thereafter placed in a floating state.

Subsequently, a positive pulse is applied to the

control gate 2 so that the potential of the control gate 2

is positive (3 V) for a short time and thereafter a negative pulse is applied to the control gate 2 so that the potential

of the control gate is negative (-10 V) for a short time.

Thus, the potential at the floating gate 3 is slightly

changed so as to lower the drain potential. Such an

operation is repeated to decrease the charges stored in the floating gate 3, thus erasing the data stored in the memory cell.

As described above, in the non-volatile semiconductor

memory device according to the first aspect of the present

invention, the erase operation is performed as follows. A pulse wave (signal) with alternating positive and negative

potentials is applied to the control gate so that the

charges stored in the floating gate are discharged, and when the threshold value of the memory cell becomes sufficiently low, the charges in the drain are discharged into the source

through the channel so as to lower the potential at the

drain .

The potential at the drain lowers when the pulse wave

is applied to the control gate. For this reason, even when

a negative pulse is applied to the control gate, a

tunnelling current does not flow between the floating gate

and the drain so that the potential at the floating gate

does not vary further. Thus, the potential at the floating

gate can be controlled by the potential of the voltage applied to the control gate.

In accordance with the second aspect of the present

invention, there is provided a non-volatile semiconductor memory device comprising a plurality of word lines, a

plurality of bit lines, for instance, main bit lines and

subsidiary bit lines intersecting said word lines, each of

main bit lines being connected to each of said subsidiary

bit lines through a select transistor, a plurality of memory cells, each composed of a source, a drain, a floating gate

and a control gate, provided at the intersections between said word lines, and said subsidiary bit lines and source

lines, each of the control gates, drains and sources of said

memory cells being connected to each of said word lines, each of said subsidiary bit lines and each of said source

lines, respectively, means for precharging one of the

subsidiary bit lines and placing it in a floating state

after a predetermined time, means for applying a signal

composed of pulses each having a positive peak potential and

a negative peak potential through said word lines to the

control gate of said selected memory cell whereby its

threshold voltage is converted into a predetermined voltage

or range, and means for supplying a current for compensating

for a leakage current from said subsidiary bit lines to said subsidiary bit lines.

In the non-volatile semiconductor memory device

according to the second aspect of the present invention, a

signal varying between positive and negative potentials is

applied to the cotrol gate of the memory cell to extact charges stored in the floating gate so that the floating

gate volatge is converged into a predetermined voltage.

Where the precharged charges leak greatly, a current for

supplementing the leak is supplied to a subsidiary bit line

so that the charging potential on the subsidiary bit line is prevented from being lowered abruptly. Thus, the

write/erase operation is performed while the charging

potential at the subsidiary is held. 7295

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In accordance with the third aspect of the present

invention, there is provided a non-volatile semiconductor

memory device according to the second aspect in which said

signal includes pulses each varying between another positive peak potential lower than said positive peak potential and

said negative peak potential, and superposed between said

positive peak potentials, otherwise said signal includes

pulses each varying between another negative peak potential

higher than said negative peak potential and said negative

peak potential, superposed between said positive peak potentials.

Referring to Fig. 2A, a brief explanation will be given

of the operation of the non-volatile semiconductor device

according to the third aspect of the present invention. In

Fig. 2A, symbol Ts denotes a selection transistor and symbol Ml denotes a non-volatile memory transistor having a

floating gate. The drain of the memory transistor Ml is

connected to the source of the selection transistor Ts. To the junction point thereof a capacitor CO and an equivalent

resistor RO corresponding to a leakage current are

connected. A signal is applied to the control gates to extract charges so that different threshold voltages of the

non-volatile memory cells are converged into a predetermined 295

15

value .

Where there is a large leakage current, changes in the

drain voltage can be decreased by means for supplementing the current corresponding to the leakage current to detect

the threshold voltage easily. The capacitor CO may be

canceled if there is a large in-line capacitance.

With a voltage of 5 V applied to the drain of the

selection transistor Ts, a voltage of 5 V is applied to the

control gate to turn 'on' the selection transistor Ts so

that the capacitor CO is charged. Then, the selection

transistor Ts is turned 'off to place the memory transistor

Ml in a floating state. To the control gate of the memory

transistor Ml pulses as shown in Figs. 2C and 2D are

applied. The signal shown in Fig. 2C includes pulses oscillating

between positive and negative. The positive pulses A and B

have different peak values ( 3V and 2.5 V) and the negative

pulse C has a fixed peak value (- 10 V). The pulse signal

shown in Fig. 2D also includes pulses oscillating between

positive and negative potentials. As seen, the negative pulses having peak values of - 10 V and - 5 V are

alternately repeated between the positive pulses A each

having a fixed peak value. In this way, the memory transistor Ml can be set for a

predetermined voltage by the positive pulses A and power

consumption is reduced by lowering the peak values of the

pulses B between the positive pulses A. In accordance with the fourth aspect of the present

invention, there is provided a non-volatile semiconductor

memory device comprising a plurality of word lines, a plurality of subsidiary bit lines intersecting said word

lines, each of main bit lines being connected to each of

said subsidiary bit lines through a select transistor, a

plurality of memory cells, each composed of a source, a

drain, a floating gate and a control gate, provided at the

intersections between said word lines, and said subsidiary

bit lines and source lines, each of the control gates, drains and sources of said memory cells being connected to

each of said word lines, each of said subsidiary bit lines

and each of said source lines, respectively, means for

either one of said source and drain of each of said memory

cells, means for applying a signal composed of pulses each

having a positive peak potential and a negative peak potential through said word lines to the control gate of

said selected memory cell whereby its threshold voltage is

converged into a predetermined voltage, and means for supplying a minute current to the source or drain of each of

said memory cells.

In the non-volatile semiconductor memory device

according to the fourth aspect of the present invention, a

pulse signal is applied to the control gate of the memory

transistor (cell) through a word line to execute an

erase/write operation. With the means of supplying a very

minute current corresponding to a leakage current provided

to a main bit line or a sub bit line, a minute current is supplied to a predetermined bit line in accordance with the

operation of a column decoder circuit during an erase or

write operation. Thus, the threshold values of a large

number of memory cells can be controlled to a predetermined

value simultaneously and precisely.

Incidentally, the "signal" to be applied to the control gate of the memory cell in the present invention can be

defined as a signal which can vary between a positive potential and a negative potential and may be any signal

which can attain the operation intended by the present

invention.

The above and other objects and features of the present

invention will be more apparent from the following

description taken in conjunction with the accompanying drawings .

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. IA is a theoretical circuit diagram of the non-

volatile semiconductor memory (cell) according to the first aspect of the present invention;

Fig. IB is a waveform chart for showing the operation

of the memory shown in Fig. IA;

Figs. 2A is a theoretical circuit diagram of the non-

volatile semiconductor memory (cell) according to the second aspect of the present invention;

Fig. 2B is a waveform chart for showing the operation

of the memory shown in Fig. 2A;

Figs. 2C and 2D are waveform charts of pulses applied to the gate of the memory shown in Fig. 2A during its erase/write operation;

Fig. 3 is a circuit diagram of a non-volatile

semiconductor memory device according to the first aspect of

the present invention;

Fig. 4A is waveform chart of pulses applied to a word

line of the memory device shown in Fig. 3;

Fig. 4B is a view showing the potential at the floating gate in the memory device shown in Fig. 3; Fig. 4C is a view showing the potential at a bit line

in the memory device shown in Fig. 3;

Fig. 5A is waveform chart of pulses applied to a word

line of the memory device shown in Fig. 3;

Fig. 5B is a view showing the potential at the floating

gate in the memory device shown in Fig. 3;

Fig. 5C is a view showing the potential at a bit line

in the memory device shown in Fig. 3;

Fig. 6 is a circuit diagram of another non-volatile semiconductor memory device according to the first aspect of

the present invention;

Fig. 7 is a circuit diagram of a non-volatile

semiconductor memory device according to the second aspect

of the present invention;

Figs. 8A and 8B are waveform charts of an input pulse applied to a level shifter and an output pulse thereof;

Figs. 9A and 9B are an equivalent circuit diagram

showing the main part of the memory shown in Fig. 7 and a

waveform chart showing the voltage applied to it,

respectively;

Fig. 10 is a circuit diagram of another non-volatile

semiconductor memory device according to the second aspect

of the present invention; Figs. 11A and 11B are waveform charts of input pulses

applied to a level shifter and Fig. 11C is an output pulse

thereof;

Figs. 12A, 12B and 12C are waveform charts of a floating gate voltage, a bit line voltage and a control gate

voltage in the memory device shown in Fig. 10, respectively;

Fig. 13A is a circuit diagram of still another non¬

volatile semiconductor memory device according to the second aspect of the present invention; Figs. 13B and 13C are an equivalent circuit diagram showing the main part of the memory shown in Fig. 13A and a

waveform chart showing the voltage applied to it, respectively;

Fig. 14A is a circuit diagram of a further non-volatile semiconductor memory device according to the second aspect of the present invention;

Figs. 14B and 14C are an equivalent circuit diagram

showing the main part of the memory shown in Fig. 14A and a

waveform chart showing the voltage applied to it,

respectively;

Figs. 15A, 15B and 15C are waveform charts of a

floating gate voltage, a bit line voltage and a control gate

voltage in the memory device shown in Fig. 14A, respectively;

Fig. 16 is a sectional view showing another example of

current supply means;

Fig. 17A is a circuit diagram of an embodiment of the

non-volatile memory according to the third aspect of the

present invention;

Fig. 17B is a waveform chart of pulses applied to the

control gate during an erase/write operation;

Fig. 18 is a circuit diagram of another embodiment of

the non-volatile memory according to the third aspect of the

present invention;

Figs. 19A, 19B and 19C are waveform charts of a floating gate voltage, a bit line voltage and a control gate

voltage in the memory device shown in Fig. 18, respectively; Fig. 20 is a circuit diagram of still another embodiment of the non-volatile memory device according to

the third aspect of the present invention;

Fig. 21A is an equivalent circuit diagram of the embodiment of Fig. 20;

Fig. 21B is a waveform chart showing the operation

timings of a switch;

Fig. 21C is a waveform chart showing a composed pulse;

Fig. 22A is another equivalent circuit diagram of the 7295

22

embodiment of Fig. 20;

Fig. 22B is a waveform chart showing the operation

timings of a switch;

Fig. 22C is a waveform chart showing a composed pulse; Fig. 23A is a circuit diagram showing a further

embodiment of the non-volatile semiconductor memory device

according to the third aspect of the present invention;

Fig. 23B is a table for explaining an erasing operation; Fig. 24 is a circuit diagram of a non-volatile semiconductor memory device according to the fourth aspect

of the present invention;

Fig. 25 is a circuit diagram of another non-volatile

semiconductor memory device according to the fourth aspect

of the present invention;

Fig. 26 is a circuit diagram of another non-volatile

semiconductor memory device according to the fourth aspect

of the present invention;

Fig. 27 is a circuit diagram showing an embodiment in

which a minute current source circuit is a charging pump

circuit;

Fig. 28 is a circuit diagram of another example of the

charging pump; Figs. 29A to 29E are waveform charts of operation

waveforms based on the charging pump shown in Fig. 29;

Fig. 30 is a circuit diagram showing an embodiment in

which a minute current source circuit is a switched

capacitor circuit;

Figs. 31A to 31C are circuit diagrams of operation

waveforms based on the switched capacitor circuit shown in Fig. 30;

Fig. 32 is a circuit diagram of another example of the

switched capacitor;

Figs. 33A to 33D are waveform charts of operation

waveforms based on the switched capacitor shown in Fig. 32;

Figs. 34 to 37 are circuit diagrams of further embodiments of the non-volatile semiconductor memory device

according to the fourth aspect of the present invention;

Figs. 38A and 38B are graphs each showing the

distribution of the threshold voltages of an ordinary flash EEPROM;

Fig. 38C is a graph showing the distribution of the

threshold voltages of an ordinary NAND type EEPROM;

Fig. 38D is a graph showing the distribution of the

threshold voltages of an UVEPROM;

Figs. 39A and 39B are circuit diagrams showing the erasing method in the conventional non-volatile

semiconductor memory;

Figs. 40A and 40B are an equivalent circuit diagram of

the non-volatile semiconductor memory and a waveform chart for explaining its operation, respectively;

Fig. 41A is a circuit diagram of an example of a pulse

generating circuit, and Figs. 41B and 41C are waveform

charts for explaining its operation;

Figs. 42A to 42C are waveform charts for explaining the

operation of a non-volatile semiconductor device; and

Figs. 43A to 43C are waveforms for explaining the problem to be solved by the present invention.

Figs. 44 and 45 are graphs showing the effects of

adjustment of the threshold values according to the present

invention; and

Fig. 46 is a block diagram of the basic structure of

the memory to which the "AC pulse method" is to be applied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Method of the threshold voltages of non-volatile memory

cells.

First, a detailed explanation will be given of the

method of unifying the threshold voltages of floating-gate type non-volatile memory cells Ml - Mn. 7295

25

In this explanation, the transistors constituting

memory cells Ml - Mn are referred to as "memory

transistors". For easy understanding, a more concrete

explanation will be given. But the present invention should

not be limited to the concrete explanation. The electrode

of a memory transistor on the side where a storage node N

(junction point of a transistor and a capacitor in Fig. IA)

is located is referred to as a drain electrode whereas the

electrode of the memory transistor on the opposite side is

referred to as a source electrode. The above definition of the source electrode and drain electrode is only for

convenience of explanation. In some cases, in accordance

with the operation mode of an actual non-volatile memory

device, the electrode of the memory transistor where the

storage node is located is preferably defined as a source electrode. For example, in a well-known virtual ground line

system, the bit line to which the drain electrodes of the memory transistors are commonly connected and the source

line to which the source electrodes thereof are commonly connected are alternately switched a ground potential. The present invention also includes such a mode.

Further, in a certain structure of a memory cell and

application condition of a voltage (distribution of an 7295

26

electric field strength), a tunnelling current may flow

between the floating gate and channel of the memory

transistor. In the following explanation, however,

considering the fact that the electrons extracted from the floating gate are finally shifted to the drain electrode in

order to place the drain electrode in a relatively high

voltages, it is assumed that the tunnelling current flows

between the floating gate and drain electrode irrespectively

of the memory structure and electric field distribution. Fig. IB is a timing chart for explaining the method of adjusting the threshold value of a non-volatile memory cell according to the present invention. In this adjusting method, an AC voltage having a certain amplitude, e.g., an

AC voltage or AC pulse signal oscillating between positive

and negative potentials is applied by a limited number of times to the control gate of the memory cell.

In this method, the drain of the memory transistor is

previously maintained at a higher potential than that at the

source electrode. In order to maintain the drain electrode

at a high potential, the drain electrode and the parasitic capacitance of a bit line connected to the drain electrode

are preferably used as a capacitor element for charge storage, or otherwise a specific capacitor element may be 295

connected to the drain electrode so that charges are stored

in the capacitor element.

Next, the AC pulse signal oscillating between positive

and negative potentials is applied to the control gate.

When a positive voltage is applied to the control gate, a

memory transistor having a threshold value lower than a

certain value defined in relation to the applied voltage or

a range in its neighborhood (hereinafter referred to as an expected value) turns on. Then, charges shift from the

drain electrode of the non-volatile memory cell to its source electrode. As a result, the drain voltage lowers

sufficiently so that subsequent application of a negative

voltage does not permit the tunnelling current to flow.

Namely, the extraction of electrons from the floating gate

ceases so that the threshold value of the non-volatile memory cell does not vary thereafter.

On the other hand, when a negative voltage is applied

to the control gate, the charges stored in the memory

transistor are extracted to the drain electrode, and the

threshold voltage of the non-volatile memory cell falls by the extracted amount. When the positive voltage is

successively applied to the control gate, the memory

transistor having a lower threshold value than the expected value turns on so that the charges shift from the drain

electrode to the source electrode. As a result, the drain

voltage falls sufficiently so that subsequent application of

a negative voltage does not permit the extraction of

electrons from the floating gate. Accordingly, the

threshold value of the non-volatile memory cell does not

vary thereafter.

When the above operation is repeated, the threshold values of all the non-volatile memory cells will be

converged into the expected value. Further, if the number of times of repeating the above operation is small,

threshold values of the non-volatile memory cells will not

be strictly converged into a predetermined value, but may have a desired range. In this case also, it is apparent

that the threshold value of the non-volatile memory cell has been suitably adjusted. Whether the threshold value has

been strictly converged into a fixed value or a desired

range means only the degree of convergence.

Although apparent from the principle of the above

method, the waveform of the AC pulse signal applied to the control gate of the non-volatile memory cell should not be

limited. The waveform may be a rectangular wave, sinusoidal

wave, triangle wave, etc. A further concrete explanation will follow. Now it is

assumed that 10 (ten) pulses of the AC pulse signal

oscillating e.g. between 3 V and 10 V are applied to the

control gate of the non-volatile memory cell.

First, 5 V is applied to the drain electrode of a

selected transistor Trl and 5 V is also applied to the gate

electrode thereof so that the selected transistor turns on.

Then, the capacitor element constituted by a bit line BL and

the parasitic capacitance of the portion electrically

connected to the bit line is charged. This charging operation enhances the drain potential of the memory

transistor of a certain non-volatile memory Mk. Thereafter, with the selected transistor Trl turned off (gate voltage =

0 V) , the AC pulse voltage is applied to the control gate of the memory transistor relative to the non-volatile memory cell Mk. When a positive voltage of 3 V is applied to the

control gate of the memory transistor, the memory transistor

having a threshold value lower than the expected value turns

on. Then, a channel current flows from the drain electrode

to the source electrode. This means reduction of the drain voltage of the memory transistor due to discharging of

charges stored in the capacitor element. In such a memory

transistor, subsequent application of the negative voltage does not permit the tunnelling current to flow.

Next, when a negative voltage of - 10 V is applied to

the control gate of the memory transistor, the potential of

the floating gate becomes negative, normally about half as

large as the potential of the control gate. Then, a small

amount of electrons are extracted from the floating gate to

the drain electrode. The corresponding tunnelling current

flows between the floating gate and drain electrode. As a result, the threshold voltage is lowered by the value

corresponding to the electrons extracted from the floating gate. When a positive voltage of 3 V is successively

applied to the control gate of the memory transistor, the

memory transistor having the threshold value lower than the expected value turns on. As a result, the drain voltage of

the memory transistor lowers owing to discharging of the charges stored in the capacitor element. Thereafter, the

application of the AC pulse signal is repeated. Thus, the

threshold values of all the non-volatile memory cells are adjusted so as to be converged into the expected value.

Figs. 42A to 42C show the secular changes in the

floating gate potential V.. (Fig. 42A) and in the bit line

potential V,. (Fig. 42B) when a pulsative control gate

voltage V_cc (Fig. 42C) is applied to the control gate of a o l

floating gate type memory transistor.

The control gate voltage V.. shown in Fig. 42C is an AC

voltage of continuous combination of plural pulses ((1),

(2), ... (6), ...) oscillating between 5 V and - 10 V. As

shown in (a), (b) and (c) in Fig. 42A, the different

floating gate potentials V.. of - 6 V, - 4 V and 2 V in an

initial state are converged into a predetermined potential

(about - 2 V) after about 100 μsec. Since the threshold

value of the memory cell can be regarded about half as large

as the absolute value of the floating gate potential V_fC , it can be understood that the application of the AC voltage to

the control gate converges the distributed threshold values

of 12 V, 8 V and 4 V into about 4 V. Then, as shown by (c)

in Fig. 42B, in the memory cell having a relatively low

threshold value, immediately after the first pulse ((1) in Fig. 42C) is applied, the bit line potential V_B1 abruptly

falls and then gradually approaches a fixed value. On the

other hand, as shown by (a) and (b) in Fig. 42B, in the memory cell having a relatively high threshold value, the

bit line potential V_B1 does not fall until the fourth pulse

((4) in Fig. 42C) is applied. The bit line potential V_n of

the memory cell having a higher threshold value abruptly

falls at a later time. In any way, however, the respective bit line potentials approach fixed values. Thus, it can be

understood from Figs. 42A to 42C that when the AC voltage is

applied to the control gate of the floating-gate type memory transistor, the threshold values of its memory cell can be

adjusted.

Such an effect is more clearly shown in Figs. 44 and

45. In these figures, the abscissa represents the initial

threshold voltage in a memory cell and the ordinate represents the threshold voltage converged when the AC

voltage composed of ten pulses is applied. The pulse constituting the AC voltage in Fig. 44 is a square wave oscillating between 4 V, 3 V or 2 V (duration of 15 μsec)

and - 10 V (duration of 10 μsec). The pulse constituting

the AC voltage in Fig. 45 is a square wave oscillating

between 3 V (duration of 15 μsec) and - 13 V, - 10 V or - 5 V (duration of 10 μsec). As seen from these figures, the converged value or range can be expected from the initial

threshold value and a parameter of the AC voltage applied to

the control gate. Further, it can be understood that (1)

where the initial threshold value (VthO) is 4 V or more, the

estimated value is substantially fixed irrespectively of the

initial threshold voltage; (2) where the initial threshold

value of the memory cell is larger than the positive peak 7295

33

voltage of the AC voltage applied to the control gate, the

estimated value is substantially fixed irrespectively of the

initial threshold value; (3) the negative peak voltage of

the AC voltage applied to the control gate is lower than -

10 V, the expected value is substantially fixed

irrespectively of the initial threshold value; and (4) where

the initial threshold value (VthO) is not smaller than 4 V

and the positive voltage applied to the control gate is V+,

the threshold value after convergence is 0.7+ to 0.8+ ( if VthO = 2 V, about 0.70 V+; if VthO = 3 V, about 0.73 V+; and Vth = 4 V, about 0.80 V+) .

The above method of adjusting the threshold value

serves to reduce the threshold value of the memory cell by

application of a lower voltage (negative potential in the case of the AC voltage oscillating between a positive

potential and a negative potential) and verify and select the threshold value of the memory cell by application of a

higher voltage (positive potential in the case of the AC

voltage oscillating between a positive potential and a

negative potential). The verifying of the threshold value

of the memory cell means to compare the actual threshold value of a memory cell as an object with the expected value

which is the converged value or range determined in relation 7295

to the higher voltage. The selection of the memory cell is

to discriminate whether the memory cell at issue is a memory

cell having the threshold value lower than the expected value. When the memory cell is selected on the basis of the higher voltage, in the memory cell having the threshold

value lower than the expected value, the drain voltage of

the memory transistor of the memory cell falls so that

subsequent application of the lower voltage does not provide

the tunnelling current. Therefore, such a memory cell will

not be served for the verification of the threshold value of

the memory cell. On the other hand, in the memory cell

still having the threshold value lower than the expected

value, application of the lower voltage provides the

tunnelling current so that such a memory will be served for the verification of its threshold value and subsequent

selection thereof.

In this case, the estimated value into which the

threshold value of the memory cell is to be converged can be

determined optionally. Since application of the lower

voltage for a shorter time can make small the tunnelling current flowing for the time, i.e. extract electrons from

the floating gate by a smaller degree, the precision of

convergence of the threshold value of the memory cell into 295

35

the expected value can be enhanced. On the other hand,

application of the higher voltage for a short time results

in start of the application of low voltage before the

termination of the reduction of the drain voltage, and hence

does not permit the convergence of the threshold value of

the memory cell to be suitably controlled. For this reason,

as long as no hindrance occurs for the operation speed of

the non-volatile memory device itself, the higher voltage is

preferably applied for a longer time.

In the case of the AC voltage varying between positive

and negative voltages, the absolute value of the positive

voltage is preferably smaller than that of the negative

voltage. Although depending on the distribution in the

electric field strength in a gate oxide film, assuming that the possibility of injection of electrons when the positive

voltage is applied to the control gate is approximately

equal to that of extraction of electrons from the floating

gate when the negative voltage is applied to the control

gate, when the absolute value of the positive voltage is larger than that of the negative voltage, the degree of

injection of electrons into the floating gate exceeds that

of extraction of electrons from the floating gate so that

the threshold value of the memory cell may result. Although 7295

36

there is a condition permitting the injection of electrons

into the floating gate to be disregarded, the method of

adjusting the threshold value is sufficiently effective as

long as the effect of application of the positive voltage

influencing changes in the threshold value of the memory

cell is lower than that of the lower voltage.

The voltage to be applied to the control gate of the

memory transistor is preferably sufficiently lower than the

drain voltage of the memory transistor. The application of

the lower voltage extracts the electrons from the floating gate. When the drain voltage gradually falls during the

application of the AC voltage, correspondingly, it becomes difficult to extract the electrons from the floating gate.

In order to obviate such an inconvenience, the' lower voltage to be applied to the control gate is made much lower than

the drain voltage of the memory transistor so that the

electrons are easily extracted and the tunnelling current easily flows. Therefore, the amplitude of the lower voltage

to be applied to the control gate is preferably vary in

accordance with a change in the drain voltage.

In the above method of adjusting the threshold value,

it is preferable that the higher voltage (positive voltage

in the AC voltage varying between the positive voltage and 7295

3 7

negative voltage) is applied precedingly to the lower

voltage (negative voltage in the above AC voltage). The

reason is as follows. In the case where the memory cell at

issue is an EPROM, if the negative voltage is applied

precedingly, the threshold value of the memory cell having the sufficiently low threshold value will be further reduced

so that the memory cell will be placed in a kind of

excessive erasure state. Thus, the source and drain

electrodes will be short-circuited so that the drain voltage

cannot be applied. This leads to difficulties such as poor reading of the data and impossibility of charging of the bit line,

However, the lower voltage may be applied precedingly.

For example, if the lower voltage is not a low voltage of -

10 V, but a relatively high voltage of - 1 V, in many cases,

the above problem of excess erasure will not occur.

Therefore, the lower voltage may be applied initially. In this case, for example, after - 1 V is initially applied and

then - 3 V is applied, e.g. - 10 V which is much lower than

the drain voltage of the memory transistor is preferably

applied so that the tunnelling current can easily flow.

It can be understood that the above method of adjusting the threshold value is a new method of reducing the 295

38

threshold value of the floating gate type non-volatile

memory cell to converge it into a desired value or range,

and also a new method of erasing (or write in another

definition) the floating gate type non-volatile memory cell.

As the case may be, in the following explanation for the

embodiments of the present invention, this method will be

referred to "AC pulse method" for convenience of explanation.

Explanation of the basic structure of a memory to which the

AC pulse method is to be applied.

Now referring to Fig. 46, an explanation will be given

of the basic structure of a non-volatile memory device to

which the above AC pulse method is to be applied.

In Fig. 46, reference numeral 1 denotes a memory array;

2 (21 - 24) selection circuits represented by multiplexers; 3 a voltage source; 4 an AC voltage generating circuit; 5 a

voltage detection circuit; 6 other peripheral circuits; and 7 a control circuit. Symbol Wi or WLi denotes a word line;

Sj a source line; Bk or BLk a bit line; Stk a gate selection

line; SL1 a source selection circuit; and Trk a selection transistor. Suffixes i, j, k and 1 are integers

corresponding to the number of word lines and source lines

and of selection transistors. 7295

39

The memory array 1 is composed of a plurality of non¬

volatile memory cells Ml to Mn regularly arranged. Any non¬

volatile memory cell Mk which includes a transistor having a

control gate and a floating gate (hereinafter referred to as

"memory transistor" is located at the crossing point of a

word line Wi and a bit line Bk. The gate electrode, drain

electrode and source electrode of the memory transistor are

connected to the word line Wi , bit line Bk and source line

Sj . The selection circuit 2 selects the word line, bit line

and source line corresponding to a specific address by a control signal from the control circuit 7. In this meaning,

the selection circuit 2 can be regarded as incorporating an

address decoder. The selection circuit 21 applies a voltage

to only a specific bit line to be selected, thereby

contributing energy saving. The selection circuit 22 selects a specific gate selection line to permit the on-off

operation of the selected transistor corresponding to the

gate selection line. These selection circuits 21 and 22

permit charging of the bit line necessary for the AC pulse

method or a capacitor element supplementarily added. The selection circuits 23 and 24 select a specific word line and

a specific source line. The AC voltage generating circuit 4

supplies a predetermined AC pulse signal to the selected word line through the selection circuit 23. The circuit 4

may be a circuit capable of generating a DC voltage signal

that is a selection signal for selecting a word line, i.e. a

word line driving circuit, or a portion thereof. The voltage

detection circuit 5 serves to detect the reduced potential

at the bit line while and after the AC pulse method is

applied. The circuit 5 may be used as a sense circuit for

reading memory information. The peripheral circuit 6 which is not necessarily required for the AC pulse method is

illustrated generally.

The control circuit 7 generally controls the selection

circuits 2 (21 - 24), voltage source 3, AC voltage

generating circuit 4 and peripheral circuits 6. Namely, the

control circuit 7 performs all the control operations

inclusive of the control of the operating timings of each circuit which is required for the operation of the AC pulse

method. Entity or part of the control circuit 7 may be

formed on a chip on which the memory array 1 is arranged,

otherwise control signals may be supplied externally from

the chip to perform the AC pulse method. Examples of the control operation effected by the control circuit 7 for the

operation of the AC pulse method are as follows.

1 The selection circuit 2 is controlled to (1) select a specific memory cell, a specific bit line or a

specific word line, or select plural memory cells, word

lines or bit lines simultaneously; and

(2) set the source potential, drain potential and substrate

potential of the selected memory cell(s) at a predetermined

value. Thus, the potential of the selected bit line is

relatively enhanced so that the subsequent floating state

can be maintained and a potential condition can be set to

permit the tunnelling current or channel current to flow

easily in the memory transistor.

2. The AC voltage circuit 4 is controlled. Thus,

(1) a predetermined AC pulse signal can be set. The pulse

width, kind, number, peak value, waveform, etc. of pulses constituting an AC voltage can be set optionally. Further,

it can be decided whether a positive voltage or negative voltage should be applied. Particularly, for example, the

control circuit 7 can increase the absolute value of the

absolute value of the peak value of the negative voltage on

the basis of the signal from the voltage detection circuit 5

which has detected that the potential at the specific word line has been reduced. Likewise, the control circuit 7 can

change the pulse width or kind of the pulses constituting

the AC pulse signal on the basis of the signal from the 7295

42

voltage detection circuit 5.

(2) A predetermined AC pulse signal can be applied to a

specific word line through the selection circuit 2.

(3) The application of the AC pulse signal to a specific word line by the AC voltage generating circuit 4 can be

stopped. Particularly, on the basis of the voltage

detection circuit which has detected that the potential at a

specific word line has been sufficiently reduced, the control circuit 7 stops the application of the AC voltage to the word line. This contributes to energy saving.

3. The voltage source 3 is controlled to enable the on-off

control of the voltage source which is necessary for the

operation of a switched capacitor.

In the respective embodiments which will be hereinafter explained, the basic structure of the non-volatile memory device as shown in Fig. 46 is basically common except for

the case particularly noted. Therefore, in each embodiment, the main part of the memory array 1 has only to be

explained.

Aspect I

Now referring to Fig. 3, an explanation will be given

of the non-volatile semiconductor memory device according

to the the first aspect of the present invention. In Fig. 3 non-volatile memory cells are arranged in a matrix shape to

form a non-volatile semiconductor memory device. Each of

memory cells Mil, M12, M21 and M22, ..., is composed of

source/drain diffused layers formed in a semiconductor

substrate, a floating gate covered with a gate oxide film

about 100 A and an ONO (silicon oxide film - silicon nitride

film - silicon oxide film) formed between the source drain

layers and a control gate formed on the floating gate.

The control gates of the memory cells Mil, M12 are

connected to a word line WI and those of the memory cells

M21, M22 are connected to a word line W2. A bit line Bl is

connected to the one electrodes of the memory cells Mil,

M21, ... and to the source of a select transistor Trl, and a

bit line B2 is connected to the one electrodes of the memory

cells M12, M22, ... and to the source of a select transistor Tr2. The junction points of the memory cells Mil and M12

and the memory cells M12 and M22 which are commonly

connected to the source of a select transistor Tr3 through a

source line SI. The drains of the select transistors Trl

and Tr2 are connected to pull-up circuits 10 (not shown), respectively. The gates of these select transistors are

connected to gate select lines ST1 and ST2 , respectively. A

capacitor Cl is connected between the bit line Bl and the source line SI and a capacitor C2 is connected between the

bit line source line SI and the bit line B2. The capacitors

Cl and C2 may be connected through a transistor.

Although not being limited, in each memory cell, the

floating gate which is formed between the gate oxide film

has a size of 3 μm x 1 μm, and a channel region and a part

of the source/drain diffused layers. The channel region has

a size of 1 μm x 1 μm. In order to adopt the AC pulse method, the capacitances of the capacitor elements 9 and CO must be determined under the following conditions.

(1) (capacitance of the floating gate in a memory cell) <<

(capacitance between a bit line and a source line)

(2) (time constant determined by the leakage current of the

bit line in a floating state and the capacitance of the bit

line) >> (width of a pulse applied to a word line)

Further, where the AC pulse method in which an AC

voltage is applied to the control gate of the memory

transistor is adopted, it is desired that the potential at

the bit line while the AC voltage is applied falls within 5

%.

Empirically, it has been found that the capitances of

the capacitor elements 9 and CO which satisfy the above

conditions (1) and (2) are about 100 to 300 fF. 7295

45

If the parasitic capacitance generated in the bit line and

the portion electrically connected thereto is larger than

the capacitance of Cl and C2 , auxiliary capacitor elements

Cl and C2 can be omitted. Now referring to the waveform charts of Figs. 4A to 4C,

an explanation will be given of the erasing method for the

memory device described above.

First, an explanation will be given of the case where

the memory cells has a high threshold voltage of 7 V or more.

It is assumed that the bit line Bl is at the potential

of 5V, the bit line B2 is at the ground potential and the source line SI is also at the ground potential.

The select transistors Trl and Tr2 are turned off to

place the bit lines Bl and B2 in a floating state. Then, the capacitors Cl and C2 are placed in a charged state.

Subsequently, with the word line W2 with its potential

reduced to ground, a pulse wave (signal) as shown in Fig. 4A is applied to the word line WI and the control gates of the memory cells Mil and M12. The potential at the floating gates connected to the word line WI , as shown in Fig. 4B, is

gradually lowered when a negative potential is applied to

the control gates. As shown in Fig. 4C, the voltage at the 295

46

drain connected to the bit line Bl is lowered when a

positive potential is applied to the control gates with a

predetermined threshold potential at the floating gates.

The pulse wave applied to the control gates through the bit line has a first pulse having a positive peak potential

of 3V and a pulse width of 20 μs and a subsequent pulse

having a negative peak potential of - 10 V and a pulse width

of 10 μs. These positive and negative pulses are applied to

the control gates alternately and repeatedly thereby to

lower the potentials at the floating gate and drain electrode. In this case, the absolute value of the positive

potential is preferably required to be smaller than that of the negative potential. Further, it is preferably required

that after the pulse with the positive potential is applied,

the pulse with the negative potential is applied.

Incidentally, the pulse signal is supplied from a pulse

generating circuit 12 through a switch 13.

In the above operation, when the negative pulse is

applied to the word line WI connected to the control gate of

the memory cell Mil, a tunnelling current flows between the floating gate and drain diffused layer. Aa a result, the

charges stored in the floating gate are decreased. When the

threshold value is gradually lowered, a channel current starts to flow between the source and drain. Because of

this channel current, the drain voltage is reduced and

eventually the tunnelling current will not flow between the

floating gate and drain. Thus, the memory cell Mil comes to

have tha conveged threshold voltage.

On the other hand, in the memory cell M12, because the

bit line B2 is at the ground potential, no tunnelling

current flows between the floating gate and the drain (or

source) thereof so that the threshold voltage of the memory

cell M12 is maintained at a high voltage.

In the memory cells M21 and M22, because the word line

W2 is at the ground potential, the potential at their

floating gates does not vary and so their threshold voltage does not vary.

Next, an explanation will be given of the case where the memory cells has a low threshold voltage of 2 V.

In the same manner as in the case where the threshold

voltage is high, signals are applied to the bit lines, source line, word lines and select transistors.

It is assumed that the bit line Bl is at the potential

of 5V, the bit line B2 is at the ground potential and the

source line SI is also at the ground potential.

The select transistors Trl and Tr2 are turned off to place the bit lines Bl and B2 in a floating state. Then, the capacitors Cl and C2 are placed in a charged state.

Subsequently, with the word line W2 with its potential

reduced to ground, a pulse wave (signal) as shown in Fig. 5A

is applied to the word line WI , i.e. the control gates of the memory cells Mil and M12.

In the above operation, when the positive pulse is

applied to the word line WI connected to the control gate of

the memory cell Mil, a channel current flows between its

source and drain so that the drain voltage is lowered. As a result, even when the subsequent negative pulse is applied,

the tunnelling current does not flow between the floating gate and the drain. In this way, since the positive pulse

is first applied, charges are not further extracted from the

floating gate with the threshold value already reduced. Thus, excess erase does not occur. Therefore, the write

operation before erasing which has been carried out is not

required. In order to lower the drain voltage sufficiently, it is desired that the positive duration of the pulse is

increased.

On the other hand, in the memory cell M12, because the

bit line B2 is at the ground potential, no tunnelling

current flows between the floating gate and the drain (or 7295

49

source) thereof so that the threshold voltage of the memory

cell M12 is maintained at a high voltage.

In the memory cells M21 and M22, because the word line

W2 is at the ground potential, the potential at their

floating gates does not vary and so their threshold voltage

does not vary.

Further, if the erase operation is completed when all

the potentials at the bit lines relative to the word line WI

have been lowered, parallel erase operation can be carried

out for a large number of memory cells, gates of which are

connected to the word line WI . Since the erase operation is completed within ten periods, if at most 128 or so memory

cells are connected in parallel, the time required for the

erasing^" can be shortened in total.

The potential at the bit line is gradually reduced with time by the source current. If the pulse having a width in consideration of such a reduction is applied to the word

line, th-≤ erase operation can be realized in a more stabilized manner at a higher speed. A more narrow pulse

width permits the accuracy of control to be enhanced.

The non-volatile semiconductor memory device according to the .first aspect of the present invention should not be limited to the memory as shown in Fig. 3. The same erasing 7295

method as described above can be applied to the non-volatile

semiconductor memory device as shown in Fig. 6.

In the memory device shown in Fig. 6, word lines WI to

W4 are made orthogonal to the channels of select transistors Trl and Tr2 , and the source lines SI to S3 of memory cells

Mil, M12; M21, M22; M31, M32 and M41 and M42 are connected

to a wide area source line Si.

Further, since the erase operation can be controlled

for the threshold voltages of a large number of memory cells

connected to a common word line, assuming that the memory cell has the size described above, the number of memory

cells which can be arranged in parallel can be enhanced from

only 64 to 1000 or so and also the time required for the

erasing can be greatly shortened. The non-volatile semiconductor memory device according to the first aspect of the present invention intends to

apply a pulse wave (signal) to the control gate of a non¬

volatile memory cell so as to erase the charges stored in

the floating gate, thereby placing the memory cell in an

initial state. Therefore, the erasing method is simple.

Also, the write operation before erase which has been conventionally executed is not required so that the erasing

time can be greatly shortened. It is possible to perform simultaneously the erase

operation for a large number of memory cells connected to a

common word line in parallel. By controlling the pulse

width of a pulse wave (signal) applied to the control gate,

the threshold voltage of the memory cell can be precisely

set. This makes it unnecessary to use any specific feedback

circuit or logic circuit for preventing the false operation

due to the fluctuation in the threshold voltages of the non¬

volatile memory cells. For this reason, with the same

storage amount, a more compact non-volatile memory

semiconductor memory device than before can be provided.

The production cost can also be reduced.

It is needless to say that the operation similar to

that described above can shorten the processing time for write.

Aspect II

An explanation will be given of a non-volatile

semiconductor memory device according to the second aspect

of the present invention.

Fig. 7 is a circuit diagram of one embodiment of the non-volatile semiconductor memory device according to the second aspect of the present invention.

As shown in Fig. 7, the non-volatile semiconductor memory device includes an array 21 composed of non-volatile

memory cells, a level shifter circuit 22, threshold voltage

detector circuits 24 for detecting the threshold voltages of the non-volatile memory cells, switches 3, row/column

decoder circuits (not shown), and a sense amplifier (not

shown) .

In the memory cell array 21, the drain of a select

transistor Tsal is connected to a main bit line BLal , and the source of the select transistor Tsal is connected to a subsidiary bit line BLsal . The drains of memory elements Mai and Ma2 are connected to the subsidiary bit line Blsal

and the sources thereof commonly connected are connected to

the drain of a source side select transistor Trsl through a source line. A source side select line SL1 is connected to the control gate of the source side select transistor Trsl. A capacitor Cal is connected between the source and drain of

each of the memory elements Mai and Ma2.

On the other hand, the drain of a select transistor

Tsbl is connected to a main bit line BLbl and the source thereof is connected to a sub-bit line BLsbl . A capacitor

Cbl is connected to the source and drain of each of the

memory cells Mbl and Mb2.

A word line WI is connected to the control gates of the memory elements Mai and Ma2. A word line W2 is connected to

the control gates of the memory cells Ma2 and Mb2. A block

lal , which is composed of the select transistor Tsal,

capacitor Cal and memory elements Mai, Ma2 connected as

described above, is connected to the main bit line Blal . A

block lbl, which is composed of the select transistor Tsbl,

capacitor Cbl and memory elements Mbl and Mb2 as described

above, is connected to the main bit line Blbl.

The word lines WI , W2 ... , which are commonly connected

are connected to the level shifter circuit 2 through the

switch 3. The switch 3 may be a multiplexer. In this case,

each block is connected to the level shifter circuit 2

through the multiplexer.

The subsidiary bit line Blsal is connected to the threshold voltage detector circuit 4 through the switch 5, and the sub-lit line Blsbl is also connected to the

threshold voltage detector 4 through the switch 5.

The threshold voltage detector 4 may be a CMOS inverter

composed of transistors (MOSFETs) T6 and T7.

The level shifter circuit 22 includes a CMOS inverter composed of transistors (MOSFETs) T2 and T3 , a transistor

(MOSFET) T4 with its input always set for "ON" and a

transistor (MOSFET) T5 for positive-feedback of the output from the CMOS inverter to its input.

In operation, an input pulse wave having a peak value

of 5V as shown in Fig. 8A is applied to the input stage of

the level shifter 22. An output pulse wave varying between positive (3 V) and negative (- 10 V) potentials is outputted

from the output stage of the level shifter 22.

Specifically, a pulse signal having an "H" (high) level (5

V) and an "L" (low) level (0 V) is supplied at a

predetermined period. The "L" level input leads to the "L"

level output (- 10 V) which will be applied to the word lines WI and W2. The "H" level input leads to the "H" level output (3 V) which will be applied to the word lines WI and W2.

In the threshold detector circuit 24 , the voltage

source Vdd applied to the source of the transistor T7 is set for the voltage twice as large as the floating gate voltage of each of the memory cells Mai, Ma2 , ... during erasing.

Each of the blocks lal, lbl, ... constitutes a DRAM

cell basically composed of a capacitor and a transistor

connected thereto in series. For example, the block lal

substatially constitutes a DRAM cell composed of the select

transistor Tsal using the select gate line ST1 as a word

line and the capacitor Co comprising the supplementary capacitor Cal and the parasitic capacitane of the sub-bit

line BLsal, the non-voltatile memory elements Mai, Ma2 , ...,

etc.

Write/erase or refresh operations are made for the DRAM

in an ordinary manner. The data once stored in the DRAM are

transferred to predetermined memory elements or cells on a

non-volatile semiconductor memory device.

Incidentally, if the parasitic capacitance based on the

subsidiary bit line BLsal and non-volatile memory elements is relatively small, provision of the capacitor Cal is necessarily required. Though the parasitic capacitance,

which has become smaller with miniaturization of memory

elements, the capacitor Cal may be omitted, where the

parasitic capacitance is 100 fF or more.

Referring to Figs. 9A and 9B, an explanation will be given of the write/erase operation for the non-volatile semiconductor memory device shown in Fig. 7.

Fig. 9A is a circuit diagram showing the main part of

Fig. 7. Fig. 9B shows the waveforms applied to the

respective parts of the circuit. In Fig. 9A, Tl denotes a

select transistor, Mai denotes a non-volatile memory element, Co denotes a parasitic capacitance and RO denotes

an equivalent resistance corresponding to a leakage current. In the following explanation, it is assumed that the leakage

current is negligible.

The write/erase operation will be explained on the case where the non-volatile memory Mai has a high threshold

voltage of 7 V or more.

With the select transistor Tl turned "on", a voltage of

5 V is applied to the subsidiary bit line BLsal to charge

(precharge) the subsidiary bit line BLsal with the source

line at ground potential. Thereafter, the select transistor

Tsal is turned off to place the subsidiary bit line BLsal in a floating state. The capacitor component CO including the

capacitor Cal is charged.

Subsequently, a pulse signal as shown in Fig. 9B is

applied to the control gate of the non-volatile memory element Mai through the word line WI. When a negative pulse (- 10 V) is applied to the control gate of the memory

element Mai, a tunnelling current flows between the floating

gate and the drain thereof so that the threshold voltage Vth

is gradually lowered. When the threshold voltage Vth

becomes sufficiently low, a channel current flows between the source and the drain. This channel current reduces the

drain voltage (potential at the subsidiary bit line BLsal)

so that the tunnelling current stops to flow between the floating gate and the drain. Thus, the threshold voltage of

the memory element Mai is lowered to be set for a constant

value.

An explanation will be given of the case where the non-

volatile memory Mai has a low threshold voltage of 2 V.

Like the above case, with the select transistor Tl

turned "on" , a voltage of 5 V is applied to the sub-bit line

BLsal to charge (precharge) the subsidiary bit line BLsal

with the source line at ground potential. Thereafter, the select transistor Tsal is turned off to place the sub-bit

line BLsal in a floating state. The capacitor component CO including the capacitor Cal is charged.

Subsequently, like the above case, a pulse signal as

shown in Fig. 9B is applied to the control gate of the memory element Mai through the word line WI . When a positive pulse (3 V) is applied, the channel current flows between the source and the drain of the memory element Mai

so that the drain voltage is lowered. Thus, even when a

negative pulse (- 10 V) is applied, the tunnelling current

stops to flow between the floating gate and the drain. In this way, the positive pulses are applied so that charges

are not further extracted from the floating gate of the non¬

volatile memory element with a low threshold voltage in an initial state. Namely, the excess erasure does not occur.

Thus, even when the erase operation are performed

simultaneously for non-volatile memory elements with different threshold voltages, the excess erasure does not

occur. Therefore, the operation of unifying the threshold

voltages by the write operation before erasure which has

been conventionally carried out is not required.

Referring to Fig. 10, an explanation will be given of another embodiment of the non-volatile semiconductor memory

device according to the second aspect of the present

invention.

The embodiment of Fig. 10 is different from that of Fig. 7 in only the construction of the level shifter

circuit. So, the remaining circuit configuration will not

be explained here.

A level shifter circuit 22' includes a CMOS inverter 26

composed of transistors (MOSFETs) T8 and T9 , a CMOS inverter

27 composed of -transistors (MOSFETs) T10 and Til, a CMOS

inverter 28 composed of transistors (MOSFETs) T12 and T13, and a speed-up circuit 29 composed of inverters II, 12 and a capacitor Cl , arid, transistors (MOSFETs) T14 and T15. The drains of the transistors Til and T12 which are connected to

each other are oonnected to the input terminal of the CMOS transistor 26. A voltage of 0 V is applied to the

connection point.

The output terminal of the CMOS inverter 27 is

connected to the source of the transistor T8. The output

terminal of the CMOS inverter 28 is connected to the source

of the transistor T8. The speed-up circuit 29 and the drain

of the transistor T15 are connected to the input terminal of

the CMOS inverter 28, and the gate of the transistor T15 is

connected to the output thereof. The source of the transistor T15 is connected to a negative voltage source.

In operation, input pulse signals INI and IN2 each

having a peak value of 5 V is applied to the input terminals

of the CMOS inverters 27 and 28. A positive voltage of 3 V

is applied to the source of the transistor T10 and a negative voltage of - 10 V is applied to the drain of the transistor T13.

Referring to Figs. 11A to 11C, an explanation will be

given of the operation of the level shifter circuit 22'.

As shown in Fig. 11A, when an "L" level signal is supplied to the input terminal of the CMOS inverter 27, the

transistor T10 turns on and the transistor T8 also turns on.

On the other hand, an "L" level signal is supplied to the

input terminal of the CMOS inverter 28 so that the transistor T12 remains "off" and the transistor T9 also

remains "off". Thus, a voltage of 3 V is applied from the

output terminal to the word lines WI and W2.

Subsequently, when an "H" level signal is supplied to

the input terminal of the CMOS inverter 27, the transistor

T10 turns off. On the other hand, an "H" level signal is

supplied to the input terminal of the CMOS inverter 28 so

that the transistor T13 turns on. The transistor T9 also turns on. Thus, a voltage of -10 V is applied to the word

lines WI and W2 ... .

As a result, the pulse signal as shown in Fig. 11C is

applied to the word lines WI , W2, ... is applied so that the

threshold voltages of the non-volatile memory elements are

unified. An explanation will be given of the case where there is more leak of the charges stored in the sub-bit line. Where

the equivalent resistance RO in Fig. 9A is small, i.e. the

leakage current is large, the floating gate voltage V_pE is

hard to converge. Figs. 12A to 12C show the waveforms at the respective portions in the non-volatile memory element

for explaining such a case.

For the erasing operation of a non-volatile memory

element, when a pulse signal having a peak value varying between 5 V and -10 V as shown in Fig. 12C is applied to the

control gate, the floating gate voltage V.. oscillates in

accordance with the width applied to the control gate.

However, as shown in Fig. 12A, different floating gate voltages V_fC of non-volatile memory elements (a), (b) and >. c)

do not easily converge into a predetermined threshold

voltage V... Further, as shown in Fig. 12C, the bit line

voltages V_al of the non-volatile memory elements lower

abruptly.

An explanation will be given of still another embodiment of the non-volatile memory device according to

the second aspect of the present invention.

The embodiment of Fig. 13 is directed to the case where

the leakage current is large, and a current supply circuit

for compensating for the leakage current is provided.

Specifically, in a memory cell array 21, a resistor Ral is connected between a main bit line Blal and a subsidiary bit line BLsal. Where the leakage current is large, the

charging" voltage in the subsidiary bit line BLsal lowers abruptly. In order to obviate such a difficulty, it is

intended that a current equal to the leakage current or more is sup-plied to the sub-bit line BLsal to restrain a decrease

in the charging voltage. A resistor Rbl is also connected in a like manner. The memory array 21 has the same

configuration as that in Figs. 7 and 10. The level shifter

circuit may have the same configuration as that in Figs. 7

and 10. Fig. 13B shows an equivalent circuit of the main part

in the circuit of Fig. 13A. Fig. 13C shows the voltage

waveforms applied to the respective parts thereof. In Fig.

13B, symbol CO denotes a capacitance component generated in

the sub-bit line, symbol RO denotes an equivalent resistance set by the voltage applied to the sub-line and the leakage current, and symbol Ral denotes a resistance for supplying

the current equal to the leakage current or more.

Referring to Figs. 14A to 14C, an explanation will be

given of a further embodiment of the non-volatile

semiconductor memory device according to the second aspect of the present invention.

In Fig. 14A, a memory cell array 21 has the same

configuration as the above embodiment. A current supply

circuit for compensating for a leakage current is composed

of a transistor (MOSFET) Ta and a resistor Ral connected in series. The drain of the transistor Ta is connected to the

main bit line BLal . The source thereof is connected to one

end of the resistor Ral. The other end of the resistor Ral is connected to the subsidiary bit line BLsal. A transistor

Tb and a resistor Rbl are also connected in a like manner.

In this embodiment, the charges stored in the sub-bit

line can be held for a long time by turning on the

transistor Ta. Therefore, a select transistor Tsal is used

as a transfer gate and a subsidiary bit line is used as a

capacitor to constitute a DRAM (dynamic RAM). The read

operation for the DRAM can be carried out in such a manner

that with the transistor Tsal turned "on", a low voltage (1

to 2 V) is applied to a memory cell to measure the current therefrom.

The floating gate of the memory element can be charged

by the method in which with the select transistor Tsal

turned "off", a sufficiently high voltage is applied to a word line to inject charges (hot electrons) into the floating gate, and the method in which a sufficiently large potential difference is given between the semiconductor substrate and the word line to charge the floating gate by

the tunnelling current flowing the thin oxide film.

The charges can be extracted from the floating gate in such a manner that with the main bit line BLal placed at a

high potential side, the select transistor turned "on" and

the transistor Ta turned "off", the current equal to the leakage current or more is supplied to the subsidiary bit

line through a high resistance. It is needless to say that

diodes in reverse-bias connection may be used instead of the

resistors Ral and Ra2.

In the embodiments of Figs. 13 and 14, the first time

constant based on the equivalent resistance RO and the

capacitance component CO is set for a smaller value than the

second time Constance based on the resistor Ral and

capacitance component. For example, assuming that the

resistance of the resistor Ral is 100 MΩ, the second time constant based on it and the capacitance component including

the floating capacitance is set for 15 to 50 μsec, and the period of the pulse applied to the floating gate of the non¬

volatile memory element is set for about 30 μsec.

In this way, the second time constant is made smaller than the first time constant and the second time constant is

made not shorter than half the period of the pulse applied

to the control gate of the non-volatile memory element.

This is for the following reason.

Where the leakage of charges stored in the bit line is great, when a current is supplied to the drain electrode

side of the non-volatile memory cell through the resistor

Ral, this supplied current must be larger than the leakge current. However, for the memory cell in which the

electrons in the floating gate has been sufficiently

extracted, the further extraction of elelctrons must not

occur. In other words, current supply for restoring the

drain potential is not required for such a memory cell. The

time necessary to restore the drain potential is defined by

the second time constant. Therefore, the second time

constant is preferably smaller than the first time constant

and about half as large as the period of the applied pulse.

Figs. 15A to 15C show the operation state of non¬ volatile memory elements (a) and (b) with different floating

gate voltages V... The pulse signal varying between positive

(3 V) and negative (- 10 V) potentials and having a period

of about 30 μsec is applied to the floating gate. As shown in Fig. 15A, the floating gate voltage V-_c varies in

accordance with the pulse period. The floating gate

voltages V.. of the non-volatile memory elements (a) and (b)

gradually converge into a predetermined voltage. On

the other hand, as seen from (b) of Fig. 15B, the bit voltage B_S1 (drain voltage) of the memory element (b)

pulsates owing to a fall due to the leakage current and a

rise due to the supplied current as the charges stored in 7295

66

the floating gate are extracted. But, as seen from (a) in

Fig. 15B, the drain voltage of the memory element (a) has a

sufficiently high potential until the charges stored in the

floating gate are sufficiently extracted. On completion of

the charge extraction, the drain voltage start to pulsate

owing to a rise due to the supplied current and a fall due

to the leakage current.

The leakage current can be compensated for by the diode

equipped with a gate as shown in Fig. 16. A P-type well

region 31 is formed in an N-type semiconductor layer 30, and N-type source/drain regions 32s and 32d are formed in the P- type well region 31. A gate electrode 33 is formed on the

channel region.

A main bit line is connected to the N-type source/drain

regions 32s and 32d and the N-type semiconductor layer 30. A word line is connected to the gate electrode 33. A sub-

bit line is connected to the P-type well 31. In such a

structure, if the pulse signal applied to the gate electrode

33 is synchronized with the voltage applied to the word

line, a change in the drain voltage can be reduced.

The causes of the leakage current are the tunnelling current flowing between the floating gate and drain which

results from a negative gate voltage and lattice defects around the drain diffused layer. The former is the main

cause.

In the embodiment, a current is supplied to the drain in synchronism with the leakage current so that a change in

the drain voltage can be reduced.

As described above, the non-volatile semiconductor

memory device according to the second aspect of the present

invention includes means for supplying a current larger than

the leakage current to the subsidiary bit line so as to

maintain the potential precharged in the subsidiary bit line or main bit line. Namely, the current source composed of a

voltage source and resistor as described in the embodiments

is connected to the subsidiary bit line or main bit line.

The current source circuit should not be limited to those used in the embodiments, but can be realized by several

known circuits.

The memory cell array should not be also limited to

those used in the embodiments. For example, where a source

line and a subsidiary source line are provided, the leakage

current can be compensated for by connecting the current supply circuit to the source line and subsidiary source

line. In this case, the drain of the transistor Tal is

connected to the subsidiary source line and the source 7295

68

thereof is connected to the source line.

The memory cell array may be composed of plural blocks

each including plural non-volatile semiconductor memory

cells which are connected to the main bit line.

As described above, in accordance with the second

aspect of the present invention, with the subsidiary bit

line precharged, a pulse signal varying positive and

negative potentals is applied to the floating gates of the non-volatile memory elements through a level shifter so that

different floating gate voltages can be converged into a predetermined voltage. For this reason, the write/erase

operation for the non-volatile semiconductor memory device

can be executed very easily.

Even where the charging potential in the sub-bit line is lowered owing to the leakage current, provision of the current supply means for compensating for the leakage current permits the charges stored in the floating gate to

be erased with the potential maintained at the sub-bit line.

Thus, the non-volatile memory elements with different

floating gate voltages can be set for a predetermined

threshold voltage.

The non-volatile semiconductor memory device according

to the second aspect of the present invention, in which 7295

69

sufficient precharging is made for the subsidiary lines, can

operate in a stabilized manner as a DRAM.

Aspect III

Now referring to the drawings, an explanation will be

given of several embodiments of the non-volatile memory

device according to the third aspect of the present

invention.

Fig. 17A is a circuit diagram of one embodiment of the non-volatile semiconductor memory device.

As seen from Fig. 17A, the non-volatile semiconductor

memory device includes a memory cell array 41 composed of non-volatile memory elements, a pulse height setting circuit

42, a switch circuit 43 (e.g. multiplexer) and peripheral circuits inclusive of row/column decoder circuits and sense

amplifier circuits (not shown).

In the memory cell array 41, the drain of a select transistor Tsal is connected to a main bit line BLal, and the source of the select transistor Tsal is connected to a sub-bit line BLsal. The drains of memory elements Mai and

Ma2 are connected to the subsidiary bit line BLsal and the

sources thereof commonly connected are connected to the

drain of a source side select transistor Trsl through a

source line. A source side select line SL1 is connected to the control gate of the source side select transistor Trsl .

A capacitor Cal is connected between the source and drain of

each of the memory elements Mai and Ma2.

On the other hand, the drain of a select transistor

Tsbl is connected to a main bit line BLbl and the source

thereof is connected to a subsidiary bit line BLsbl. A

capacitor Cbl is connected to the source and drain of each

of the memory cells Mbl and Mb2.

Incidentally, if the parasitic capacitance based on the sub-bit line BLsal and non-volatile memory elements Mai and

Ma2 is relatively small, provision of the capacitor Cal is

necessarily required. Though the parasitic capacitance,

which has become smaller with miniaturization of memory elements, the capacitor Cal may be omitted, where the

parasitic capacitane is 100 fF or more.

A word line WI is connected to the control gates of the memory elements Mal and Mbl. A word line W2 is connected to

the control gates of the memory cells Ma2 and Mb2. The word lines WI , W2 , ... are connected to the switch circuit 43.

The switch circuit 43 is connected to the pulse peak value

setting circuit 42. The switch circuit 43, which may be a

switch, serves to successively apply an output pulse signal

from the pulse peak value setting circuit 42 to the word lines WI , W2 , ... through the switch circuit 43.

With a common word line connected to each of the blocks

each composed of plural memory elements, charges stored in

the memory elements may be successively erased.

The configuration of the pulse peak value setting

circuit 42 will be explained. A P-channel transistor

(MOSFET) Tl and an N-channel transistor (MOSF"T) T2

constitute a CMOS inverter. The source of the transistor Tl

is connected to transistors (MOSFETs) T3 and T4. The source

of the transistor T2 is connected to a negative voltage

source (- 10 V). The drains of the transistors Tl and T2 are connected to the gate of a transistor (MOSFET) T5 for speed-up, and the drain of the transistor T5 is connected to

the commonly connected gates of the transistors Tl and T2

and a transistor T6 for self-biasing. A first (4 V) and a

second (5 V) voltage source are connected to the drains of the transistors T3 and T4 with their gate electrodes

commonly connected.

In the pulse peak value setting circuit 42, an input

signal INI is inputted to the drain of the transistor T6, and an input signal IN2 is inputted to the gates of the transistor T3 and T4. From the output stage of the circuit 42, an output pulse signal composed of 5 V (peak value) positive pulses at a predetermined period, 4 V (peak value)

positive pulses superposed between the 5 V positive pulses

and - 10 V (peak value) negative pulses is applied to the word lines WI , W2 , ... through the switch circuit 3.

The output pulse signal from the pulse peak value

setting circuit 42 is applied to the control gates of the

memory elements through the switch circuit 43 and the word

lines so that the charges stored in the floating gates of

the memory elements which are placed in a floating state are

extracted to unify the threshold voltages of the memory elements into a predetermined value or range.

Fig. 18 shows another embodiment of the non-volatile

semiconductor memory device according to the third aspect of the present invention.

In a pulse peak value setting circuit 2 shown in Fig.

18, unlike the embodiment of Fig. 17A, the source of the transistor Tl of the CMOS inverter is connected to a 4 V

voltage source and also the source of the transistor T4 the drain of which is connected to the 5 V voltage source. The

remaining circuit configuration is the same as that of Fig. 17. Thus, although the input signals INI and IN2 different

from those in Fig. 17B are inputted, the resultant output

pulse signal is the same as that in Fig. 17B. Referring to Figs. 19A to 19C, an explanation will be

given of the operation of the circuit shown in Fig. 18.

Figs. 19A, 19B and 19C show the waveforms of a floating gate

voltage V_fC , a drain voltage (bit line voltage V_B1 ) and a

control gate voltage V-..

The pulse signal shown in Fig. 19C is composed of 3 V

(peak value) positive pulses (A) at a predetermined period,

2. 5 V (peak value) positive pulses (B) superposed between

the pulses (A) and - 10 V (peak value) negative pulses.

Such a pulse signal is applied to the control gates. The peak value of the positive pulses (A) applied to the control

gates should not be limited to 3 V, but may be 5 V.

The peak value of the 2. 5 V pulses (B) may be - 5 V.

Further, the peak value of the pulses (B) can be set within

a range between 3 V (or 5 V) and - 10 V, and should not be limited to 2.5 V and - 5V.

In operation, after the select transistors Tsal and

Trsl are turned on to charge the subsidiary bit line BLsal

and capacitor Cal, etc. , the select transistor Tsal is

turned off to place the memory elements Mai and Ma2 in a

floating state. Subsequently, when the pulse signal (control gate voltage V-. ) as shown in Fig. 19C is applied to

the word line WI through the switch circuit 43, the charges stored in the floating gate of the memory element Mai are

extracted. As seen from (a), (b) and (c) of Fig. 19,

different floating gate voltages V.. will be converged when about 300.0 μsec passes. The bit line voltages V_Bl have the

waveforms as shown in (a), (b) and (c) of Fig. 19B. The

difference in these waveforms is due to the initial values

of the floating gate voltages and the leakage currents

generated in the bit lines.

Fig. 20 shows still another embodiment of the non-

volatile semiconductor memory device according to the third aspect of the present invention.

The pulse peak value setting circuit 44 is composed of

a switch circuit 44 and voltage source circuits 45. , 45. and 45₃. The switch circuit 44 is composed of a buffer 44.. and

a switch 44_lb ; a buffer 44_2a a d a switch 44_2a and a switch 44._b. The outputs from the switches 45. , 45. and 45., which

are commonly connected, is connected to the switch circuit

43. Voltages 3 V and - 5 V outputted from the voltage

sources 45* and 45₂ are inputted to the switches 44,_b and 44_2b

through the buffers 44_Ia and 44_2l . A voltage of - 10 V from the voltage source 45. is inputted to the switch 44_3fe .

Referring to Fig. 21, an explanation will be given of

the operation of the embodiment of Fig. 20. 7295

The equivalent circuit of the switch circuit 44 shown

in Fig. 20 is shown in Fig. 21A. The switches 44_]fc to 44._fc

are labelled a to c. Timings of select signals for

controlling these switches are shown in Fig. 21B. The

output from the switch circuit 44 is shown in Fig. 21C.

At a timing tl, when the switch a is turned on and the

switches b and c are turned off, a 3 V (peak value) positive

pulse is outputted. At a timing t2, when the switch c is turned on a d the other switches are turned off, a - 10 V

(peak value) negative pulse is outputted. At a timing t3,

when the switch b is turned on and the other switches are

turned off, a - 5 V (peak value) negative pulse is

outputted. In this way, by controlling the switches a, b

and c, a composed pulse signal is applied to the control gates of the memory elements the switch circuit 3.

Fig. 21 shows a further embodiment of the non-volatile

semiconductor memory device according to the third aspect of

the present invention.

As seen from Fig. 22A, the switch circuit 44 is

composed of switches Al , Bl, Cl, A2 , B2 and C2. The one ends of the switches Al and A2 are connected to a voltage

source (3 V) 45. , those of the switches Bl and B2 are

connected to a voltage source (- 5 V) 5., and those of the switches Cl and C2 are connected to a voltage source (- 10

V). The other ends of the switches Al, Bl and Cl are

commonly connected. The other ends of the switches A2 , B2

and C2, which are also commonly connected, are connected to

the word lines through the switch circuit (e.g. multiplexer)

43.

Referring to Figs. 22B and 22C, a composed pulse will

be explained. At a timing tl, when the switch Al is turned

on, a 3 V (peak value) positive pulse is outputted. At a

timing t2 , when the switch Cl is turned on, a - 10 (peak value) negative pulse is outputted. At a timing t3 , when

the switch Bl is turned on, a - 5 V (peak value) negative pulse is outputted. At the timing t2, when the switch A2 is

turned on, a 3 V positive pulse indicated by a dotted line

is outputted. Subsequently, at the timing t3 , when the switch C2 is turned on, a - 10 V (peak value) negative pulse

is outputted.

Incidentally, as extraction of charges from the

floating gate is completed, the pulsation in the drain

voltage constitutes noise in detecting reduction in the drain voltage. It obstructs the detection of the threshold

voltage of the memory element. The pulsation can be

decreased by decreasing the pulse width in the word line, 7295

77

which increases power consumption. However, by setting

three levels A, B and C of the pulse signal applied to the

control gates for 3 V, - 5 V (as negative as possible) and -

10 V, the charges charged/discharged through the word line

can be decreased to reduce power consumption.

It is needless to say that a large leakage current also

obstructs the erase and write operation. This can be

compensated for by the current supply means for supplying

the current equal to the leakage current generated by the

memory element.

Figs. 23A and 23B show a further embodiment of the non¬ volatile semiconductor memory device according to the third

aspect of the present invention which is an NAND gate type

EEPROM.

In Fig. 23A, memory elements (cells) Ml to M3 are connected in series between select transistors Tsl and Ts2. The control gates of these memory elements Ml, M2 and M3 are

connected to word lines WI , W2 and W3 , respectively. The

drain of the select transistor Tsl is connected to a bit

line BLal and connected to a voltage source (5 V) through a

resistor Rl . ST1 and ST2 denote select lines.

The potentials on the respective word lines necessary

to extract the charges from the floating gates of the cells 7295

Ml to M3 are shown in the table of Fig. 23B.

For example, when the cell 1 is to be erased, with the

select lines STl a d ST2 and the word lines W2 and W3 placed

at "H" level, the pulse signal as described in the above

embodiments is applied to the word line WI so that the

charges stored in the floating gate of the cell 1 can be

surely extracted. The pulse signal may be also composed of

pulses varying between negative and positive potentials.

The resistor Rl is a resistor for supplying a minute

current which is the simplest current supplying means for compensating for the leakage current. If the bit line

cannot gives sufficient capacitance, a capacitor CO is

provided.

As described above, the non-volatile semiconductor

memory device according to the third aspect of the present invention intends to apply a pulse signal varying between positive and negative potentials to the control gates of

memory elements so that the charges stored in the gates are extracted so as to make an erase/write operation. When

pulses having a peak value higher than a predetermined normal potential are applied at a predetermined period, the channel conductance of the memory element increases

temporarily so that the drain potential decreases abruptly. 295

79

Thus, reduction in the threshold voltage can be easily

detected.

The application of the pulses with the potential

higher than a predetermined potential, which promotes high

speed charging/discharging for word lines, gives rise to an

increase in power consumption. However, this defect can be

obviated by superposing lower (negative) potential pulses

between the higher potential pulses. That is, the pulses

with the higher potential serve to set the threshold voltage

and the superposed pulses with a negative potential serve to reduce power consumption.

In accordance with the third aspect of the present

invention, by applying a pulse signal to word lines to

perform the erase/write operation, the threshold voltages

can be properly detected in a stabilized manner and also the operation time can be reduced.

Further, charges can be simultaneously extracted from

the floating gates of a large number of memory elements, and

the threshold voltages can be unified accurately.

Aspect IV

Now referring to the drawings, an explanation will be

given of one embodiment of the non-volatile semiconductor

memory device according to the fourth aspect of the present 7295

80

invention.

First, for comparison to the fourh aspect, a further

improvement required in the present invention described

above will be explained.

The means for making uniform the threshold voltages of

floating gate type memory transistors was proposed by

inventors of this application. This proposal is to apply

pulses to the control gate of a memory transistor in a floating condition to extract the charges stored in the

floating gate so that the threshold voltages are converged.

Figs. 40A and 40B are an equivalent circuit diagram showing

the proposal and an operation waveform chart, respectively.

In Fig. 40A, symbol TO denotes a selection transistor

and symbol MO denotes a non-volatile memory transistor. In

operation, as seen from the waveform chart of Fig. 40B, a voltage of 5 V as a drain voltage is applied to the drain of

the selection transistor TO and a voltage of 5 V is applied

to the selection gate thereof. Thereafter, the drain of the

memory transistor MO is placed in the floating state.

Subsequently, pulses which oscillate positively and negatively at a predetermined period are applied to the

control gate of the memory transistor MO to extract

redundant charges so that the threshold voltage is lowered. 7295

81

An exemplary circuit for generating pulses is shown in

Fig. 41A. In Fig. 41A, a CMOS inverter is composed of a

PMOS transistor Ta and an NMOS transistor Tb. To its input

stage a self-biased transistor Td is connected. To its

input and output terminals the drain and control gate of a

speed-up transistor Ta are connected, respectively. To the

source of the PMOS transistor Ta a 3V voltage source is

connected. To the drain of the NMOS transistor a (-) 10

volt source is connected.

Fig. 41B shows an input signal IN with a peak value of

5 V. Fig. 41C shows an output signal OUT ranging from - 10

V to 3 V.

Figs. 42A to 42C show changes in the potentials on the

floating gate and bit line when a pulse-like control voltage

V_CI! is applied to the control gate of a memory transistor.

Specifically, when the pulses as shown in Fig. 42C are

applied to the control gate, different floating gate

voltages V_FG in an initial state are converged into a predetermined threshold voltage within about 100 μsec as

shown in (a), (b) and (c) in Fig. 42A. Then, as shown in (a), (b) and (c) of Fig. 42B, the bit voltages change.

However, if an equivalent resistance Rl is small, a large

leakage current id flows. As a result, as shown in Fig. 7295

82

43A, the waveforms (a), (b) and (c) of the floating gate

voltage V-_c are not converged after lapse of 200 μsec.

Now, in Fig. 24, a memory cell array 62 is composed of memory elements (MOSFETs) Mil, M12, M21 and M22. Bit lines

BL1 and BL2 are connected to the sources of select

transistors Tl and T2 , respectively. The drains of the

memory elements Mil and M21 are connected to a subsidiary

bit line BLsl and those of the memory elements M12 and M22 are connected to a subsidiary bit line BLs2. The respective

sources of the memory elements Mil, M12, M21 and M22 are connected to a source line SI which is connected to the

drain of the select transistor Ts. STl and ST2 denote

select lines and WL1 and WL2 denote word lines.

The bit lines BL1 and BL2 are connected to minute

current supply circuits 66 and 67 and also connected to a column decoder circuit 64. The word lines WL1 and WL2 are

connected to a row decoder circuit 2 through a word driver

circuit 63. A pulse signal for erase/write operation is supplied from a pulse generating circuit 65 to the word

lines WL1 and WL2 through the word driver circuit 63. To the minute current supply circuits 66 and 67, clock signals

and Φ bar are applied, respectively.

During the erase/write operation, a pulse signal varying between positive and negative potentials is applied

to any one of the selected word lines WL1 and WL2 from the

pulse generating circuit 65 as described above. During the

erase operation, in accordance with the operation of the

column decoder circuit 64, a current is supplied to the

subsidiary bit line BLsl or BLs2 (drains or sources of the

memory elements) from any of the current supply circuits 66

and 67 through the select transistor Tl or T2. The current

supplied from the minute current circuit 66 or 67

corresponds to the leakage current (3-5 nA) from the sources or drains of the memory elements. In this way, the difficulty in the erase/write operation as described in

connection with Figs. 40A and 40B can be overcome.

The minute current supply circuits 66 and 67 can apply a predetermined charging voltage to the subsidiary bit lines BLsl and BLs2 through the select transistor Tl and T2 thereby to supply a minute current to the drains of the

memory elements. The predetermined charging voltage can be

supplied from e.g. a charging circuit composed of a

transistor and a capacitor.

The minute current supply circuits 66 and 67 can be

constructed by the charge pump circuits as shown in Figs. 27

and 28 and the switched capacitor circuits as shown in Figs. 30 to 33 .

Referring to Fig. 25, an explanation will be given of

another embodiment of the non-volatile semiconductor memory device according to the fourth aspect of the present

invention.

The embodiment of Fig. 25 is different from that of

Fig. 24 in the following points. The bit lines BL1 and BL2

are connected to the column decoder circuit 64 and a minute

current supply circuit 68 is connected to the column decoder

circuit 64. The minute current supply circuit 68 to which clock signals Φ and Φ bar are supplied is controlled by a

transistor T3. The minute current from the minute current supply circuit 68 is supplied to the main bit lines BL1 and

BL2 through the column decoder 64 and further connected to the sub-bit lines BLsl and BLs2 through the select

transistors Tl and T2. The transistor T3 with a control

gate to which a control signal is supplied operates in

accordance with the operation timings of the column decoder

circuit 64. Then, the column decoder circuit 68 operates to

supply the minute current through the column decoder circuit 64. The remaining circuit configuration is the same as that

in Fig. 24.

Further, the minute current supply circuit 68 can be constructed by charge pump circuits and switched capacitor

circuits as in the embodiment of Fig. 24 which can supply a

minute current corresponding to the leakage current for each

main bit line.

Referring to Fig. 26, an explanation will be given of

still another embodiment of the non-volatile semiconductor

memory device according to the fourth aspect of the present

invention.

The embodiment of Fig. 26 is different from that of Fig. 24 in the following points. The minute current supply circuits 66 and 67 are connected to transistors T4 and T5

with their control gates which are controlled by the column

decoder circuit 64. The minute current supply circuits 66 and 67 sets the potential for each bit line. The minute

current supply circuits 66 and 67 can be constructed by the same arrangement as in the embodiment of Fig. 24 and the

remaining circuit configuration is the same as in the

embodiment of Fig. 24.

In this embodiment, as in the embodiment of Fig. 25, the minute current supply circuits 66 and 67, which are controlled by the transistors T4 and T5 , respectively,

supply the minute current for each bit line.

Referring to Figs. 27 to 33, an explanation will be given of embodiments of the minute current supply circuits

66 to 68.

Fig. 27 shows the minute current supply circuit

constructed by a charge pump circuit. As seen from Fig. 27,

self-biased transistors T6 , T7 and T8 are connected in

series. To the junction point of the transistors T7 and T8

a coupling capacitor Cl is connected. To the junction point

of the transistors T6 and T7 a coupling capacitor C2 is

connected. A clock signal Φ is applied through the coupling

capacitor Cl and a clock signal Φ bar is applied through the

coupling capacitor C2. The output OUT from the charge pump circuit is applied to the bit lines BL1 and BL2.

The clock signals Φ and Φ bar have a peak value of 5 V

and a frequency of 1 MHz. When the clock signals Φ and Φ

inverted from each other are applied to the respective junction points, a predetermined voltage is applied through

the transistor T8 to the bit lines. When the predetermined

voltage is applied to the bit lines through the charge pump

circuit, a minute current I, (3-5 nA) is supplied to the

sub-bit lines through the on-state select transistors. The

coupling capacitors Cl and C2 have a capacitance of 1-1000 fF. The value of the minute current I_y is determined by a

clock frequency and an oscillation frequency. The supplied current I_j to the bit lines is charged as a line

capacitance. The clock signals adopted in this embodiment

have a clock frequency of 1 Mhz and a peak value of 5 V.

The parasitic capacitance in the bit lines is 1 pF. The

value of the minute current I, can be optionally set in

accordance with the value of the leakage current I_I (3-5

nA) .

Fig. 28 shows an charge pump circuit capable of

providing a higher potential. On the ground side of the

charge pump circuit in Fig. 27, a self-biased transistor T9

is connected in series. To the junction point of the transistors T6 and T9, a coupling capacitor C3 is connected.

A clock signal Φ is applied through the coupling capacitor

C3. To the coupling capacitors Cl and C2, the same clock

signals as in Fig. 27 are applied. The output OUT is applied

to the bit line. C4 denotes the parasitic capacitance (about

IpF) on the bit line. Tl denotes a select transistor and M denotes a memory transistor. Transistors T6 to T9 denotes

MOSFETs. Figs. 29A to 29E show the waveforms representative of the operation state of the circuit of Fig. 28. Referring to

Fig. 28, an explanation will be given of the operation of

the non-volatile semiconductor memory device provided with the charge pump circuit of Fig. 28.

A source voltage (5 V) is applied to the drain of the

select transistor Tl in an on-state to charge the drain or

source of the memory element Tl. A minute current I. (3-5

nA) is supplied to the drain of the memory element M through

the on-state select transistor Tl. Thus, the drain of the

memory element M is substantially set for its floating

state. Thereafter, the pulse signal as shown in Fig. 29E is

applied to the control gate of the memory element M through

the word line WL for an erase/write operation. In the state of the memory element where redundant electrons are

extracted so that the threshold voltage is unified or

converged, the channel conductance of the memory element is about 1 MΩ.

On the other hand, in the charge pump circuit, clock signals Φ, Φ bar and Φ each having a frequency of 1 MHz and a peak value of 5 V are applied to the junction points A, B

and C through the coupling capacitors Cl , C2 and C3 ,

respectively. The waveforms at these junction points are

shown in Figs. 29A to 29D.

As seen from the waveforms shown in Figs. 29A to 29E, when the clock signal Φ is applied through the coupling

capacitor C3, the transistor T9 is charged so that the potential at point A is boosted. Simultaneously, when the

clock signal Φ bar with an inverted phase is applied, the

transistor T6 is charged. The resultant potential is

superposed on the potential at point A. As a result of

successive superposition, the voltage as shown in Fig. 29A

is applied to the bit line BL. Thereafter, the minute

current is supplied to the drain or source of the memory

element M through the on-state select transistor Tl and the

pulse signal as shown in Fig. 29E is applied so that the

redundant charges in the floating gate are extracted to

unify the threshold voltage of the memory element.

Fig. 30 shows a switched capacitor circuit used as the

minute current supply circuits 66 to 68.

As seen from Fig. 30, a voltage source EO is connected to the drain of a transistor TIO. The source of the transistor TIO is connected to the one end of a capacitor C5 and the drain of the transistor Til. The source of the

transistor Til is connected to a bit line BL. The bit line

BL has a parasitic capacitance of about 1 pF and the

capacitor C5 has a capacitance of about 15 fF.

In operation, the clock signals Φ and Φ bar are applied

to the control gates of transistors TIO and Til so that the

transistors TIO and Til are alternately turned on. A "H" level pulse is applied to the control gate of the transistor

T10 while a "L" level pulse is applied to the control gate

of the transistor Til. Thus, a voltage EO is applied to the

capacitor C5 so that the capacitor C5 is charged.

Subsequently, when the "L" level signal is applied to the

control gate of the transistor TIO, the transistor TIO

turns off. When the "H" level signal is applied to the

transistor Til, the transistor Til turns on. The charging

voltage charged in the capacitor C5 is outputted through the

transistor Til and charged into the parasitic capacitor C6 of the bit line. In this way, when the transistors TIO and

Til operate alternately, a predetermined voltage is applied

to the bit line BL. The capacitance of the capacitor C5 is set for a small capacitance of 1-100 fF, and the frequency and amplitude of each of the clock signals Φ and Φ bar are

set for optimum values so that a minute current is supplied to the bit line BL.

Fig. 31 shows the operation waveforms when the switched

capacitor circuit is used as the minute current supply

circuit.

In operation, when clock signals Φ and Φ bar are

applied to the control gates of the transistors T10 and Til,

the capacitor is gradually charged so that the potential at the junction point of the transistors TIO and Til increases.

As a result, the output voltage having the waveform as shown

in Fig. 31A is applied to the bit line BL. Then, the pulse

signal as shown in Fig. 31C is applied to the control gate

of the memory element M. Accordingly, different floating

gate voltages V-. are unified into a predetermined threshold

value. The bit line voltage V,. has the waveform as shown in

Fig. 31A.

Fig. 32 shows another embodiment of the switched

capacitor circuit. To the circuit of Fig. 30, transistors

Til and T13 is further connected and a MOS transistor T12 in

diode connection is connected to the junction point of the

transistor Til and T13. This structure permits noise to be

removed so that the stabilized output can be applied to the bit line. The transistors TIO to T13 are MOS transistors. The waveforms at the respective points of the switched

capacitor circuit of Fig. 32 are shown in Figs. 33A to 33D.

Fig. 34 shows a further embodiment of the non-volatile

semiconductor memory device according to the fourth aspect

of the present invention.

In the embodiment of Fig. 34, a memory cell array 61

has the same structure as that shown in Fig. 24. A minute

current supply circuit 70 is connected to subsidiary bit lines BLsl and Bls2 through a switch circuit 71 (e.g.

multiplexer). The minute current supply circuit 71 can be

connected to the subsidiary bit lines of an adjacent memory

cell array through the switch circuit 71. Each of the

supplementary capacitors Ca and Cb is 100 to 300 fF.

The erase/write operation in this embodiment is carried

out as follows. After the drains (or sources) of the memory

elements are charged to a positive potential, the select

transistor is turned off. A minute current (3-5 nA) is

supplied to the drains (bit line) to place the bit line in a

floating state. A pulse signal is applied to the control

gate of the memory element to reduce the charges stored in the floating gate, thus performing the write/erase

operation. During the erase/write operation, the minute current is supplied to the sub-bit line through the switch circuit 71.

Figs. 35 to 37 show further embodiments of the non¬ volatile semiconductor memory device according to the fourth

aspect of the present invention.

In the previous embodiments, the charge pump circuit or switched capacitor circuit is used as the minute current

supply circuit to charge the bit lines. On the other hand,

the embodiments of Figs. 35 to 37 intend to improve the response characteristic of charging/discharging to realize

high speed erase/write.

The embodiments of Figs. 35 to 37 are characterized in

that a charging/discharging system for bit lines are added

to the embodiments of Figs. 24 to 26.

In Fig. 35, the bit lines BL1 and BL2 are connected to

the sources of transistors T6 and T7, respectively. The

drains of the transistors are connected to voltage sources

Vcc. The other circuit configuration is the same as that in

Fig. 24. In operation, a charging signal Sc is applied to the sources of the transistors T6 and T7, and a discharging

signal Sd is applied to the gates of the transistors T4 and

T5. At the start of the erase/write operation, the charging

signal is applied. At the end thereof, the discharging

signal Sd is applied to discharge the charges stored in the bit lines BL1 and BL2.

In Fig. 36, the bit line BL1 is connected to the junction point of transistors T8 and T9, and the bit line

BL2 is connected to the junction point of transistors TIO

and Til. The transistors T9 and Til constitute a charging system. Charging signals Sci and Sc2 are applied to the

gates of the transistors T9 and Til, respectively so that

the bit lines BL1 and BL2 are charged to perform the erase/write operation. On the other hand, the transistors

T8 and TIO constitute a discharge system. At the end of the

erase/write operation, discharging signals Sdl and Sd2 are

applied to the transistors T8 and TIO to discharge the charges stored in the bit lines BLl and BL2. In the

embodiment, the charging/discharging operation can be

carried out for each bit line.

In Fig. 37, the bit line BLl is connected to the

junction point of the transistors T8 and T9, and the bit line BL2 is connected to the junction point of the

transistors TIO and Til. The transistors T9 and Til

constitute a charging system. A charging signal Sc is applied to the gates of the transistors T9 and Til, respectively so that the bit lines BLl and BL2 are charged to perform the erase/write operation. On the other hand,

the transistors T8 and TIO constitute a discharge system. At the end of the erase/write operation, a discharging

signal Sd is applied to the transistors T8 and TIO their

gates of which are commonly connected, thereby discharging the charges stored in the bit lines BLl and BL2.

In the embodiments of Figs. 35 to 37, the charging

signal is applied to the bit lines by the

charging/discharging system before a predetermined potential to the bit lines by the charge pump circuit or switched

capacitor circuit, thereby charging the bit lines at the

higher potential than source potential. Thereafter, the

pulse sinal is applied to the word lines to unify the

threshold values of predetermined memory elements. Thus, the

erase/write operation can be carried out at a high speed.

On the other hand, after the completion of the erase/write

operation, the bit lines are placed at the potential lower

than the drain potential. This permits the operation to be succeeded by a next operation within a short time.

As described above, in the non-volatile semiconductor

memory device according to the fourth aspect of the present

invention, a very minute current is supplied to bit lines

through on-state select transistors. Otherwise, after the bit lines are charged, the select transistors are turned off and the minute current equivalent to a leakage current is

supplied to the bit lines. Thereafter, the a pulse signal is applied to the control gates of the memory elements to

unify the threshold voltages thereof. Since the minute

current is supplied to the bit lines while the channel

conductance of the memory elements is large, in order to

prevent excess erasure in the memory elements or restoration

of the potential on the drain side, a pulse signal having shorter pulse widths than the restoration time should be

applied to the control gates.

Although the charge pump circuit or switched capacitor

in which the current value can be set in terms of the

frequency and the peak value can be used, several known

circuits capable of supplying the minute current may be

used.

In the non-volatile semiconductor memory device

according to the fourth aspect of the present invention, in

the erase/write process of extracting charges from the

floating gate, the manner of injecting electrons into the

floating gate is the same as the conventional manner. Therefore, the memory device can be applied to a non¬

volatile semiconductor memory device in which the floating

gate is charged at a negative potential by hot electrons from a channel and charges are caused to escape from the

floating gate toward a source/drain or a substrate by the

tunnelling current.

In the non-volatile semiconductor memory device

according to the fourth aspect of the present invention, the erase/write operation is carried out in such a manner that

with the bit lines substantially placed in a floating state

by a minute current, a pulse signal varying between positive and negative potentials is applied to the control

gates of the memory elements to extract the redundant

charges stored in the floating gate. Since the minute

current is supplied to the bit lines by the minute current supply circuit even when there are leakage currents from the

bit lines (drains or sources), it is possible to extract the

charges from the floating gates of a large number of memory

elements simultaneously and precisely.

By carrying out the erase/write operation after the bit

lines are charged, the rising time of the charging potential can be shortened so that the erase/write operation time can

be shortened.

Claims

CLAIMS :

1. A non-volatile semiconductor memory device comprising:

a memory cell, each composed of a source, a drain, a floating gate and a control gate;

means for charging either one of the source and drain

of the memory cell and placing it in a floating state after

a predetermined time; and

means for applying a signal varying between a positive potential and a negative potential to the control gate of

said memory cell to reduce charges stored in said floating gate.

2. A non-volatile semiconductor memory device according to claim 1, wherein the absolute value of the positive

potential of the said signal applied to said control gate is smaller than that of the negative potential thereof.

3. A non-volatile semiconductor memory device according to claim 1, wherein the peak values of said signal are so set

that a tunnelling current flows between said control gate and said source or drain owing to the negative potential of said signal and that a current flows between the source and

drain owing to the positive potential of said signal.

4. A non-volatile semiconductor memory device according to

claim 1, wherein the negative potential of said pulse signal

applied to said control gate is applied after the positive

potential is applied.

5. A non-volatile semiconductor memory device according to

claim 1, wherein a change of the potential applied to said

drain or source of said memory cell stops the application of

said signal to said control gate.

6. A non-volatile semiconductor memory device according to

claim 1, wherein the negative potential of said signal

applied to said control gate is changed before a change in

the potential in a bit line resulting from the current

flowing between said source and drain of said memory cell.

7. A non-volatile semiconductor memory device according to claim 1, wherein the duration of the positive potential of said pulse signal applied to said control gate is longer

than that of the negative potential thereof.

8. A non-volatile semiconductor memory device according to

claim 1 , wherein the order of applying the positive and negative potentials to said control gate is exchanged.

9. A non-volatile semiconductor memory device comprising: a memory cell composed of a source, a drain, a floating gate and a control gate;

means for charging either one of the source and drain

of the memory cell and placing it in a floating state after

a predetermined time; and means for applying a signal varying between a positive

potential and a negative potential to the control gate of said memory cell whereby its threshold voltage is converged.

10. A non-volatile semiconductor memory device according to claim 9, wherein the absolute value of the positive

potential of the said signal applied to said control gate is larger than that of the negative potential thereof.

11. A non-volatile semiconductor memory device according to claim 9, wherein the peak values of said signal are so set

that a tunnelling current flows between said control gate and said source or drain owing to the negative potential of

said signal and that a current flows between the source and

drain owing to the positive potential of said signal.

12. A non-volatile semiconductor memory device according to

claim 9, wherein the converged threshold voltage is set by

the positive potential of said signal applied to said

control gate.

13. A non-volatile semiconductor memory device according to

claim 9, wherein the negative potential of said pulse signal

applied to said control gate is applied after the positive

potential is applied.

14. A non-volatile semiconductor memory device according to

claim 9, wherein a change of the potential applied to said

drain or source of said memory cell stops the application of said signal to said control gate.

15. A non-volatile semiconductor memory device according to claim 9, wherein the negative potential of said signal applied to said control gate is changed before a change in

the potential in a bit line resulting from the current

flowing between said source and drain of said memory cell.

16. A non-volatile semiconductor memory device according to

claim 9, wherein the duration of the positive potential of said pulse signal applied to said control gate is longer

than that of the negative potential thereof.

17. A non-volatile semiconductor memory device according to

claim 9, wherein the order of applying the positive and negative potentials to said control gate is exchanged.

18. A non-volatile semiconductor memory device comprising: a plurality of memory cells, each composed of a source, a drain, a floating gate and a control gate; means for charging either one of the source and drain of a selected memory cell and placing it in a floating state

after a predetermined time; and

means for applying a signal varying between a positive

potential and a negative potential to the control gate of said selected memory cell whereby its threshold voltage is

converged.

19. A non-volatile semiconductor memory device according to

claim 18, wherein the absolute value of the positive

potential of the said signal applied to said control gate is

larger than that of the negative potential thereof.

20. A non-volatile semiconductor memory device according to

claim 18, wherein the peak values of said signal are so set

that a tunnelling current flows between said control gate

and said source or drain owing to the negative potential of said signal and that a current flows between the source and

drain owing to the positive potential of said signal.

21. A non-volatile semiconductor memory device according to

claim 18, wherein the converged threshold voltage is set by the positive potential of said signal applied to said control gate.

22. A non-volatile semiconductor memory device according to

claim 18, wherein the negative potential of said signal

applied to said control gate is applied after the positive potential is applied.

23. A non-volatile semiconductor memory device according to

claim 18, wherein charges stored in said floating gates of

said memory cells with said control gates commonly connected are simultaneously reduced.

24. A non-volatile semiconductor memory device according to claim 18, wherein a change of the potential applied to said

drain or source of said memory cell stops the application of

said signal to said control gate.

25. A non-volatile semiconductor memory device according to

claim 18, wherein the negative potential of said signal

applied to said control gate is changed before a change in

the potential in a bit line resulting from the current

flowing between said source and drain of said memory cell.

26. A non-volatile semiconductor memory device according to claim 18, wherein the duration of the positive potential of

said signal applied to said control gate is longer than that

of the negative potential thereof.

27. A non-volatile semiconductor memory device comprising: a plurality of word lines;

a plurality of bit lines intersecting word lines and a

plurality of source lines;

a plurality of memory cells, each composed of a source, a drain, a floating gate and a control gate, provided at the

intersections between said word lines and said bit lines,

each of the control gates, drains and sources of said memory 27295

105

cells being electrically connected to each of said word

lines, each of said bit lines and each of said source lines,

respectively;

means for charging either one of the source and drain

of a selected memory cell and placing it in a floating state

after a predetermined time; and

means for applying a pulse signal varying between a

positive potential and a negative potential to the control gate of said selected memory cell whereby its threshold voltage is converged.

28. A non-volatile semiconductor memory device according to

claim 27, wherein the absolute value of the positive

29. A non-volatile semiconductor memory device according to claim 27, wherein the peak values of said signal are so set

that a tunnelling current flows between said control gate

drain owing to the positive potential of said signal.

30. A non-volatile semiconductor memory device according to

claim 27, wherein the converged threshold voltage is set by

the positive potential of said signal applied to said

control gate.

31. A non-volatile semiconductor memory device according to

claim 27, wherein the negative potential of said signal

32. A non-volatile semiconductor memory device according to

claim 27, wherein charges stored in said floating gates of

33. A non-volatile semiconductor memory device according to

claim 27, wherein a change of the potential applied to said

drain or source of said memory cell stops the application of

said signal to said control gate.

34. A non-volatile semiconductor memory device according to

claim 27, wherein the negative potential of said signal

applied to said control gate is changed before a change in the potential in a bit line resulting from the current

flowing between said source and drain of said memory cell.

35. A non-volatile semiconductor memory device according to

claim 27, wherein the duration of the positive potential of said signal applied to said control gate is longer than that

of the negative potential thereof.

36. A non-volatile semiconductor memory device comprising:

a plurality of word lines; a plurality of bit lines intersecting said word lines,

each of bit lines being connected to each of said bit lines

through a select transistor;

a plurality of memory cells, each composed of a source, a drain, a floating gate and a control gate, provided at the intersections between said word lines, and said bit lines, each of the control gates, drains and sources of said memory

cells being connected to each of said word lines, each of said bit lines and each of said source lines, respectively;

means for charging either one of said source and drain of each of said memory cells; and

means for applying a pulse signal pulses each having a

positive peak potential and a negative peak potential through said word lines to the control gate of said selected

memory cell whereby its threshold voltage is converged.

37. A non-volatile semiconductor memory device according to

claim 36, further comprising:

means for supplying a current for compensating for a

leakage current in said bit lines.

38. A non-volatile semiconductor memory device according to

claim 36, wherein the memory device further includes a plurality of main bit lines, each of the main bit lines being electrically connected to each of said bit lines

through a selector transistor.

39. A non-volatile semiconductor memory device according to claim 36 further comprising: first switch means for applying a potential which is

not lower than a source potential to the source or drain of each memory cell; and

second switch means for applying a potential which is not higher than a drain potential to the source or drain of

each memory cell.

40. A non-volatile semiconductor memory device according to

claim 39, wherein before the signal is applied to the

control gate, the bit line is set for a higher potential

than the source potential by said first switch means.

41. A non-volatile semiconductor memory device according to

claim 39, wherein before the signal is applied to the

control gate, said bit line is set at a higher potential

than the source potential by said first switch means, and

after said signal is applied to said control gate, said bit line is set at a lower voltage than a drain potential by said second switch means.

42. A non-volatile semiconductor memory device according to claim 36, wherein the floating gate of each memory cell is charged to a negative potential by hot electrons from the channel of each memory cell, and the charges stored in said floating gate is caused to flow from the floating gate to

the source, drain or substrate as a tunneling current.

43. A non-volatile semiconductor memory device according to

claim 36, wherein the floating gate is charged to a negative potential by a tunnelling current flowing from the source, drain or substrate, and the charges stored in said floating

gate are caused to flow from the floating gate to the

source, drain or substrate as another tunneling current.

44. A non-volatile semiconductor memory device according

claim 36, wherein said minute current supply means is

electrically connected to at least one bit line directly or

through a switch.

45. A non-volatile semiconductor memory device according to claim 44, wherein said switched capacitor circuit includes at least one MOS diode.

46. A non-volatile semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting said word lines;

a plurality of memory cells, each composed of a source,

a drain, a floating gate and a control gate, provided at the

intersections between said word lines and said bit lines,

each of the control gates, drains and sources of said memory cells being connected to each of said word lines, each of

said bit lines and each of source lines, respectively;

means for precharging one of the bit lines and placing it in a floating state after a predetermined time; and

means for applying a signal composed of pulses each

having a positive peak potential and a negative peak

potential through said word lines to the control gate of said selected memory cell whereby its threshold voltage is

converged into a predetermined voltage.

47. A non-volatile semiconductor memory device according to claim 46, further comprising:

means for supplying a current for compensating for a

leakage current in said bit lines.

48. A non-volatile semiconductor memory device according to claim 46, further comprising: means for supplying a minute current to the source or

drain of each of said memory cells.

49. A non-volatile semiconductor memory device according to

claim 46, wherein the memory device further includes a plurality of main bit lines, each of main bit lines being electrically connected to each of said bit lines through a

selector transistor.

50. A non-volatile semiconductor memory device according to

claim 46, wherein the first time constant based on the

capacitance component of said bit line and the equivalent

resistance due to the current from said current supply means

is smaller than the second time constant based on the capacitance component of said bit line and the equivalent

resistance due to said leak current, and the first time

constant is longer than the half of the period of said

signal.

51. A non-volatile semiconductor memory device according to

claim 46, wherein said current supply means includes a resistor connected to a voltage source or a resistor

connected in series to a switch.

52. A non-volatile semiconductor memory device according to

claim 46, wherein said current supply means includes a diode

reverse-bias connected to a voltage source or a diode reverse-bias connected in series to a switch.

53. A non-volatile semiconductor memory device according to

claim 46, wherein said current supply means includes a gate- equipped diode connected to a voltage source or a gate-

equipped diode connected in series to a switch.

54. A non-volatile semiconductor memory device according

claim 46, wherein said current supply means is connected

between a main bit line and a bit line.

55. A non-volatile semiconductor memory device according to

claim 46, wherein said signal includes a plurality of

positive peak potentials.

56. A non-volatile semiconductor memory device according to claim 46, wherein said signal includes a plurality of negative peak potentials.

57. A non-volatile semiconductor memory device according to

claim 46, wherein said signal includes a plurality of

positive peak potential.

58. A NAND type non-volatile semiconductor memory device

comprising:

a bit line,

select lines and word lines intersecting said bit l ine ;

memory cells connected in series between a first and a

second select transistor, each of memory cells having a

source, a drain, a control gate and a floating gate, the

control gate thereof being connected to each of said word lines; and

means for applying a signal varying a positive peak

potential and a negative peak potential to any of said

memory cells so that the threshold voltage thereof is

converged.

59. A non-volatile memory cell including a transistor

having a floating gate and a control gate comprising:

a capacitor element electrically connected to one of

a drain electrode and a source electrode of said transistor; potential setting means for charging the said capacitor

element to set one of said source electrode and drain

electrode at a potential higher than that of the other; and voltage generating means for applying an AC voltage to

said control gate.

60. A non-volatile memory cell according to claim 59,

wherein said voltage generating means alternately generates a positive voltage and a negative voltage so that the said

positive voltage is applied precedingly to said negative

voltage to said control gate.

61. A non-volatile memory cell according to claim 59,

wherein said capacitor element includes a parasitic element

contained in a wiring electrically connected to said one of

the drain electrode and source electrode of said transistor.

62. A method of adjusting the threshold value of a non¬ volatile memory cell including a transistor having a floating gate and a control gate, comprising the steps of:

a first step of maintaining one of a drain electrode and a source electrode of said transistor at the potential

higher than that at the other; and a second step of applying an AC voltage to said control gate to reduce the potential at the drain electrode.

63. A method of adjusting the threshold values of a

plurality of transistors each having a floating gate and a

control gate, comprising the steps of: a first step of maintaining one of a drain electrode

and a source electrode of each of said transistors at the potential higher than that at the other;

a second step of applying a positive voltage at said

control gate to cause the transistors each having a threshold value no larger than the value determined in

relation to said positive voltage; and

a third step of applying a negative voltage to the

control gate of each of the transistors each having a

threshold value larger than the value determined in relation

to said negative voltage so as to reduce the threshold value of each of the transistors, said second step and said third step being alternately

repeated until all the threshold values of said plurality of

transistors are converged into a desired value or desire

range determined in relation to said positive voltage.

64. A method of adjusting the threshold value of each of a

plurality of transistors each having a floating gate and a

control gate, comprising the steps of: a first step of setting the threshold value of each of

said plurality of transistors; a second step of maintaining one of a drain electrode

and a source electrode of a specific transistor of said

transistors at the potential higher than that at the other; /27295

117

and

a third step of applying an AC voltage to the control

gate of said specific transistor to set the threshold value

of said specific transistor at a lower value.