WO1994022169A1 - Bright field wafer target - Google Patents
Bright field wafer target Download PDFInfo
- Publication number
- WO1994022169A1 WO1994022169A1 PCT/US1994/002830 US9402830W WO9422169A1 WO 1994022169 A1 WO1994022169 A1 WO 1994022169A1 US 9402830 W US9402830 W US 9402830W WO 9422169 A1 WO9422169 A1 WO 9422169A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- alignment marks
- layer
- alignment
- target
- target area
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Definitions
- This invention relates generally to processing integrated circuits and more particularly to auto alignment marks used to align layer placement during processing of wafers.
- targets are placed to assure each layer is properly aligned with respect to prior layers.
- ahgnment marks are placed.
- Layers placed subsequent to the alignment marks utilize the alignment marks for proper placement.
- the subsequent layer can then be aligned to the mark within an alignment error.
- the alignment error results from the error tolerances of the processing devices. See for example, Canon Reticle Alignment for Canon I-2000/I-2500 Stepper Model, available from Canon U.S.A. having a business address of 2051 Mission College Blvd., Santa Clara, CA 95054.
- each lay ⁇ ay include alignment marks for each target.
- Each layer is aligned using alignment marks composed of material from the immediately prior layer. This guarantees that immediately adjacent layers are misaligned at most an amount equal to the alignment error.
- use of such a sequential mark alignment system may result in a "walking error" wherein misalignment between layers which are not immediately adjacent to one another can be significantly larger than the alignment error.
- a target used in alignment of layers on a wafer is presented.
- alignment marks are placed within a target area.
- the alignment marks are composed of material from a first layer placed on the wafer.
- alignment marks composed of material from the subsequent layers are placed within the target area.
- alignment marks composed of material from a second layer are each placed adjacent to one of the alignment marks composed of material from the first layer.
- Alignment marks composed of material from a third layer are each placed adjacent to one of the alignment marks composed of material from the second layer.
- Alignment marks composed of material from a fourth layer are each placed adjacent to one of the alignment marks composed of material from the third layer. And so on.
- the alignment marks are each rectangular in shape.
- the resulting composite target utilizes visible alignment marks for a multitude of layers. This combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme.
- the present invention is advantageous over the sequential mark alignment scheme as the present invention does not require a new target for every layer, thus saving space in the scribe lines.
- Figure 1 shows two targets on the scribe lines of the device area on a wafer in accordance with the prior art.
- Figure 2 shows alignment marks from a first layer placed on a target in accordance with the preferred embodiment of the present invention.
- Figure 3 shows alignment marks from a second layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
- Figure 4 shows alignment marks from a third layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
- Figure 5 shows alignment marks from a fourth layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
- Figure 6 shows ahgnment marks from a fifth layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
- Figure 1 shows a target 9 and a target 10 on the scribe line of device area 8 of a wafer being processed in accordance with the prior art.
- target 9 and target 10 are, for example, 120 micrometers by 50 micrometers.
- a composite wafer target is partially built at each layer where an etch is performed.
- the layers may be composed of oxide, polysilicon, metal or some other material used in processing wafers.
- Figures 2 through 6 show processing stages of the composite wafer target in accordance with the preferred embodiment of the present invention. The particular composite wafer target shown being processed is for a process in which five layers are etched.
- Figure 2 shows target area 10 after a first layer is etched. After etching the first layer, alignment marks 11 are exposed within target area 10. Outside lines 22 from the first layer are also exposed. Each of alignment marks 11, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, Alignment marks 11 are separated from each other by a distance of, for example, 20 micrometers. While only 20 of alignment marks 11 are shown, a typical target may have, for example, more (or less) than twenty alignment marks for each layer.
- Figure 3 shows target area 10 after a second layer is etched. After etching the second layer, alignment marks 12 are exposed within target area 10. Outside lines 23 from the second layer are also exposed. Outside lines 23 are placed directly over outside lines 22.
- Each of alignment marks 12, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 12 is immediately adjacent to one of alignment marks 11.
- Figure 4 shows target area 10 after a third layer is etched. After etching the third layer, alignment marks 13 are exposed within target area 10. Outside lines 24 from the second layer are also exposed. Outside lines 24 are placed directly over outside lines 23. Each of alignment marks 13, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 13 is immediately adjacent to one of alignment marks 12.
- Figure 5 shows target area 10 after a fourth layer is etched. After etching the fourth layer, alignment marks 14 are exposed within target area 10. Outside lines 25 from the second layer are also exposed. Outside lines 25 are placed directly over outside lines 24. Each of alignment marks 14, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 14 is immediately adjacent to one of alignment marks 13.
- Figure 6 shows target area 10 after a fifth layer is etched. After etching the fifth layer, alignment marks 15 are exposed within target area
- Each of alignment marks 15 has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 5 is immediately adjacent to one of alignment marks 14.
- Embodiments of targets in accordance with the present invention may vary significantly.
- the exact size of each alignment mark is not significant. Therefore, the height and/or width of alignment marks can vary from layer to layer. Likewise, the distance between the alignment can be varied to account for the addition alignment marks from more than (or less than) five layers.
- the outside lines on the left and the right of the alignment marks are used to minimize resist pile up over the target. These all overlap at each masking layer. Even if the lines are broken, this will not impact the alignment of the layers.
- the present invention presents a composite target in which alignment marks for each layer are visible for use in the alignment of subsequent layers.
- This system combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme.
Abstract
A composite target used in alignment of layers (22-26) on a wafer uses alignment marks placed in a target area (9, 10). First alignment marks (11) are composed of material from a first layer (22) placed on the wafer. As subsequent layers (22-26) are placed on the wafer, alignment marks composed of material from the subsequent layers (23-26) are placed within the target area (9, 10). For example, alignment marks (12) composed of material from a second layer (23) are each placed adjacent to one of the alignment marks composed of material from the first layer (22). Alignment marks (13) composed of material from a third layer (24) are each placed adjacent to one of the alignment marks composed of material from the second layer (23). Alignment marks (14) composed of material from a fourth layer (25) are each placed adjacent to the alignment marks composed of material from the third layer (24). And so on. The alignment marks (11-15) are, for example, each rectangular in shape.
Description
BRIGHT FIELD WAFER TARGET
Technical Field
This invention relates generally to processing integrated circuits and more particularly to auto alignment marks used to align layer placement during processing of wafers.
When processing wafers, targets are placed to assure each layer is properly aligned with respect to prior layers. Within the targets, ahgnment marks are placed. Layers placed subsequent to the alignment marks, utilize the alignment marks for proper placement. The subsequent layer can then be aligned to the mark within an alignment error. The alignment error results from the error tolerances of the processing devices. See for example, Canon Reticle Alignment for Canon I-2000/I-2500 Stepper Model, available from Canon U.S.A. having a business address of 2051 Mission College Blvd., Santa Clara, CA 95054.
For example, in a first layer, master marks may be placed in each target. Subsequent layers are all aligned to these first layer master marks. This assures that every layer subsequent to the first layer will be aligned to the first layer within the alignment error. However, one problem with such a master mark alignment system is that the total alignment errors between layers other than the first layer is the square root of two times the alignment error. Thus immediately adjacent layers may be misaligned an amount up to the square root of two times the alignment error. In some processes this amount of error between adjacent layers may be excessive. Alternately, each layατ ay include alignment marks for each target.
Each layer is aligned using alignment marks composed of material from the immediately prior layer. This guarantees that immediately adjacent layers are misaligned at most an amount equal to the alignment error.
However, use of such a sequential mark alignment system may result in a "walking error" wherein misalignment between layers which are not immediately adjacent to one another can be significantly larger than the alignment error.
Disclosure of the Invention
In accordance with the preferred embodiment of the present invention, a target used in alignment of layers on a wafer is presented. Within a target area, alignment marks are placed. The alignment marks are composed of material from a first layer placed on the wafer. Also within the target area, as subsequent layers are placed on the wafer, alignment marks composed of material from the subsequent layers are placed within the target area. For example, alignment marks composed of material from a second layer are each placed adjacent to one of the alignment marks composed of material from the first layer. Alignment marks composed of material from a third layer are each placed adjacent to one of the alignment marks composed of material from the second layer. Alignment marks composed of material from a fourth layer are each placed adjacent to one of the alignment marks composed of material from the third layer. And so on. In the preferred embodiment of the present invention, the alignment marks are each rectangular in shape.
The resulting composite target utilizes visible alignment marks for a multitude of layers. This combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme. The present invention is advantageous over the sequential mark alignment scheme as the present invention does not require a new target for every layer, thus saving space in the scribe lines.
Brief Description of the Drawings
Figure 1 shows two targets on the scribe lines of the device area on a wafer in accordance with the prior art.
Figure 2 shows alignment marks from a first layer placed on a target in accordance with the preferred embodiment of the present invention.
Figure 3 shows alignment marks from a second layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
Figure 4 shows alignment marks from a third layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
Figure 5 shows alignment marks from a fourth layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention. Figure 6 shows ahgnment marks from a fifth layer added to the target shown in Figure 1 in accordance with the preferred embodiment of the present invention.
Description of the PrefcrnM. TCn-ihoftinwi.* Figure 1 shows a target 9 and a target 10 on the scribe line of device area 8 of a wafer being processed in accordance with the prior art. Each of target 9 and target 10 are, for example, 120 micrometers by 50 micrometers.
In the preferred embodiment, a composite wafer target is partially built at each layer where an etch is performed. For example the layers may be composed of oxide, polysilicon, metal or some other material used in processing wafers. Figures 2 through 6 show processing stages of the composite wafer target in accordance with the preferred embodiment of the
present invention. The particular composite wafer target shown being processed is for a process in which five layers are etched.
Figure 2 shows target area 10 after a first layer is etched. After etching the first layer, alignment marks 11 are exposed within target area 10. Outside lines 22 from the first layer are also exposed. Each of alignment marks 11, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, Alignment marks 11 are separated from each other by a distance of, for example, 20 micrometers. While only 20 of alignment marks 11 are shown, a typical target may have, for example, more (or less) than twenty alignment marks for each layer.
Figure 3 shows target area 10 after a second layer is etched. After etching the second layer, alignment marks 12 are exposed within target area 10. Outside lines 23 from the second layer are also exposed. Outside lines 23 are placed directly over outside lines 22. Each of alignment marks 12, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 12 is immediately adjacent to one of alignment marks 11.
Figure 4 shows target area 10 after a third layer is etched. After etching the third layer, alignment marks 13 are exposed within target area 10. Outside lines 24 from the second layer are also exposed. Outside lines 24 are placed directly over outside lines 23. Each of alignment marks 13, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 13 is immediately adjacent to one of alignment marks 12. Figure 5 shows target area 10 after a fourth layer is etched. After etching the fourth layer, alignment marks 14 are exposed within target area 10. Outside lines 25 from the second layer are also exposed. Outside lines 25 are placed directly over outside lines 24. Each of alignment marks 14, for
example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 14 is immediately adjacent to one of alignment marks 13.
Figure 6 shows target area 10 after a fifth layer is etched. After etching the fifth layer, alignment marks 15 are exposed within target area
10. Outside lines 26 from the second layer are also exposed. Outside lines 26 are placed directly over outside lines 25. Each of alignment marks 15, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 5 is immediately adjacent to one of alignment marks 14.
Embodiments of targets in accordance with the present invention may vary significantly. For example, the exact size of each alignment mark is not significant. Therefore, the height and/or width of alignment marks can vary from layer to layer. Likewise, the distance between the alignment can be varied to account for the addition alignment marks from more than (or less than) five layers.
The outside lines on the left and the right of the alignment marks are used to minimize resist pile up over the target. These all overlap at each masking layer. Even if the lines are broken, this will not impact the alignment of the layers.
The present invention presents a composite target in which alignment marks for each layer are visible for use in the alignment of subsequent layers. This system combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme. The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics
thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
Claims
1. A method for producing a target (11-15) used in alignment of layers (22-26) on a wafer, the method comprising the steps of: (a) placing, within a target area (9,10), first alignment marks (11) composed of material from a first layer (22) placed on the wafer; and,
(b) placing, within the target area (9,10), subsequent alignment marks (12-15) composed of material from layers (22-26) placed on the wafer subsequent to the first layer (22), wherein the subsequent alignment marks (12-15) are placed in locations within the target area (9,10) which are different from locations within the target area (9,10) in which the first alignment marks (11) are placed.
2. A method as in claim 1 wherein step (b) includes the substeps of: (b.l) placing, within the target area (9,10), second alignment marks
(12) composed of material from a second layer (23) placed on the wafer subsequent to the first layer (22), each of the second alignment marks (12) being within the target area (9,10) and adjacent to one of the first alignment marks (11); and, (b.l) placing, within the target area (9,10), third alignment marks (13) composed of material from a third layer (24) placed on the wafer subsequent to the second layer (23), each of the third alignment marks (13) being within the target area (9,10) and adjacent to one of the second alignment marks (12).
3. A method as in claim 2 wherein step (b) additionally includes the substep of: (b.3) placing, within the target area (9,10), fourth alignment marks (14) composed of material from a fourth layer (25) placed on the wafer subsequent to the third layer (24), each of the fourth alignment marks (14) being within the target area (9,10) and adjacent to one of the third alignment marks (13).
4. A method as in claim 3 wherein the first alignment marks (11) placed in step (a) and the second, the third and the fourth alignment marks (12-14) placed in step (b) are each rectangular shaped.
5. A target (11-15) used in alignment of layers (22-26) on a wafer, the target (11-15) comprising: the steps of: first alignment marks (11) composed of material from a first layer (22) placed on the wafer placed within a target area (9,10) in the wafer; and, subsequent alignment marks (12-15) composed of material from layers (22-26) placed on the wafer subsequent to the first layer (22), the subsequent alignment marks (12-15) being placed in locations within the target area (9,10) which are different from locations within the target area (9,10) in which the first alignment marks (11) are placed.
6. A target (11-15) as in claim 5 wherein the subsequent alignment marks (12-15) include: second alignment marks (12) composed of material from a second layer (23) placed on the wafer subsequent to the first layer (22), each of the second alignment marks (12) being placed within the target area (9,10) adjacent to one of the first alignment marks (11); and, third alignment marks (13) composed of material from a third layer (24) placed on the wafer subsequent to the second layer (23), each of the third alignment marks (13) being placed within the target area (9,10) adjacent to one of the second alignment marks (12).
7. A target (11-15) as in claim 6 wherein the subsequent marks additionally include: fourth alignment marks (14) composed of material from a fourth layer (25) placed on the wafer subsequent to the third layer (24), each of the fourth alignment marks (14) being placed within the target area (9,10) adjacent to one of the third alignment marks (13).
8. A target (11-15) as in claim 7 wherein the first alignment marks (11), the second alignment marks (12), the third alignment marks (13) and the fourth alignment marks (14) are each rectangular shaped.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6521204A JPH08508366A (en) | 1993-03-25 | 1994-03-15 | Brightfield wafer target |
EP94911616A EP0691033A1 (en) | 1993-03-25 | 1994-03-15 | Bright field wafer target |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/036,786 US5316984A (en) | 1993-03-25 | 1993-03-25 | Bright field wafer target |
US08/036,786 | 1993-03-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994022169A1 true WO1994022169A1 (en) | 1994-09-29 |
Family
ID=21890647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1994/002830 WO1994022169A1 (en) | 1993-03-25 | 1994-03-15 | Bright field wafer target |
Country Status (4)
Country | Link |
---|---|
US (1) | US5316984A (en) |
EP (1) | EP0691033A1 (en) |
JP (1) | JPH08508366A (en) |
WO (1) | WO1994022169A1 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2790416B2 (en) * | 1993-08-26 | 1998-08-27 | 沖電気工業株式会社 | Alignment mark placement method |
US5545593A (en) * | 1993-09-30 | 1996-08-13 | Texas Instruments Incorporated | Method of aligning layers in an integrated circuit device |
US6327513B1 (en) * | 1998-04-16 | 2001-12-04 | Vlsi Technology, Inc. | Methods and apparatus for calculating alignment of layers during semiconductor processing |
US6350548B1 (en) | 2000-03-15 | 2002-02-26 | International Business Machines Corporation | Nested overlay measurement target |
JP2003532306A (en) * | 2000-05-04 | 2003-10-28 | ケーエルエー・テンコール・テクノロジーズ・コーポレーション | Method and system for lithographic process control |
US7541201B2 (en) | 2000-08-30 | 2009-06-02 | Kla-Tencor Technologies Corporation | Apparatus and methods for determining overlay of structures having rotational or mirror symmetry |
US7317531B2 (en) * | 2002-12-05 | 2008-01-08 | Kla-Tencor Technologies Corporation | Apparatus and methods for detecting overlay errors using scatterometry |
US6782337B2 (en) | 2000-09-20 | 2004-08-24 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension an a presence of defects on a specimen |
US6919957B2 (en) * | 2000-09-20 | 2005-07-19 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension, a presence of defects, and a thin film characteristic of a specimen |
US7349090B2 (en) * | 2000-09-20 | 2008-03-25 | Kla-Tencor Technologies Corp. | Methods and systems for determining a property of a specimen prior to, during, or subsequent to lithography |
WO2002025708A2 (en) * | 2000-09-20 | 2002-03-28 | Kla-Tencor-Inc. | Methods and systems for semiconductor fabrication processes |
US7130029B2 (en) * | 2000-09-20 | 2006-10-31 | Kla-Tencor Technologies Corp. | Methods and systems for determining an adhesion characteristic and a thickness of a specimen |
US6812045B1 (en) | 2000-09-20 | 2004-11-02 | Kla-Tencor, Inc. | Methods and systems for determining a characteristic of a specimen prior to, during, or subsequent to ion implantation |
US6891627B1 (en) | 2000-09-20 | 2005-05-10 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension and overlay of a specimen |
US7106425B1 (en) | 2000-09-20 | 2006-09-12 | Kla-Tencor Technologies Corp. | Methods and systems for determining a presence of defects and a thin film characteristic of a specimen |
US6694284B1 (en) | 2000-09-20 | 2004-02-17 | Kla-Tencor Technologies Corp. | Methods and systems for determining at least four properties of a specimen |
US6673637B2 (en) | 2000-09-20 | 2004-01-06 | Kla-Tencor Technologies | Methods and systems for determining a presence of macro defects and overlay of a specimen |
US20030002043A1 (en) * | 2001-04-10 | 2003-01-02 | Kla-Tencor Corporation | Periodic patterns and technique to control misalignment |
US7440105B2 (en) * | 2002-12-05 | 2008-10-21 | Kla-Tencor Technologies Corporation | Continuously varying offset mark and methods of determining overlay |
US20120049186A1 (en) * | 2010-08-31 | 2012-03-01 | Li Calvin K | Semiconductor structures |
US10451412B2 (en) | 2016-04-22 | 2019-10-22 | Kla-Tencor Corporation | Apparatus and methods for detecting overlay errors using scatterometry |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4343877A (en) * | 1981-01-02 | 1982-08-10 | Amdahl Corporation | System for design and production of integrated circuit photomasks and integrated circuit devices |
EP0061536A1 (en) * | 1980-12-29 | 1982-10-06 | Fujitsu Limited | Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2642634A1 (en) * | 1976-09-22 | 1978-03-23 | Siemens Ag | METHOD OF ADJUSTING EXPOSURE MASKS RELATIVE TO A SUBSTRATE DISC |
JPS59224123A (en) * | 1983-05-20 | 1984-12-17 | Oki Electric Ind Co Ltd | Alignment mark for wafer |
JPS6042828A (en) * | 1983-08-18 | 1985-03-07 | Nec Corp | Method for aligning mask |
JPS60211838A (en) * | 1984-04-05 | 1985-10-24 | Nec Corp | Automatic aligning mark for optical exposure |
JPH01162330A (en) * | 1987-12-18 | 1989-06-26 | Matsushita Electron Corp | Manufacture of semiconductor device |
-
1993
- 1993-03-25 US US08/036,786 patent/US5316984A/en not_active Expired - Fee Related
-
1994
- 1994-03-15 EP EP94911616A patent/EP0691033A1/en not_active Withdrawn
- 1994-03-15 JP JP6521204A patent/JPH08508366A/en active Pending
- 1994-03-15 WO PCT/US1994/002830 patent/WO1994022169A1/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0061536A1 (en) * | 1980-12-29 | 1982-10-06 | Fujitsu Limited | Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method |
US4343877A (en) * | 1981-01-02 | 1982-08-10 | Amdahl Corporation | System for design and production of integrated circuit photomasks and integrated circuit devices |
Non-Patent Citations (2)
Title |
---|
G.F. DOLAN ET AL.: "Split Field Alignment Marks", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 18, no. 10, March 1976 (1976-03-01), NEW YORK US, pages 3306 * |
S. MAGDO: "Registering Marks for Semiconductor Fabrication Masks", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 13, no. 4, September 1970 (1970-09-01), NEW YORK US, pages 955 - 956 * |
Also Published As
Publication number | Publication date |
---|---|
EP0691033A1 (en) | 1996-01-10 |
JPH08508366A (en) | 1996-09-03 |
US5316984A (en) | 1994-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5316984A (en) | Bright field wafer target | |
EP0405585B1 (en) | A method of manufacturing a semiconductor device | |
US4388386A (en) | Mask set mismatch | |
US20060017074A1 (en) | Raised-lines overlay semiconductor targets and method of making the same | |
US5946583A (en) | Method for preventing alignment marks from disappearing after chemical mechanical polishing | |
EP0780886B1 (en) | Method of aligning layers in a semiconductor device | |
US6828071B2 (en) | Method of aligning a wafer and masks | |
US4690880A (en) | Pattern forming method | |
US20040140052A1 (en) | Method for aligning key in semiconductor device | |
US6531374B2 (en) | Overlay shift correction for the deposition of epitaxial silicon layer and post-epitaxial silicon layers in a semiconductor device | |
JP3080400B2 (en) | Semiconductor device | |
US7390722B1 (en) | System and method for using an oxidation process to create a stepper alignment structure on semiconductor wafers | |
US5338397A (en) | Method of forming a semiconductor device | |
EP0286086A3 (en) | Electron beam drawing method | |
US6228705B1 (en) | Overlay process for fabricating a semiconductor device | |
CN110865519B (en) | Method for aligning wafer in photoetching process | |
JPS5963728A (en) | Manufacture of semiconductor device | |
JPH07321015A (en) | Manufacture of semiconductor device | |
US20030068580A1 (en) | Ceramic shadow-mask in IC process flow | |
JPS5835538A (en) | Production for pattern mask | |
JPH07161618A (en) | Alignment mark and photo-mask having alignment mark | |
US20030013303A1 (en) | Full image exposure of field with alignment marks | |
JPH0357269A (en) | Manufacture of semiconductor device | |
JPH0544815B2 (en) | ||
JPS5856333A (en) | Formation of key pattern for mask alignment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1994911616 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1994911616 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1994911616 Country of ref document: EP |