WO1994011936A1

WO1994011936A1 - Switching arrangement

Info

Publication number: WO1994011936A1
Application number: PCT/GB1993/002249
Authority: WO
Inventors: Dennis Malcolm Pryor; Michael Challis
Original assignee: Raychem Limited
Priority date: 1992-11-12
Filing date: 1993-11-02
Publication date: 1994-05-26
Also published as: HUT73624A; HU9501359D0; TW280046B; TR28861A; BR9307421A; GB9223773D0; FI952317A; FI952317A0; RU95112565A; AU5375094A; NO951862L; CN1089403A; IL107573A0; NO951862D0; EP0669049A1; CA2148362A1; BG99627A; PL308764A1; CZ124695A3; MX9307078A

Abstract

An arrangement for connection in an electrical circuit, which comprises: (1) a pair of FETs that are series connected in a line of the circuit with their sources connected together or with their drains connected together and whose states can be altered by means of a voltage acting on their gates; (2) a control connected to the gate of at least one of the FETs; the control being responsive to an overcurrent on the line thereby altering the states of at least one of the FETs.

Description

SWITCHING ARRANGEMENT

This arrangement relates to protection of electrical circuits from overcurrents, for example from overcurrents caused by equipment faults, electrostatic discharge or other threats. The arrangement is preferably bidirectional, ie can deal with currents flowing in either direction through it, and can preferably deal with alternating currents. In general, the arrangement can act as a switch that is closed under normal operating conditions and that opens in response to an overcurrent fault. The arrangement is particularly useful in communication lines that have a DC bias from which a voltage may be generated.

One circuit protection arrangement of relatively simple form is described in German Patent Application No. 37 25 390 dated 31st July 1987 to Wickmann-Werke GmbH. This arrangement comprises a series switching transistor that controls the circuit current and a control transistor that controls the base or gate voltage of the switching transistor. The base or gate voltage of the control transistor is set by a voltage divider that spans the switching transistor, so that, if the arrangement experiences an overcurrent, the control transistor will be biased into conduction and will turn the switching transistor OFF. Although this arrangement is particularly simple, it is not bidirectional and it suffers from the disadvantage that in normal operation there will always be a significant voltage drop across the arrangement before it will conduct current, this voltage drop being due to the base-emitter junction voltage of the switching transistor added to the voltage drop across the base resistor in the case of bipolar arrangements.

We have now designed a circuit protection arrangement that is bidirectional and that in preferred embodiments at least can provide protection in AC circuits, and in particular we have designed a circuit

SUBSTITUTE SHEET protection switch employing a pair of field-effect transistors (FETs), preferably arranged so that for any voltage across the arrangement one is forward biased and one is reverse biased.

Thus, the present invention provides an arrangement for connection in an electrical circuit, which comprises:

( 1 ) a pair of FETs that are series connected in a line of the circuit with their sources connected together or with their drains connected together and whose states can be altered by means of a voltage (generally by means of a replacement of one voltage by another) acting on their gates;

(2) a control connected to the gates of at least one of (preferably both of) the FETs;

the control being responsive to an overcurrent on the line thereby altering the states of the FETs.

The arrangement is preferably not merely current-limiting (ie allowing increased current with increased voltage drop across the arrangement up to a certain voltage drop beyond which the current remains constant), but rather causes a reduction in current once some threshold voltage across it has been reached. That voltage drop will in general result from a current flowing through the resistance of the arrangement, and then an overcurrent will produce a significant reduction in subsequent current flow. This behaviour may be regarded as "foldback", although the degree of foldback may be less than 100%.

The behaviour of a FET alone may be regarded as current- limiting, ie its ID (drain current) versus VΓJS (drain-source voltage)

SUBSTITUTE SHEET curve shows an increase from Nos = 0 to some threshold value at which the value of lp levels off. A series of such curves exist for different values of VQS (gate-source voltage).

The function of the control is preferably to make VQS more negative (in the case of an n-channel FET) as V^s increases (and therefore as current flowing through the arrangement increases) thus shifting the operating point from one Ip - Nos curve to another as the current increases. The result is to cause foldback behaviour.

The way in which this is done will in general differ for enhancement-mode and depletion mode n-channel FETs. An enhancement mode FET requires a bias for normal conduction, and hence the function of the control will be to remove this bias, for example reducing N^s from, say, 5 volts to zero volts. A depletion mode FET on the other hand conducts with VQ$ = 0 volts, and here the control will serve to reduce VQS ^t0 _' ^say> ~5 volts.

The control may comprise a switch that applies a negative voltage (in the case of n-channel depletion mode FETs) or that shorts or otherwise removes a positive voltage (in the case of n-channel enhancement mode FETs), and it may do this substantially instantaneously gradually depending on the speed of foldback required. The control may comprise a transistor whose resistance comprises the switch.

The situation is reversed in the case of p-channel FETs, where application of a more positive voltage to the gate (from say -5N to OV for an enhancement mode FET, and from say ON to +5N for a depletion mode FET) will cause the FET to turn off.

The gate or base voltage of the transistor, the value of which determines that resistance, can be made automatically dependent on

SUBSTITUTE SHEET the voltage drop across the arrangement, and therefore on the current whose value is to be controlled.

The foldback process may involve positive feedback and therefore be very rapid. In general, the channel resistance of a FET increases as the gate voltage is made more negative, in the case of an n-channel FET, or more positive in the case of a p-channel FET. Also, it is the voltage drop across the FETs, which is itself a function of channel resistance, which forms the input into the control, the output of which is the value of VQS - Thus, an overcurrent is registered by the control as a voltage drop across the FETs and this causes VQS to be altered. An alteration in VQS results in a greater channel resistance, which increases the voltage drop across the FETs, which in turn further alters VQ - and so on.

When we refer to the FETs being connected together we include the possibility of other components such as a resistor being connected between them. Any such resistor preferably has a resistance of less than 100 KO and more preferably is substantially 0Ω .

We prefer that the FETs be arranged with their sources, rather than drains, connected together since that allows their gates to be connected together for control by a single voltage signal. This is because it is the gate-source (rather than gate-drain) voltage that controls the source-drain resistance and hence the resistance of the arrangement. If the drains are connected together, the sources will be at mutually different voltages, and if each gate-source voltage is to be correct then the two gate voltages will, in general, be different.

The arrangement is preferably used for overcurrent protection and/or remote switching in a telecommunications line, such as a telephone line, or other communications line. The arrangement may

SUBSTITUTE SHEET comprise a first pair of FETs ( 1) and control (2) connected in one conductor of the line, and a second pair of FETs ( 1) and control (2) connected in a second conductor of the line. Additionally, a shunt switch may be provided that will interconnect conductors of the line, thereby for example shunting an overvoltage across a telephone or other load in the circuit, or that will connect either conductor to an earth. Such a shunt switch may be activated by the or another control.

The invention also provides a telecommunications system or other system comprising a communications line and an arrangement of the invention in which the voltage is generated from a DC bias on the line. The invention further provided terminal equipment, for example a telephone, computer, network interface device or exchange switch, incorporating an arrangement of the invention.

In general, each FET of the pair may comprise an enhancement mode FET or each may comprise a depletion mode FET, either of which may be an n-channel or p-channel FET. An enhancement mode FET will be normally switched off, and a voltage will normally be needed to bias it into conduction. The control may then serve to remove that bias voltage in response to an overcurrent and optionally also in response to a separate gating signal. This may be done by opening a switch that connects the bias voltage to the FETs or by shorting the gates and sources of the FETs.

Depletion mode FETs are normally switched on and in this case the control may serve to connect a bias voltage to the FETs in response to an overcurrent and optionally also in response to a separate gating signal.

A mixture of one enhancement mode and one depletion mode FET is not at present preferred since the control required will have to

SUBSTITUTE SHEET act in opposite sense for each FET and will therefore be more complex.

In a preferred embodiment there is provided an arrangement that can be series connected in a line of an electrical circuit for protecting the circuit from an overcurrent, which comprises:

(i) a pair of enhancement mode FETs (preferably n-channel) that are series connected in the line with their sources connected together and can be biased into conduction by means of a voltage source acting on their gates;

(ii) a pair of control transistors, each control transistor being connected between the gate and source of one of the FETs;

the control transistors being biased into conduction when the arrangement experiences an overcurrent so that the FETs are switched off.

The invention has the advantage that the voltage drop appearing across the arrangement can be low, that the arrangement can deal with current in either direction and in preferred embodiments that the switch can be actuated remotely by altering the output of the voltage source.

It is quite possible to form an arrangement having a voltage drop of not more than I N, e.g. not more than 0.6N and especially about 0.5N at a line current of 50mA. This voltage drop is due to the channel resistance of the forward biased FET and the voltage drop across the parasitic diode present in the reversed biased FET. Of course, a FET having a lower channel resistance will have a lower voltage drop for the same current. Normally the parasitic diodes are relatively leaky (which is preferred) so that, at 50mA, the voltage

SUBSTITUTE SHEET drop across the parasitic diode is only about 0.1N. At least in the case of enhancement mode FETs, when the gate is forward biased and the drain-source current is reversed, the parasitic diodes exhibit substantially linear characteristics rather than a typical non-linear diode characteristic. Also the arrangement can be employed directly in a.c. circuits, thereby obviating the need for a rectifying bridge (which would increase the voltage drop by a further 1.3V).

As mentioned above, the arrangement preferably exhibits a "foldback" characteristic, that is to say, one in which the current that passes through the arrangement increases with increasing voltage difference across it until a certain voltage, referred to as the threshold voltage, is reached whereupon the current through the device decreases to a lower value. Normally the ratio of the maximum leakage current of the device in its off state to the maximum current of the device in its on state (trip current) is not more than 0.5, more preferably not more than 0.1 and especially not more than 0.01. In may cases the ratio can be lower than 10^-4. It is possible, depending on the mechanism of operation of the device that biases the FET, for the arrangement to have a "slow" or a "fast" foldback characteristic. If the arrangement switches quickly from its on state to its off state, for example in less than 100 microseconds, then it can be said to exhibit a fast foldback characteristic, whereas if the transition between the on state and the off state takes longer it can be said to exhibit a slow foldback characteristic. Which characteristic is preferred will depend on the application of the circuit. For example an arrangement that exhibits a fast foldback characteristic will generally let through less energy to the load when subjected to a current transient, whereas arrangements exhibiting slower foldback characteristics may be preferred if the circuit has a load having a significant inductance or if the arrangement needs to be insensitive to short current transients due, for example to equipment being switched on.

SUBSTITUTE SHEET The control transistors may be either bipolar transistors or FETs. The base or gate of each control transistor is normally held in a voltage divider that spans the arrangement. In this way, the voltage appearing across the arrangement due to the channel resistance etc. of the switching FETs will be passed to the base or gate of each control transistor.

When the base emitter junction voltage rises above 0.6V or the gate source voltage rises above the threshold voltage of the control transistor they will switch on and "short" the gate and source of the switching FET, thereby switching it off.

It is possible for the arrangement to be controlled remotely if desired, or it is possible for it to be connected to a fixed voltage source, in which case the arrangement will act merely as an overcurrent protection switch. The voltage source may, for example, be fixed by tying it to the line voltage (or a fraction of the line voltage) and optionally inverting it by means of a voltage doubling circuit or the like.

Although the arrangement defined above need only be a two terminal arrangement, it is possible also to form three terminal arrangements according to the invention where the third terminal switches on when an overcurrent is experienced in order to shunt the current across the load or to an earth terminal.

Five terminal protection arrangements for protecting a pair of lines, as commonly used in the telephone protection industry, may be formed employing a pair of overcurrent protection devices as described above which can employ either two devices for shunting the overcurrent to an earth terminal, and/or a single shunting device across the lines.

SUBSTITUTE SHEET The arrangement according to the invention is particularly suitable for use as a series switch in a maintenance termination unit (MTU). One such form of MTU whose features may be used in this invention is described in our copending British patent application 9223770 entitled "Transmission Line Testing Equipment" the disclosure of which is incorporated herein by reference.

That application claims a switching arrangement that can be connected in a communications channel that comprises a pair of lines between sets of terminal equipment, which comprises:

( 1 ) a series switch for connection in each of the lines, and preferably controlled by a voltage generator that takes its power from voltage appearing between the lines, the voltage generator preferably being controlled by a control circuit;

(2) a shunt switch for connection between the lines which may be located on the exchange side or on the subscriber side of the series switches; and

(3 ) the control circuit, the control circuit being able to actuate the series switches and the shunt switch on receipt of a signal sent along the channel;

wherein the control circuit can actuate both the shunt switch and the series switches on receipt of a single signal, but the shunt switch will remain closed over a different time period than that during which the series switches remain open, in order to allow different tests to be performed on the channel;

SUBSTITUTE SHEET if the shunt switch is on the exchange side of the series switches then, after the switches have been activated by the control circuit, the shunt switch will preferably open before the series switches close; and

if the shunt switch is on the subscriber side of the series switches then, after the switches have been activated by the control circuit, the series switches will preferably close before the shunt switch opens.

The present invention will now be illustrated by way of example with reference to the accompanying drawings, in which

Figure 1 is a circuit diagram of an arrangement employing two enhancement mode FETs;

Figure 2 is a circuit diagram of an arrangement employing two depletion mode FETs;

Figure 3 is a circuit diagram of an arrangement employing two pairs of FETs and two controls; and

Figure 4 is a circuit diagram showing the use of charge pumps.

Referring to figure 1 a switching arrangement for a circuit line 1 comprises a pair of n-channel enhancement-mode field effect transistors Ql and Q2 arranged with their sources connected together so that one of these transistors is always forward biased and the other is always reverse biased (but which is forward and which is reversed biased will depend on the polarity of the voltage on the line). When one of these FETs is reverse biased a current will flow through its "parasitic" drain-source diode, giving a very low voltage

SUBSTITUTE SHEET drop. This allows the circuit to exhibit a substantially linear a.c. characteristic.

The gates of the two FETs Ql and Q2 are connected together and this node is connected to a positive voltage source 2. The node is also connected to the sources of the two FETs Ql and Q2 via a 10MO resistor Rl in order to prevent the gate terminals floating.

A pair of NPN bipolar control transistors Q3 and Q4, preferably with their emitters connected together, are included so that each transistor Q3 and Q4 is connected between the gate and source terminals of a respective FET, Q l and Q2. The bases of the bipolar transistors are held in a pair of voltage dividers formed from resistors R2, R3, R4 and R5, each voltage divider spanning one of the FETs Ql and Q2.

In operation, if the voltage source 2 is powered, the FETs Ql and Q2 are biased into conduction so that current can flow in the line, current flowing through the parasitic diode of the reverse biased FET. If an overcurrent is experienced, the base-emitter voltages of the control transistors Q3 and Q4 will rise to about 0.7V and these transistors will be switched on, thereby shorting the gates and sources of FETs Ql and Q2 and switching them off, thus breaking the line and protecting any equipment connected to it. The current flow may also, if desired, be controlled by altering the voltage of the voltage source 2.

The arrangement will remain in the off state even when the overcurrent has passed because the whole system voltage will then be dropped across the arrangement, thereby ensuring that the control transistors remain on. In this state the only leakage current is that due to the four series connected resistors R2 to R5. This leakage current may be reduced to a satisfactorily small value by

SUBSTITUTE SHEET chosing high resistances, such as 1 MΩ for each of resistors R2 to R5. The arrangement may be reset simply by removing the line voltage, which will cause the control transistors Q3 and Q4 to turn off.

Capacitors (not shown) may be connected in parallel with resistors R2 and R4 in order to prevent the arrangement switching off when power is initially applied to the line and to prevent spurious current spikes that normally appear on the line from activating the overcurrent control transistors Q3 and Q4.

Although the device has been described employing bipolar overcurrent control transistors Q3 and Q4, it is quite possible for field effect transistors, relays, comparators or other devices or circuitry to be employed instead.

Figure 2 shows an arrangement comprising two depletion mode FETs Q2 and Q3, and a control. The arrangement is inserted in a line 1. The control 3 comprises a rectifier Dl, D2, D3, D4, a regulator 4 and a negative voltage generator 5. The regulator 4 is made up of a FET Q l and a resistor Rl, and the negative voltage generator is based on a 7660 integrated circuit plus capacitors Cl and C2. A variable resistor RV1 is included so that the degree of foldback can be chosen by regulating the negative voltage applied to the gates of the FETs Q2 and Q3.

Current flows through the FETs Q2 and Q3 from a source connected to Jl to a load connected to J2 (the return line is not shown). This current flow causes a voltage drop across Q2 and Q3, which is substantially proportional to the current since the resistance characteristics of the pair of FETs is substantially linear. As in Figure 1, one FET is forward biased, and the other has a parasitic diode that allows current to flow in the reverse direction.

SUBSTITUTE SHEET A fault that results in an overcurrent causes a greater voltage to be developed across the FETs Q2 and Q3, and this is supplied to the negative voltage generator 5 of the control 3. Due to the rectifier Dl, D2, D3, D4 the negative voltage generator operates whichever direction of current flow occurs in the line 1 , and the arrangement will operate on AC lines.

When the intended trip value of the arrangement is reached the negative voltage generator 5 supplies the required negative bias to the gates of the FETs Q2 and Q3, turning them off. Thus, the line 1 is broken, protecting equipment connected to it.

Figure 3 shows a circuit comprising two arrangements substantially as shown in figure 1 , one in each of two lines, for example the tip and ring lines of a telecommunications system. In this circuit the bias voltages for the FETs are generated by opto¬ electronic devices 6. In some circumstances such opto-electronic devices will draw significant line currents, and where this is a problem we prefer that the bias voltages are provided by the use of voltage doublers or charge pumps, if necessary in conjunction with a voltage divider etc. A suitable circuit which fulfils our present preference for low current consumption is shown in figure 4, where the charge pump is shown as 7.

Components of various ratings may be used, but we prefer the following.

The FETs preferably have a current rating of greater than 1 mA, more preferably greater than 10 mA, especially greater than 100 mA, and preferably less than 500A, usually less than 10A, and often less than 1A. Various types of FETs including MOSFETs and JFETs and n-channel and p-channel types, including mixtures of these, can be used.

SUBSTITUTE SHEET Their channel resistances when switched on are preferably less than 1 KΩ , more preferably less than 10Ω . The on resistances will generally be greater than 2mΩ , often greater than l OOmΩ .

Preferred voltage ratings are 1500V to 20V, especially 400V-20V, and preferred power dissipation in between 1 KW and 200 mW, more usually from 1W to 100 mW.

A preferred gate threshold is between 10V and 0.8V, especially from 1 -4 V.

Bipolar transistors for the control preferably have the following characteristics:

VcEO (MAX) 20 - 400V IC(MAX) 100 mA - 500 mA h _fe 10 - 100.

SUBSTITUTE SHEET

Claims

1 . An arrangement for connection in an electrical circuit, which comprises:

( 1 ) a pair of FETs that are series connected in a line of the circuit with their sources connected together or with their drains connected together and whose states can be altered by means of a voltage acting on their gates:

(2) a control connected to the gate of at least one of the FETs;

the control being responsive to an overcurrent on the line thereby altering the states of at least one of the FETs.

2. An arrangement according to claim 1, in which each FET is an enhancement mode FET which can be biased into conduction by a voltage acting on its gate, which voltage can be removed by the control.

3. An arrangement according to claim 1, in which each FET is a depletion mode FET that can be switched off by the control.

4 An arrangement according to any preceding claim, in which the control is powered by the voltage drop across the arrangement.

5 An arrangement according to claim 4, in which the control comprises a pair of control transistors, each control transistor

SUBSTITUTE SHEET being connected between the gate and source of one of the FETs, the control transistors being biased into conduction when the arrangement experiences an overcurrent.

6. An arrangement according to claim 5, in which the FETs are enhancement mode FETs and the control transistors are so arranged that when they are conductive they short the gates and sources of the FETs.

7. An arrangement according to claim 5, in which the FETs are depletion mode FETs and the control transistors are so arranged that when they are conductive they connect a voltage source between the gates and sources of the FETs.

8. An arrangement according to claim 6 or 7, in which the base or gate of one or each control transistor is held in a voltage divider that spans the arrangement.

9. An arrangement according to any preceding claim, in which the control is additionally responsive to an external gating signal that changes the voltage on the gates thereby altering the states of the FETs.

10. An arrangement according to any preceding claim for connection in a communications line, which comprises a first pair of FETs (1) and control (2) connected in one conductor of the line and a second pair of FETs (1 ) and control (2) connected in a second conductor of the line.

1 . An arrangement according to any preceding claim for connection in a communications line, which additionally comprises a shunt switch that will interconnect conductors of

SUBSTITUTE SHEET the line or will interconnect a conductor of the line and an earth on activation by the or another control.

12. An arrangement according to any preceding claim, in which the control causes VQ$ of at least one n-channel FET to decrease as VDS of that FET increases, thereby causing that FET to exhibit foldback behaviour; or in which the control causes V_Q$ of at least one p-channel FET to increase as V^s of that FET increases, thereby causing that FET to exhibit foldback behaviour.

1 3. An arrangement according to claim 12, in which the foldback process involves positive feedback as a result of the channel resistance of the FET increasing with a change in the value of v_Gs-

14. A communications system comprising a communications line and an arrangement according to any preceding claim, in which the voltage is generated from a DC bias on the line.

15. Terminal equipment for a communications systems, incorporating an arrangement according to any of claims 1 -14.

SUBSTITUTE SHEET