WO1994006091A1 - Local area video network - Google Patents

Local area video network Download PDF

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Publication number
WO1994006091A1
WO1994006091A1 PCT/US1993/005604 US9305604W WO9406091A1 WO 1994006091 A1 WO1994006091 A1 WO 1994006091A1 US 9305604 W US9305604 W US 9305604W WO 9406091 A1 WO9406091 A1 WO 9406091A1
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WIPO (PCT)
Prior art keywords
data
high speed
recited
speed link
workstations
Prior art date
Application number
PCT/US1993/005604
Other languages
French (fr)
Inventor
John T. Kernan
Gregory Bestick
Jack Johnson
Original Assignee
Jostens Learning Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jostens Learning Corporation filed Critical Jostens Learning Corporation
Priority to AU46326/93A priority Critical patent/AU4632693A/en
Publication of WO1994006091A1 publication Critical patent/WO1994006091A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

Definitions

  • This invention relates in general to systems and methods for networking personal computers, and in particular, to a local area video network for networking an extensible number of personal computers and for providing each computer access to a large multimedia database.
  • multimedia The integration of text, graphics, digitized video, and sound into one database, commonly referred to as "multimedia”, was traditionally a function of mainframe and minicomputers. Nevertheless, powerful personal computers have emerged with the resources to create a multimedia experience.
  • LAN local area network
  • the X3T9.5 committee of the American National Standards Institute defined a set of protocols for a high speed network known as the Fiber Distributed Data Interface (FDDI).
  • the high speed network provides data throughput in excess of 100 mega-bits per second and can extend up to 100 kilometers.
  • the FDDI specification calls for a fiber-optic transmission medium in a ring topology and a token-passing protocol.
  • FDDI has long been considered the solution that solves the throughput requirement of the vast amounts of data required by multimedia applications. While FDDI has been known for years, it has been accompanied by a number of problems. High costs, lack of standards, and unavailability of components has limited the use of FDDI networks to areas where performance is key and cost is not a problem.
  • a backbone network is a primary network which interconnects a secondary network through gateways, bridges, and routers.
  • a gateway, bridge, or router acts as an internetworking module for integrating dissimilar LANs onto the high speed backbone and in effect, creating a hybrid network.
  • the router operates at the network layer. It intercepts and forwards data packets based on a network identifier. The router performs packet fragmentation and reassembly, packet control, and priority routing for internetworking the high speed network to a low speed LAN having a star topology.
  • a gateway operates in a similar manner to the router except that it internetworks the high speed network to a low speed LAN having a ring topology.
  • a bridge operates at the data-link layer. Each destination field on the high speed network is read and compared with an address table. The bridge then determines whether a data packet is for a particular workstation connected to the low speed end of the bridge.
  • the present invention discloses an economical local area video network which utilizes existing LAN technology for delivering multimedia information and which is extensible to a large number of PC workstations without the use of specialized hardware in each workstation.
  • the local area video network includes a redundant array of inexpensive disks (RAID) for storing the multimedia data.
  • the system further includes a media server coupled to the RAID through a disk interface for mapping logical data requests to physical data on the RAID.
  • the disk interface provides parallel access to data on the disks which in the aggregate, provides a large total bandwidth.
  • a high speed link having a ring topology couples the media server to unique time division multiple access (TDMA) control circuitry.
  • the TDMA circuitry transmits and receives data in a time division multiple access (TDMA) manner so that multiple PC workstations take advantage of the high throughput provided by the link.
  • TDMA time division multiple access
  • a star topology is provided between the TDMA circuitry and individual PC workstations.
  • the TDMA circuitry may further include means for reformatting the data in a traditional LAN protocol for delivery of the data to individual workstations.
  • a combination of elements provides a solution to coupling a large number of standard PC workstations having traditional type LAN interfaces to a media server.
  • the large number of standard PC workstations have access to a large multimedia database.
  • an economical system and method is provided to pack and unpack data from a star topology network onto a high speed, ring topology network.
  • TDMA circuitry is provided as an interface between a high speed ring network and a star network.
  • Another aspect of the invention is that a large number of PC workstations have substantially random and simultaneous access to a large multimedia database.
  • Yet still another aspect of the invention is that a local area video network is provided which is extensible to a large number of personal computers having standard interf ces.
  • Fig. 1 depicts an overall diagram of a local area video network in accordance with the principles set forth in the present invention
  • Fig. 2 depicts a data stream and a bit format of a packet control register for time division multiple access control in accordance with the principles set forth in the present invention
  • Fig. 3 is a more detailed view of an individual data packet within the data stream of Fig. 2;
  • Fig. 4 depicts the slot time logic for the time division multiple access control circuitry depicted in Fig 1;
  • Fig. 5 depicts the transmit portion of the packet control register of the time division multiple access control circuitry depicted in Fig. 1;
  • Fig. 6 depicts the receive portion of the packet control register of the time division multiple access control circuitry depicted in Fig. 1.
  • FIG. 1 wherein a local area video network 10 in accordance with the present invention is depicted.
  • server is used herein to denote a computer workstation configured to provide a specified service on the network.
  • a media server 12 includes a small computer system interface (SCSI) 14 for accessing and serving digital data representative of text, graphics, digitized video and audio signals.
  • SCSI 14 couples the media server 12 to a redundant array of inexpensive disks (RAID) 16.
  • RAID 16 is six disks wide.
  • Each disk within the RAID 16 provides a throughput of 24 MHz giving a total throughput to the media server 12 of 144 MHz.
  • the media server 12 has access and can serve 120 independent video strings at 1.2 MHz apiece.
  • a high speed data link 18 having a ring topology transmits and receives data at a high rate of speed between the media server 12 and time division multiple access (TDMA) control circuitry 20.
  • the link 18 may be, but is not limited to, a link in accordance with the fiber distributed data interface (FDDI) as described in the X3T9.5 standard set forth by the American National Standards Institute (ANSI) and herein incorporated by reference.
  • FDDI fiber distributed data interface
  • ANSI American National Standards Institute
  • the TDMA circuitry 20 is depicted in more detail in Figs. 4-6 and is more fully described herein below.
  • the physical layer of the high speed data link 18 is referenced to as an optical fiber cable.
  • the physical layer such as a shielded twisted pair or data-grade unshielded twisted pair wire.
  • a controller (not shown) is included within the media server 12 for adapting the data link 18 at the network layer to the particular bus configuration of the media server 12.
  • the bus configuration of the media server 12 may be, but is not limited to, the Industry Standard Architecture (ISA), the Extended Industry Standard Architecture (EISA), VME, VXI, or Multibus configurations.
  • the controller may include a processor unit and sufficient memory to relieve the media server 12 from overhead associated with the data link 18.
  • the TDMA circuitry 20 receives and transmits data in accordance with the protocols of the data link 18 and reformats the data for distribution to a plurality of PC workstations 22.
  • a TDMA protocol is practiced wherein a sync packet, a control register packet, and N data packets are included within the data stream.
  • the TDMA circuitry 20 internetworks the plurality of PC workstations 22 configured in a star topology to the link 18 configured as a ring. The internetworking between the media server 12 and the plurality of PC workstations 22 is accomplished in a manner which is transparent to the individual PCs.
  • the TDMA circuitry 20 is coupled to each of the plurality of PCs 22 through an individual full duplex link 24.
  • the link 24 may be a 10 Base- T twisted pair link as set forth by the Institute of Electrical and Electronic Engineers (IEEE) in the IEEE 802.3 standard, herein incorporated by reference.
  • Each link 24 is dedicated to the individual PC attached thereto for supplying the full bandwidth to that associated PC.
  • the usual delays associated network overhead such as carrier sense multiple access with collision detect (CSMA/CD) LANS, are not present and multimedia data can be sent and received at the full bandwidth rate of the link 24.
  • CSMA/CD carrier sense multiple access with collision detect
  • Fig. 2 depicts the data stream 26 and the bit format for a control register packet 28.
  • a sync packet 30 is included at the beginning of the data stream 26 for synchronizing the TDMA control circuitry 20 to the data stream 26 and for providing a timing reference.
  • the sync packet 30 is designated as the reference time slot and is used for correcting past variations in slot time and to signal a start of frame.
  • Each PC within the array of workstations 22 has an unique time slot (1-N) in reference to the sync packet 30.
  • Adjacent the sync packet 30 is a control register packet 28.
  • the control register packet 28 comprises a receive flag register (PCR RX) 32 and a transmit flag register (PCR TX) 34.
  • Individual bits within PCR RX 32 and PCR TX 34 correspond to each time slot of the workstations 22.
  • a bit indicates that a packet of data is ready to be transferred between the media server 12 and a particular PC within the array of workstations 22.
  • setting the i th bit in the PCR RX 32 register indicates to the controller in the media server 12 that the i th workstation has inserted data into its time slot.
  • setting the i th bit in the PCR TX 32 register indicates to the i th workstation that media server 12 through the controller has inserted data into its time slot.
  • TDMA time division multiple access
  • each packet of data served by the media server 12 is interleaved to contain multiple video and audio channels.
  • a representative i th data packet is depicted in Fig. 3.
  • the i th data packet contains a plurality of video and audio channels such as described by the Audio/Video Support System (AVSS) format.
  • Fig. 3 depicts two video (video A and video B) and two audio (audio A and audio B) channels.
  • AVSS Audio/Video Support System
  • a clock generator 36 has an input coupled to the serial data stream traveling on the link 18 and a clock output for providing a data clock signal 38 which assimilates the frequency and phase characteristics of the data stream.
  • the data clock signal 38 is a local timing reference used for among other things, to clock data in and out of data buffers. Many expedients are known for the clock generator 36. Such circuits may include voltage controlled oscillators, dividers and phase-locked loops. The particular detailed configuration of the clock generator 36 is not necessary for practicing the invention in accordance with the principals set forth. The structural details for such a circuit will be readily apparent to those skilled in the art having the benefit of the description herein.
  • the data clock signal 38 is applied to an input of a divider 44 having a divisor equal to the packet size.
  • the divider 44 has an output coupled to a clock input on shift register 46 for generating packet slot times.
  • Sync detector 40 has a first input to the data clock signal 38 and a second input coupled to the data stream.
  • the sync detector 40 compares the data stream to a predetermined data pattern for detecting a sync packet and has an output for generating a sync detect pulse 42 to initiate a start of frame sequence in response thereto.
  • the sync detect pulse 42 is coupled to a load input on shift register 46.
  • the shift register 46 is loaded and is sequenced by the divider 44 output for providing slot times 1 through N.
  • Slot time outputs 1-N are temporally spaced apart a time equal to the packet size and are in phase with packets 1-N on link 18.
  • the sync detect pulse 42 is delayed by PCR delay 45 to take into account the length of the control register packet 28.
  • Fig. 5 wherein the transmit portion (viewed from the media server side) of the TDMA control circuitry 20 is depicted.
  • the PCR TX 34 portion of the packet control register 48 indicates whether the media server 12 has placed a packet of data on link 18 for a select workstation.
  • the transmit portion will be described with respect to the i th workstation. It should be understood that the description of the i th workstation applies equally to all the other workstations and that redundant circuitry has been excluded for the sake of clarity.
  • the control register packet 28 in the data stream is clocked through the packet control register 48 by the data clock signal 38 in response to the presence of a sync detect pulse 42.
  • AND gate 50 enables input buffer 52 to fill with data from the data stream if the i th packet ready bit in the PCR TX 34 is set, the input buffer 52 is empty, and it is the i th slot time. AND gate 50 further resets the i th packet ready bit in the PCR TX 34 when the input buffer 52 is not empty to indicate to the media server 12 that the data packet has been read.
  • the input buffer 52 may be an accordion buffer having an auxiliary clock 54 applied to it for clocking the data to the i th workstation at a slower speed.
  • the auxiliary clock 54 is compatible data speeds set forth under IEEE 802.3.
  • the data stream passes through the packet control register 48 and is regenerated with the locally generated data clock 38 for reducing jitter in the data out stream 56.
  • Fig. 6 wherein the receive portion (viewed from the media server side) of the TDMA control circuitry 20 is depicted.
  • the PCR RX 32 portion of the packet control register 48 indicates to the media server 12 whether a select workstation has placed a packet of data on the link 18.
  • the receive portion will be described with respect to the i th workstation with the understanding that the description applies equally to all other workstations.
  • the packet ready bit for the i th workstation is clocked through the packet control register 48 by the data clock signal 38. If the output buffer 58 is full and the i th packet ready bit in the PCR RX 32 has been cleared by the media server 12 indicating that the server 12 has read the packet, AND gate 60 sets the i th packet ready bit in the PCR RX 32 to indicate to the media server 12 that a new data packet has been placed on the link 18. AND gate 62 enables tri-state driver 64 for driving the data stream with data stored in the output buffer 58 if the buffer full signal is activated and it is the i th slot time. Output buffer 58 sets the buffer full signal true when filled with data from the i th workstation. The auxiliary clock 54 is applied to output buffer 58 to clock the data in the buffer from the i th workstation at a slower speed.

Abstract

A local video network (10) is disclosed providing digitized video clips, traditional text, graphics, and sound for creating a true multimedia experience. The system is extensible to a large number of personal computers (22) and comprises a redundant array of inexpensive disks (16) for storing the multimedia data, a media server (12) coupled to the disks (16) through an interface (14) for mapping logical data requests to physical data, a high speed link, time division multiple access (TDMA) control circuitry (20) and a plurality of workstations (22) coupled to the TDMA control circuitry (20) for interacting with the multimedia data.

Description

LOCAL AREA VIDEO NETWORK
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates in general to systems and methods for networking personal computers, and in particular, to a local area video network for networking an extensible number of personal computers and for providing each computer access to a large multimedia database. 2. Description of Related Art
The integration of text, graphics, digitized video, and sound into one database, commonly referred to as "multimedia", was traditionally a function of mainframe and minicomputers. Nevertheless, powerful personal computers have emerged with the resources to create a multimedia experience.
The advantages of sharing resources among users such as a common multimedia database are known. One such advantage is the amortization of development costs and the variety of applications which can be supplied. While resource sharing is theoretically cost efficient, current systems and methods are either too narrow in bandwidth for real-time transfer of the large amounts of information required by multimedia applications or very expensive. It is known that a single digital video channel requires a bandwidth of 1.2 MHz while a digital audio channel requires about 0.12 MHz of bandwidth.
Known systems and methods such as an Ethernet (IEEE 802.3) or a Token Ring (IEEE 802.5) local area network (LAN) provide a link having a data transmission rate of only about 10 mega-bits per second. Furthermore, the full bandwidth of these known techniques cannot be utilized because of the overhead associated with the particular network topology. With the type of data throughput required by multimedia applications, it can be seen that traditional type LANs are theoretically extensible to a maximum of about three workstations. Simply put, these conventional networks are inadequate for connecting a large number of workstations in the high throughput environment required by multimedia applications.
The X3T9.5 committee of the American National Standards Institute (ANSI) defined a set of protocols for a high speed network known as the Fiber Distributed Data Interface (FDDI). The high speed network provides data throughput in excess of 100 mega-bits per second and can extend up to 100 kilometers. The FDDI specification calls for a fiber-optic transmission medium in a ring topology and a token-passing protocol.
FDDI has long been considered the solution that solves the throughput requirement of the vast amounts of data required by multimedia applications. While FDDI has been known for years, it has been accompanied by a number of problems. High costs, lack of standards, and unavailability of components has limited the use of FDDI networks to areas where performance is key and cost is not a problem.
Attempts have been made to make FDDI cost effective by utilizing it as a backbone network. A backbone network is a primary network which interconnects a secondary network through gateways, bridges, and routers. A gateway, bridge, or router acts as an internetworking module for integrating dissimilar LANs onto the high speed backbone and in effect, creating a hybrid network.
The router operates at the network layer. It intercepts and forwards data packets based on a network identifier. The router performs packet fragmentation and reassembly, packet control, and priority routing for internetworking the high speed network to a low speed LAN having a star topology. A gateway operates in a similar manner to the router except that it internetworks the high speed network to a low speed LAN having a ring topology.
A bridge operates at the data-link layer. Each destination field on the high speed network is read and compared with an address table. The bridge then determines whether a data packet is for a particular workstation connected to the low speed end of the bridge.
While these systems and methods for internetworking low speed networks to a high speed backbone network are available, they require considerable overhead and usually take the form of a specialized bus-board in each computer.
It can be seen then that there is a need for a high speed network which is easily adaptable to existing systems. It can also be seen that there is a need for a local area video network which is extensible to a large number of workstations but which primarily utilizes existing economical network technology to deliver multimedia data.
SUMMARY OF THE INVENTION To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an economical local area video network which utilizes existing LAN technology for delivering multimedia information and which is extensible to a large number of PC workstations without the use of specialized hardware in each workstation.
The local area video network includes a redundant array of inexpensive disks (RAID) for storing the multimedia data. The system further includes a media server coupled to the RAID through a disk interface for mapping logical data requests to physical data on the RAID. The disk interface provides parallel access to data on the disks which in the aggregate, provides a large total bandwidth.
A high speed link having a ring topology couples the media server to unique time division multiple access (TDMA) control circuitry. The TDMA circuitry transmits and receives data in a time division multiple access (TDMA) manner so that multiple PC workstations take advantage of the high throughput provided by the link. A star topology is provided between the TDMA circuitry and individual PC workstations.
The TDMA circuitry may further include means for reformatting the data in a traditional LAN protocol for delivery of the data to individual workstations.
In one aspect of the present invention, a combination of elements provides a solution to coupling a large number of standard PC workstations having traditional type LAN interfaces to a media server. In another aspect of the invention, the large number of standard PC workstations have access to a large multimedia database.
In another aspect of the invention, an economical system and method is provided to pack and unpack data from a star topology network onto a high speed, ring topology network.
In another aspect of the invention, TDMA circuitry is provided as an interface between a high speed ring network and a star network. Another aspect of the invention is that a large number of PC workstations have substantially random and simultaneous access to a large multimedia database.
Yet still another aspect of the invention is that a local area video network is provided which is extensible to a large number of personal computers having standard interf ces.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described specific examples of devices and methods in accordance with the invention. BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
Fig. 1 depicts an overall diagram of a local area video network in accordance with the principles set forth in the present invention;
Fig. 2 depicts a data stream and a bit format of a packet control register for time division multiple access control in accordance with the principles set forth in the present invention;
Fig. 3 is a more detailed view of an individual data packet within the data stream of Fig. 2;
Fig. 4 depicts the slot time logic for the time division multiple access control circuitry depicted in Fig 1;
Fig. 5 depicts the transmit portion of the packet control register of the time division multiple access control circuitry depicted in Fig. 1; and
Fig. 6 depicts the receive portion of the packet control register of the time division multiple access control circuitry depicted in Fig. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Before describing, in detail, the particular system and method for practicing a local area video network in accordance with principals of the present invention, it should be noted that the invention resides primarily in a novel structural combination of conventional elements, and not in the particular detailed configuration thereof. Accordingly, the structure, control, and arrangement of these conventional elements have been illustrated in the drawings by readily understandable block representations and schematic diagrams, which show only those specific details that are pertinent to the present invention, in order not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the illustrations in the figures do not necessarily represent the mechanical structural arrangement of the exemplary system, but are primarily intended to illustrate the major structural components in a convenient functional grouping, wherein the present invention may be more readily understood. Reference is now made to Fig. 1 wherein a local area video network 10 in accordance with the present invention is depicted. The term "server" is used herein to denote a computer workstation configured to provide a specified service on the network. A media server 12 includes a small computer system interface (SCSI) 14 for accessing and serving digital data representative of text, graphics, digitized video and audio signals. The SCSI 14 couples the media server 12 to a redundant array of inexpensive disks (RAID) 16. In the preferred embodiment, the RAID 16 is six disks wide. Those skilled in the art will be able to bring to mind other suitable sizes for the RAID 16 for which the principles of the present invention may be practiced without departing from its scope.
Each disk within the RAID 16 provides a throughput of 24 MHz giving a total throughput to the media server 12 of 144 MHz. At this bandwidth, the media server 12 has access and can serve 120 independent video strings at 1.2 MHz apiece.
A high speed data link 18 having a ring topology transmits and receives data at a high rate of speed between the media server 12 and time division multiple access (TDMA) control circuitry 20. The link 18 may be, but is not limited to, a link in accordance with the fiber distributed data interface (FDDI) as described in the X3T9.5 standard set forth by the American National Standards Institute (ANSI) and herein incorporated by reference. The TDMA circuitry 20 is depicted in more detail in Figs. 4-6 and is more fully described herein below.
In the preferred embodiment, the physical layer of the high speed data link 18 is referenced to as an optical fiber cable. Those skilled in the art will be able to bring to mind other suitable expedients for the physical layer such as a shielded twisted pair or data-grade unshielded twisted pair wire.
A controller (not shown) is included within the media server 12 for adapting the data link 18 at the network layer to the particular bus configuration of the media server 12. The bus configuration of the media server 12 may be, but is not limited to, the Industry Standard Architecture (ISA), the Extended Industry Standard Architecture (EISA), VME, VXI, or Multibus configurations. The controller may include a processor unit and sufficient memory to relieve the media server 12 from overhead associated with the data link 18.
The TDMA circuitry 20 receives and transmits data in accordance with the protocols of the data link 18 and reformats the data for distribution to a plurality of PC workstations 22. In the preferred embodiment, a TDMA protocol is practiced wherein a sync packet, a control register packet, and N data packets are included within the data stream.
The TDMA circuitry 20 internetworks the plurality of PC workstations 22 configured in a star topology to the link 18 configured as a ring. The internetworking between the media server 12 and the plurality of PC workstations 22 is accomplished in a manner which is transparent to the individual PCs. The TDMA circuitry 20 is coupled to each of the plurality of PCs 22 through an individual full duplex link 24. In the preferred embodiment and by way of example and not limitation, the link 24 may be a 10 Base- T twisted pair link as set forth by the Institute of Electrical and Electronic Engineers (IEEE) in the IEEE 802.3 standard, herein incorporated by reference. Each link 24 is dedicated to the individual PC attached thereto for supplying the full bandwidth to that associated PC. Thus, the usual delays associated network overhead such as carrier sense multiple access with collision detect (CSMA/CD) LANS, are not present and multimedia data can be sent and received at the full bandwidth rate of the link 24.
Reference is now made to Fig. 2 which depicts the data stream 26 and the bit format for a control register packet 28. A sync packet 30 is included at the beginning of the data stream 26 for synchronizing the TDMA control circuitry 20 to the data stream 26 and for providing a timing reference. The sync packet 30 is designated as the reference time slot and is used for correcting past variations in slot time and to signal a start of frame. Each PC within the array of workstations 22 has an unique time slot (1-N) in reference to the sync packet 30. Adjacent the sync packet 30 is a control register packet 28. The control register packet 28 comprises a receive flag register (PCR RX) 32 and a transmit flag register (PCR TX) 34. Individual bits within PCR RX 32 and PCR TX 34 correspond to each time slot of the workstations 22. When set, a bit indicates that a packet of data is ready to be transferred between the media server 12 and a particular PC within the array of workstations 22. For example, setting the ith bit in the PCR RX 32 register indicates to the controller in the media server 12 that the ith workstation has inserted data into its time slot. Likewise, setting the ith bit in the PCR TX 32 register indicates to the ith workstation that media server 12 through the controller has inserted data into its time slot. The data stream 26 depicted in Fig. 2 is best described as a fixed time division multiple access (TDMA) packet wherein the number of traffic channels (N) within the time interval T is fixed. Each recurring time interval T (i.e. a frame period) is divided into N equal time slots plus a slot for the control register packet 28 and a slot for the sync packet 30. Each participating PC in workstation array 22 is allotted one of N time slots. In addition to digital baseband information, a packet within a given time slot may also include a preamble for containing auxiliary information for system organization such as headers, trailers, addresses, and cyclic redundancy checking (CRC) .
In the preferred embodiment, each packet of data served by the media server 12 is interleaved to contain multiple video and audio channels. By way of example and not limitation, a representative ith data packet is depicted in Fig. 3. The ith data packet contains a plurality of video and audio channels such as described by the Audio/Video Support System (AVSS) format. Fig. 3 depicts two video (video A and video B) and two audio (audio A and audio B) channels. Those skilled in the art will be able to bring to mind other suitable combinations and variations thereof without departing from the scope of the present invention. Reference is now made to Fig. 4 wherein the slot time logic for the TDMA control circuitry 20 is depicted. A clock generator 36 has an input coupled to the serial data stream traveling on the link 18 and a clock output for providing a data clock signal 38 which assimilates the frequency and phase characteristics of the data stream. The data clock signal 38 is a local timing reference used for among other things, to clock data in and out of data buffers. Many expedients are known for the clock generator 36. Such circuits may include voltage controlled oscillators, dividers and phase-locked loops. The particular detailed configuration of the clock generator 36 is not necessary for practicing the invention in accordance with the principals set forth. The structural details for such a circuit will be readily apparent to those skilled in the art having the benefit of the description herein. The data clock signal 38 is applied to an input of a divider 44 having a divisor equal to the packet size. The divider 44 has an output coupled to a clock input on shift register 46 for generating packet slot times.
Sync detector 40 has a first input to the data clock signal 38 and a second input coupled to the data stream. The sync detector 40 compares the data stream to a predetermined data pattern for detecting a sync packet and has an output for generating a sync detect pulse 42 to initiate a start of frame sequence in response thereto. The sync detect pulse 42 is coupled to a load input on shift register 46. When sync is detected, the shift register 46 is loaded and is sequenced by the divider 44 output for providing slot times 1 through N. Slot time outputs 1-N are temporally spaced apart a time equal to the packet size and are in phase with packets 1-N on link 18. The sync detect pulse 42 is delayed by PCR delay 45 to take into account the length of the control register packet 28.
Reference is now made to Fig. 5 wherein the transmit portion (viewed from the media server side) of the TDMA control circuitry 20 is depicted. The PCR TX 34 portion of the packet control register 48 indicates whether the media server 12 has placed a packet of data on link 18 for a select workstation. For purposes of illustration, the transmit portion will be described with respect to the ith workstation. It should be understood that the description of the ith workstation applies equally to all the other workstations and that redundant circuitry has been excluded for the sake of clarity. The control register packet 28 in the data stream is clocked through the packet control register 48 by the data clock signal 38 in response to the presence of a sync detect pulse 42. .AND gate 50 enables input buffer 52 to fill with data from the data stream if the ith packet ready bit in the PCR TX 34 is set, the input buffer 52 is empty, and it is the ith slot time. AND gate 50 further resets the ith packet ready bit in the PCR TX 34 when the input buffer 52 is not empty to indicate to the media server 12 that the data packet has been read.
The input buffer 52 may be an accordion buffer having an auxiliary clock 54 applied to it for clocking the data to the ith workstation at a slower speed. In the preferred embodiment, the auxiliary clock 54 is compatible data speeds set forth under IEEE 802.3.
The data stream passes through the packet control register 48 and is regenerated with the locally generated data clock 38 for reducing jitter in the data out stream 56. Reference is now made to Fig. 6 wherein the receive portion (viewed from the media server side) of the TDMA control circuitry 20 is depicted. The PCR RX 32 portion of the packet control register 48 indicates to the media server 12 whether a select workstation has placed a packet of data on the link 18. For purposes of illustration, the receive portion will be described with respect to the ith workstation with the understanding that the description applies equally to all other workstations.
The packet ready bit for the ith workstation is clocked through the packet control register 48 by the data clock signal 38. If the output buffer 58 is full and the ith packet ready bit in the PCR RX 32 has been cleared by the media server 12 indicating that the server 12 has read the packet, AND gate 60 sets the ith packet ready bit in the PCR RX 32 to indicate to the media server 12 that a new data packet has been placed on the link 18. AND gate 62 enables tri-state driver 64 for driving the data stream with data stored in the output buffer 58 if the buffer full signal is activated and it is the ith slot time. Output buffer 58 sets the buffer full signal true when filled with data from the ith workstation. The auxiliary clock 54 is applied to output buffer 58 to clock the data in the buffer from the ith workstation at a slower speed.
The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:
1. A system for providing digitized video clips, text, graphics, and sound for creating a multimedia experience, the system being extensible to a large number of personal computers having standard interfaces, the network comprising:
(a) means for storing and providing random access to multimedia data;
(b) server means, coupled to the means for storing and providing random access to multimedia data, for mapping requests to the multimedia data;
(c) high speed link means, coupled to the server means, for transmitting the multimedia data in a ring network; (d) workstation means for providing a plurality of users access to the multimedia data; and
(e) time division multiple access control means for coupling the workstations means to the high speed link means, the time division multiple access control means transmitting and receiving data between the high speed link means and the workstations means.
2. A system as recited in claim 1 wherein the means for storing and providing random access to multimedia data is a redundant array of inexpensive disks.
3. A system as recited in claim 1 wherein the high speed link means substantially complies with protocols for a Fiber Distributed Data Interface (FDDI) set forth by an X3T9.5 committee of the American National Standards Institute.
4. A system as recited in claim 1 wherein the workstation means comprises at least three personal computers.
5. A system as recited in claim 1 wherein the time division multiple access control means internetworks a plurality of workstations configured in a star topology to high speed link means configured as a ring.
6. A system as recited in claim 5 wherein each of the plurality of workstations are individually coupled to the time division multiple access control means through a full duplex link as set forth by the Institute of Electrical and Electronic Engineers (IEEE) in the IEEE 802.3 standard.
7. A local area video network comprising:
(a) a redundant array of inexpensive disks (RAID) for storing multimedia data;
(a) a media server coupled to the RAID through an interface for mapping logical data requests to physical data on the RAID, the interface providing parallel access to data on the RAID; (c) a high speed link having a ring topology coupled to the media server;
(d) a plurality of computer workstations; and
(e) time division multiple access (TDMA) control means for coupling the plurality of workstations to the high speed link, the TDMA control means being coupled to the plurality of workstations in a star configuration and to the high speed link in a ring configuration, the TDMA control means transmitting and receiving data between the high speed link and the plurality of workstations.
8. A local area video network as recited in claim 7 wherein the TDMA control means further include means for reformatting the data into a low speed protocol for delivery of the data to the plurality of workstations.
9. A local area video network as recited in claim 7 wherein the interface for mapping logical data requests to physical data on the RAID is a small computer system interface (SCSI).
10. A local area video network as recited in claim 7 wherein the media server further includes a controller for adapting a bus configuration of the media server to the high speed link at a network layer.
11. A local area video network as recited in claim 10 wherein the controller further includes a processor unit and sufficient memory to relieve the media server from overhead associated with the high speed link.
12. A local area video network as recited in claim 7 wherein the bus configuration substantially complies with an Extended Industry Standard Architecture (EISA) .
13. A local area video network as recited in claim 7 wherein a data stream on the high speed link comprises: (i) a sync packet;
(ii) a control register packet concatenated to the sync packet; and (iϋ) N data packets concatenated to the control register packet wherein N represents a number of the plurality of computer workstations.
14. A local area video network as recited in claim 13 wherein the data stream further comprises a preamble for containing auxiliary information for system organization such as headers, trailers, addresses, and cyclic redundancy checking (CRC) .
15. A local area video network as recited in claim 13 wherein each of the N data packets comprises interleaved multiple video and audio channels.
16. A local area video network as recited in claim 15 wherein the interleaved multiple video and audio channels are in an Audio/Video Support System (AVSS) format.
17. A local area video network as recited in claim 7 wherein the time division multiple access (TDMA) control means further comprises:
(i) slot time logic means for determining slot times of the respective computer workstations; (ϋ) sync detector means for comparing the data on the high speed link to a predetermined data pattern and for indicating sync detect in response thereto; and
(iii) a packet control register for indicating whether a packet of data has been placed on the high speed link.
18. A local area video network as recited in claim 17 wherein the packet control register further comprises:
(i) a receive flag register for indicating to the media server that the a select workstation has inserted data onto the high speed link; and
(ii) a transmit flag register for indicating to a select workstation that the media server has inserted data onto the high speed link.
19. A method for providing digitized video clips, text, graphics, and sound for creating a multimedia experience on a plurality of workstations, the method comprising the steps of: (a) storing and providing random access to multimedia data;
(b) mapping requests to the multimedia data;
(c) transmitting the multimedia data in a high speed ring network; (d) providing a plurality of users access to the multimedia data; and (e) coupling the users in a time division multiple access manner to the high speed ring network and transmitting and receiving data therebetween.
20. A method as recited in claim 19 wherein step (e) further comprises the steps of:
(i) determining slot times of the respective users in the high speed network;
(ii) comparing the data on the high speed link to a predetermined data pattern and indicating a sync detect in response thereto; and
(iii) indicating whether a packet of data has been placed on the high speed link.
PCT/US1993/005604 1992-09-04 1993-06-11 Local area video network WO1994006091A1 (en)

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AU4632693A (en) 1994-03-29

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