WO1993024895A3 - Timing driven method for laying out a user's circuit onto a programmable integrated circuit device - Google Patents

Timing driven method for laying out a user's circuit onto a programmable integrated circuit device Download PDF

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Publication number
WO1993024895A3
WO1993024895A3 PCT/US1993/004892 US9304892W WO9324895A3 WO 1993024895 A3 WO1993024895 A3 WO 1993024895A3 US 9304892 W US9304892 W US 9304892W WO 9324895 A3 WO9324895 A3 WO 9324895A3
Authority
WO
WIPO (PCT)
Prior art keywords
suggested
limits
delays
integrated circuit
programmable integrated
Prior art date
Application number
PCT/US1993/004892
Other languages
French (fr)
Other versions
WO1993024895A2 (en
Inventor
Jon A Frankle
Mon-Ren Chene
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Priority to JP50067794A priority Critical patent/JP3737104B2/en
Priority to EP93911389A priority patent/EP0643855A1/en
Publication of WO1993024895A2 publication Critical patent/WO1993024895A2/en
Publication of WO1993024895A3 publication Critical patent/WO1993024895A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing

Abstract

The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.
PCT/US1993/004892 1992-06-04 1993-05-27 Timing driven method for laying out a user's circuit onto a programmable integrated circuit device WO1993024895A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP50067794A JP3737104B2 (en) 1992-06-04 1993-05-27 Timing driven method of placing user circuitry in a programmable integrated circuit device
EP93911389A EP0643855A1 (en) 1992-06-04 1993-05-27 Timing driven method for laying out a user's circuit onto a programmable integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89450092A 1992-06-04 1992-06-04
US894,500 1992-06-04

Publications (2)

Publication Number Publication Date
WO1993024895A2 WO1993024895A2 (en) 1993-12-09
WO1993024895A3 true WO1993024895A3 (en) 1994-02-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/004892 WO1993024895A2 (en) 1992-06-04 1993-05-27 Timing driven method for laying out a user's circuit onto a programmable integrated circuit device

Country Status (4)

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US (1) US5521837A (en)
EP (1) EP0643855A1 (en)
JP (1) JP3737104B2 (en)
WO (1) WO1993024895A2 (en)

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Also Published As

Publication number Publication date
WO1993024895A2 (en) 1993-12-09
EP0643855A1 (en) 1995-03-22
JPH07507409A (en) 1995-08-10
EP0643855A4 (en) 1995-04-19
JP3737104B2 (en) 2006-01-18
US5521837A (en) 1996-05-28

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