WO1992019052A1

WO1992019052A1 - Mappable test structure for gate array circuit and method for testing the same

Info

Publication number: WO1992019052A1
Application number: PCT/US1992/003204
Authority: WO
Inventors: Michael A. Zampaglione; Michael G. Kliment
Original assignee: Vlsi Technology, Inc.
Priority date: 1991-04-19
Filing date: 1992-04-16
Publication date: 1992-10-29

Abstract

A set of interconnections is used for testing components (104) of a gate array integrated circuit (100). The gate array integrated circuit has an array (102) of the components (104) arranged in rows and columns and a set of input/output pads (120) along the periphery of the array. The set of interconnections includes component selection interconnections (METAL 1), coupled to all components in a core region (140) of the gate array integrated circuit. These component selection interconnections enable selective activation of predefined groups of the components (104) in the core region. Bit line interconnections (METAL 2) carry test signals generated by activated components in the core region. A separate test signal is generated by each of the components in the core region (140), thereby enabling each of the components in the core region to be individually tested.

Description

MAPPABLE TEST STRUCTURE FOR GATE ARRAY CIRCUIT AND METHOD FOR TESTING THE SAME

The present invention relates generally to gate array integrated circuits, typically used to speed the development of application specific integrated circuits (known as ASICs), and particularly to methods and systems for testing the integrity of all devices defined by base layers in a gate array.

BACKGROUND OF THE INVENTION

The problem which the present invention solves is as follows. When a new gate array is first developed, there is the possibility that one or more of the components in the array is defective. For instance, an error during mask making, (e.g., a broken connection caused by a piece of dust during mask making) may cause the gate array to be partially inoperable. Furthermore, a gate array may contain hundreds of thousands of components, and any one customized circuit built using the gate array will typically use less than one hundred percent of those components.

It is quite possible to design one or more customized circuits using a gate array having one or more defective components without encountering the defective component or components in the gate array. Then, if the gate array does contain a defective component, a subsequent customized circuit will fail. As a result there will then be a substantial unavoidable delay in producing a working circuit because it will take much time and effort to locate the defect, generate new masks for the base layers of the gate array, and then to manufacture new circuits using the new masks. Typically, encountering such a defect in the base layers of the gate array would delay the production of a custom integrated circuit by at least two to three months.

As will be understood by those skilled in the art, the "base layers" of a gate array are those layers which remain unchanged regardless of the manner in which the array's components are interconnected. Typically, the base layers are all layers of the gate array below the two metal interconnect layers and the contact layers, which are used to interconnect components and thereby form a customized circuit. Gate array wafers containing only the base layers are often "banked" by manufacturers, to speed up the process of manufacturing customized circuits. In other words, all the manufacturing steps, except for those steps required for interconnecting components, are performed on large numbers of wafers in advance of receiving orders or even circuit designs from customers.

When a customer brings in a new circuit design using the gate array, or orders additional wafers of a circuit design using the gate array, the customer's circuit can be manufactured very quickly using the banked wafers. Given the heavy investment made in such banked wafers, it is important to be able to test the base layers of gate array integrated circuits so as to ensure that the gate array does not contain any defective components.

Furthermore, since one of the main reasons for using gate array technology is to substantially reduce the time required for designing and beginning production of a customized circuit, it would be desirable for the manufacturers of gate array circuits to be able to test the base layers of such gate array circuits for defective components. However, such testing has generally not been done in the past because it has been assumed that it is not possible to design a circuit using the gate array that would allow complete testing of every component in the core of the array. The present invention solves the problem of how to completely test all the components of a gate array core by providing an interconnect pattern which allows individual testing of the great majority of the components in a gate array integrated circuit, and group testing of all the remaining components, with the ability to detect and map many types of failures. Therefore if even a single component in the gate array core is defective, the presence of the defect will be detected, and the location of the defect will be either identified as a particular single component or as a member of a particular group of components.

SUMMARY OF THE INVENTION

In summary, the present invention is a set of interconnections for testing components of a gate array integrated circuit. The gate array integrated circuit has an array of components arranged in rows and columns and a set of input/output pads along the periphery of the array of components. The set of interconnections includes component selection interconnections which enable selective activation of predefined groups of the components in the core region of the circuit.

Bit line interconnections carry test signals generated by activated components in the core region of the gate array. A separate test signal is generated by each component in the core region of the gate array, thereby enabling each such component to be individually tested.

Decoder interconnections, located in the core region of the integrated circuit that is tested by the present invention, are coupled to components in a first peripheral region of the gate array core and to a set of input pads along the periphery of the gate array circuit. These decoder interconnections form a decoder circuit which selectively couples certain input pads to selected ones of the component selection interconnections. This allows activation signals transmitted via the input pads to be selectively asserted on the component selection interconnections which, in turn, activates selected groups of components in the core region of the gate array.

Finally, a set of multiplexer interconnections located in the core region of the integrated circuit are coupled to components in a second peripheral region of the gate array core and to a set of output pads along the periphery of the gate array. The resulting multiplexer circuit transmits selected test signals from the bit line interconnections to the output pads. Component failures in the decoder and multiplexer regions of the test circuit are mappable using the present invention to within a few components. As a result, virtually all components within the core region of the gate array are testable so as to be able to map any base layer defects that may exist.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

Figure 1 is a block diagram of a gate array integrated circuit, and Figure 1A shows the unconnected circuit elements in one cell of the gate array.

Figure 2 is a block diagram of a gate array interconnect pattern used in the preferred embodiment of the present invention.

Figure 3 depicts the circuitry interconnect in one cell in the core of the gate array circuit shown in Figure 2.

Figure 4 depicts the circuit interconnects for a set of four neighboring cells.

Figure 5 depicts a two-to-one multiplexer circuit using two gate array cells. Figure 6 depicts a sixteen-to-one multiplexer circuit using 30 gate array cells, and also depicts where those cells are located within the gate array interconnect pattern shown in Figure 2.

Figure 7 depicts a delay chain formed from a chain of two-to-one multiplexer circuits.

Figure 8 depicts a two-to-eight demultiplexer circuit using sixteen gate array cells.

Figure 9 depicts a plurality of two-to-eight demultiplexer circuits and where those cells are located within the gate array interconnect pattern shown in Figure 2.

Figure 10 depicts a gate array circuit coupled to a tester system.

Figure 11 depicts a flow chart of the testing method used by present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to Figure 1 , there is shown a conceptual drawing of a gate array integrated circuit 100. The circuit 100 is manufactured using standard CMOS processing techniques, and the devices on the particular gate array circuit used in the preferred embodiment use 1 micron design rules. For the purposes of describing the invention, this document will describe how the invention is implemented using one particular gate array circuit 100. However, the particular arrangement of circuit elements in the "base layers" of this gate array circuit is not essential to the invention, because the invention concerns an interconnect pattern that will facilitate the testing of virtually any gate array integrated circuit.

Gate array 100 contains an array of unconnected circuit components, shown in Figure 1 as an array 102 of cells 104. Figure 1A shows that in the preferred embodiment, each such cell 104 contains two N-channel transistors 106 and

108, and two P-channel transistors 110 and 112. Furthermore, there are one-hundred and forty input output pads 120 located along the periphery of the gate array 102. It should be understood that the gate array circuit 100 shown in Figures 1 and 1A contains only the "base layers" of a gate array circuit, which are the set of layers which remain unchanged regardless of the manner in which the array's components are interconnected.

Referring to Figure 2, there is shown a block diagram of the gate array interconnect pattern used in the preferred embodiment of the present invention. In particular, components in the base layers of the gate array circuit are divided into three regions:

1) a core region 140, which includes all the components of the gate array except those in certain peripheral regions of the array,

2) one or more peripheral regions 142 used to form multiplexing circuits that are used to transmit signals generated by selected components in the core 140, to output pads along the periphery of the gate array and

3) one or more peripheral regions 144 used to form decoder circuits that are used to decode and transmit component selection signals from input pads along the periphery of the gate array to selected sets of components in the core 140.

in addition, there are a small number of "extra cells" 150 in regions along the periphery of the array not included in regions 140, 142 or 144. These extra cells are interconnected to form a delay chain using a fourth interconnect pattern so as to enable testing of the components in these extra cells.

A programmable circuit tester 154 is coupled to all the input/output pads along the periphery of the gate array, The tester 154 is programmed to test the operability of every cell in the gate array core 140, as well as the other cells surrounding the gate array core. Using the test signals generated by activated components in the gate array circuit, the position of any transitors with defects in the base layers of the core region 140 can be identified precisely (i.e., the specific transistor with the defect can be identified), the position of transistors with defects in the multiplexer and demultiplexer regions can be identified to within a few transistors, and the position of transistors with defects in the extra regions 150 can be identified as being in one of the two paths in the delay chain.

Referring to Figure 3, there is shown the circuitry interconnect pattern 160 for one cell in the core region 140 of the gate array circuit shown in Figure 2. As shown, each cell requires four row lines, labelled here as ROW_0 through ROW_3 formed from a first metal interconnect layer herein called the Metal 1 layer and a bit line formed from a second metal interconnect layer herein called the Metal 2 layer. Each row line enables a distinct one of the four components (i.e., transistors 106-112) in the cell, and thereby asserts a corresponding signal on the bit line 162. In particular, asserting a low voltage on ROW_0 enables transistor 110, thereby asserting a high voltage (Vcc) on the bit line; asserting a low voltage on ROW_1 enables transistor 112, thereby asserting a high voltage (Vcc) on the bit line; asserting a high voltage on ROW_2 enables transistor 108, thereby asserting a low voltage (Gnd) on the bit line; asserting a high voltage on ROW_3 enables transistor 106, thereby asserting a low voltage (Gnd) on the bit line.

So that the reader can better picture how components are interconnected in the core region 140, Figure 4 depicts the circuit interconnects for a set of four neighboring cells 171-174 in the core region 140 of the gate array. As shown, each row line enables one component in each cell in a row of cells, and each bit line BLO and BL1 is connected to all the components in a column of cells. Furthermore, for reasons that will be explained below, the bit lines BLO and BL1 in neighboring columns of cells terminate at opposite ends of the array - one terminating at the bottom of the array and one terminating at the top.

Assuming that there were sufficient numbers of input and output pads, one could use the interconnection pattern shown in Figures 2, 3 and 4 to individually test every component in the core region 140 of the gate array by enabling one row signal at a time, and then testing the resulting test signals on the bit lines. The results of these tests are easily mapped into a "bitmap" matching the arrangement of components in the gate array, in particular, test signals are compared with expected output signal patterns, and those which do not match the expected signal patterns are reported and the location of the defective component is noted.

COMPONENT SELECTION AND OUTPUT SIGNAL CONNECTIONS. In the preferred embodiment, the gate array circuit 100 contains 550 columns of cells (i.e., 1100 columns of components) with 220 transistor components in each column of cells. In other words, there are 550 columns and 55 rows of cells. Thus, 550 bit lines, and 220 row lines, and 770 input output pads would be needed to individually test all the components in the array using the interconnect patterns shown in Figures 2, 3 and 4. However, the actual gate array circuit has only 140 input/output pads for transmitting input and output signals to and from the gate array.

Since there are not enough pads, output signals from the bit lines are multiplexed, and component selection signals are decoded, in particular, referring to Figure

2, the row below the top row and the row above the bottom row 142 of the gate array are used to multiplex the bit lines down to a smaller number of outputs, and two columns of cells 144 on either side of the array are used to de-multiplex

(i.e., decode) selection signal inputs from a smaller number up to the number of row selection signals needed. The top and bottom rows of the array are used to form delay chains. Since four of the fifty five rows of cells are not included in the core region 140, this leaves fifty-one rows of cells, requiring 204 row lines for the core region 140. Similarly, there are 542 bit lines in the core region, not

550, since eight columns of cells are occupied by decoder regions 144.

Referring to Figure 5, there is shown a two-to-one multiplexer circuit 180 using two gate array cells. This circuit uses two selection signals SEL_0 and SEL_1 , which are complementary signals, to assert either of two input signals IN_0 or IN_1 on an output line OUT. The selected input signal is inverted by the circuit 180 before being asserted on the output line. An important feature of this multiplexer circuit is that it uses no "isolation" components. Therefore if any component in the circuit 180 fails, such a failure will affect the output signals generated by the circuit and thus the failure will be detectable.

Referring to Figure 6, there is shown a sixteen-to-one multiplexer circuit 190 using thirty gate array cells. Each pair of cells shown in Figure 6 comprises one copy of the circuit 180 shown in Figure 5. Figure 6 also depicts where those cells are located within the multiplexer region 142 shown in Figure 2. In particular, circuit block 192 is an eight-to-one multiplexer using six selection signals MSELO through MSEL5 (actually three pairs of selection signals) to select one of eight bit lines. The outputs from two blocks 192 are then multiplexed by one last two-to-one multiplexer circuit 194, under the control of a last pair of selection signals MSEL6 and MSEL7, to output a single bit line signal to an output pad 196 along the periphery of the gate array.

The bottom portion of Figure 6 shows how the sixteen-to-one multiplexer is implemented using a single row of cells. Each "level" of multiplexer cells are distinctly labelled, the first level being labelled "M", the second level being labelled "2", the third level being labelled "3" and the fourth level being labelled "4".

As shown in Figure 4, every other bit line is processed by the multiplexer region 142 at the top of the array and the other bits lines are processed by the multiplexer region 142 at the bottom of the array. This is necessary for the multiplexers to fit into one row and to evenly distribute the outputs among the top and bottom rows of the array without extensive routing. Using this scheme, for every thirty-two columns of cells in the core region, sixteen bit lines will be processed by one sixteen-to-one multiplexer at the bottom of the array and the other sixteen bit lines will be processed by one sixteen-to-one multiplexer at the top of the array. Since there are 542 columns of cells in the core region 140 of the gate array circuit, thirty-four sixteen-to-one multiplexers 190 (seventeen on top and seventeen on the bottom of the array) and thirty-four output pads are needed. Since thirty-four multiplexers could multiplex up to 544 bit lines, the connections for the last multiplexer 190 are only partially completed.

Only thirty cells are used by each sixteen-to-one multiplexer. Thus there are two unused cells 150 in region 142 for each set of thirty-two columns. These extra cells in each region 142, along with a row of similar "inverter" cells in an adjacent row of cells, are interconnected to form a chain of delay elements, with each end of the delay chain being connected to a pad. Each "inverter" or delay element in the delay chain is actually a multiplexer cell connected as shown in Figure 7. Each such chain of cells actually contains two parallel delay chains, one of which is tested by setting SEL0 high and SEL1 low, and the other one of which is tested by setting SEL0 low and SEL1 high.

Each delay chain includes two cells in each of two corners of the gate array, plus thirty-three cells not used by the seventeen 16-to-1 multiplexers in each region 142, plus 550 cells in the top or bottom row of the array core. Thus each of the two chains of inverters contains or uses 587 cells. These inverter chains can be broken into smaller chains if there are any leftover input output pads.

In Figures 2 and 8, the demultiplexer cells labelled with the letter D use the same circuit connections as the multiplexer cell shown in Figure 5, with the input and output signals for the top left demultiplexer cell in Figure 8 being renamed as follows: IN_0 and IN_1 are called ADR_0 and ADR_1, SEL_0 and SEL_1 are called DSELO and DSEL1, and OUT is called ROW_A. Figure 8 shows a two-to-eight demultiplexer or decoder circuit 220 formed from eight such "demultiplexer" cells (using a total of sixteen gate array cells). As explained above, the purpose of the decoder circuit 220 is to reduce the number of row selection input signals, which is required because the gate array circuit has a limited number of input output pads. A pair of complementary selection signals DSELO and DSEL1 , received from input pads, are used to either enable or disable cell 182 or 184 (see Figure 5). If cell 182 is enabled, address signal ADR_0 is asserted as ROW_A. If cell 184 is enabled, address signal ADR_1 is asserted as ROW_A.

Figure 9 depicts a plurality of two-to-eight demultiplexer circuits 220, each using sixteen gate array cells, and also depicts where the cells in those circuits are located within the gate array interconnect pattern shown in Figure 2. The demultiplexer circuit 220 at the top-left corner of the gate array decodes two input signals ADR_0 and ADR_1 into eight row selection signals:

ROW_0, ROW_1, ROW_6, ROW_7,

ROW_8, ROW_9 ROW_14, ROW_15 using decoder selection signals DSELO through DSEL15. For testing, each row must be activated twice: once with ADR_0 enabled and once with ADR_1 enabled. The same decoder selection signals DSELO through DSEL15 are used in every decoder circuit 220. Furthermore, as shown, two of the four row selection signals needed for each row of cells in the core region 140 of the array are generated by one decoder circuit 220 on the left side of the array and the other two row selection signals are generated by another decoder circuit 220 on the right side of the array.

Since there are fifty-one rows of cells in the core region 140 of the gate array circuit, twenty-six two-to-eight demultiplexers (thirteen on the left and thirteen on the right of the array) are needed. Fifty-two address signals (from fifty-two input pads) can be decoded onto 208 row lines with these demultiplexer circuits. However, since there are only 204 row lines, the final decoder will be only partially completed.

The following is a listing of the minimum numbers of input/output pads used in the above described preferred embodiment of the present invention: PADS USED DESCRIPTION OF ASSOCIATED CIRCUIT

34 Multiplexer Outputs

8 Selection signals for Multiplexers

52 Address inputs for Decoders 16 Selection signals for Decoders

4 Two Chains of Inverters

2 Vcc and Ground Potential Connections

116 TOTAL

if separate pads are used for the selection signals for each region 142, 144 of decoders and multiplexers, thereby avoiding the need to transport these signals across the array, that would require an additional twenty-four input pads, for a total of 140 input and output pads - which is the total number of input/output pads available. In this case the delay chains cannot be broken into smaller chains, unless the multiplexer and decoder signals are shared.

As shown above, the use of multiplexer and decoder circuits along the periphery of the gate array circuit solves the problem of having insufficient numbers of input and output connections to individually test all components in the core region 140 of the array.

It may be noted that in this preferred embodiment, the core region 140 occupies or uses 91.37 percent of the cells in the gate array. For larger gate arrays, the percentage of cells located in the core region will be even higher, it should also be noted that the decoders, multiplexers and delay chains use the remaining 8.63% of the cells in the gate array, thereby allowing 100% of the cells in the gate array core to be tested.

TESTING METHODOLOGY.

Referring to Figures 10 and 11 , the testing methodology of the present invention is as follows. After forming the requisite interconnect pattern on a gate array integrated circuit (step 300), and connecting the gate array circuit 290 to a standard circuit tester system 292, all the components in the core region 140 of the array are individually tested by a test program 294 which sequentially steps through all the necessary combinations of input address and selection signals (step 302). For instance, to test all the components in one specified row of the array, the tester 154 (see Figure 2) asserts the corresponding row signal, and then steps through the sixteen possible settings for the multiplexer selection signals. For each setting of the multiplexer selection signals, the bit line output signals are compared with the expected values. If any values do not match the expected values, the location of the component which failed the test is denoted in the tester's memory 296.

In addition, the two delay chains are tested by toggling the input to each chain several times, and checking to see that the outputs of the chains toggle accordingly (step 304). If not, then it is known that there is a defect somewhere in the delay chain. As mentioned above, the delay through the chain must be measured twice, once with SEL_1 =1 and SEL_0=0 and once with SEL_1 =0 and SEL_0=1, to test all the transistors in the chain.

After testing all the components in the core region of the array, the list of component failures stored in the tester's memory is processed. If there were no component failures, the test is complete and no further analysis is needed (step 306).

The primary purpose of any further analysis is to determine if there has been a failure in either the decoder regions 144 or the multiplexer regions 142 of the gate array. A multiplexer failure will generally be denoted as test failures for either an entire column of cells, or failures for several columns of cells. A decoder failure will be denoted as the failure of all the cells in one "row", where a row is all the cells coupled to one row line (thus, a single physical row of components may contain two or more logical rows for test purposes).

Therefore, if there are less component failures than a "threshold value" which equal to the lesser of (1) the number of components coupled to each row line, and (2) the number of components coupled to each bit line, then there have been no failures in the decoders and multiplexers, and all denoted failures are simply component failures at the denoted locations in the core of the array (steps 308 and 310). If the number of component failures is greater than this threshold value, then the tester will check the denoted failure locations to see if all the cells in any row or column failed (step 312).

If all the cells in a row failed, that failure can be traced to a single cell in the decoder region 144, because only one cell is used to generate each row signal. Thus, the position of any failure in the decoder regions can be identified very precisely - to a single particular cell containing just four transistors.

If all the cells in a column failed, that failure can be traced to one multiplexer circuit, which may contain up to thirty cells in the preferred embodiment. However, by looking at which column or columns failed, one can generally narrow down the location of the failure to just two or four cells. Cell failures at the first level of the multiplexer will cause only one or two columns to fail, while cell failures at the second level of the multiplexer will cause two or four columns to fail, and so on.

Once all the cells associated with failed decoders or multiplexers have been identified, any remaining components denoted as having failed are then listed as separate component failures (step 312).

Clearly, whenever there is a decoder or multiplexer failure, the components in the affected rows or columns are not tested, and there is the possibility of additional defective components in the array. However, the rows and columns which need special checking due to a decoder or multiplexer failure will generally be few, and it is expected that decoder and multiplexer failures will be relatively rare since those circuit structures will typically occupy five percent or less of the gate array. ln general, the circuit formed using the interconnect pattern of the present invention can detect and map many types of failures. The easiest failure to find is a component (i.e., transistor) that will not turn on. Shorts, or transistors that do not turn off, are harder to detect. If there are shorts in the core region 140, they will be detected only if the short is strong enough to overpower transistors trying to drive the bit lines to the opposite state.

ALTERNATE EMBODIMENTS.

The techniques of the present invention can be used with any gate array circuit, regardless of the types of components used in the array, and regardless of the number of rows and columns of components in the array or even if some other type of component placement pattern were used. In general, in excess of ninety percent, and typically close to one-hundred percent, of the cells in the gate array core of virtually any gate array can be tested for base layer defects using the present invention.

While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A set of interconnections for testing components of a gate array integrated circuit, the gate array integrated circuit having an array of components arranged in rows and columns and a set of input/output pads along the periphery of the array of components, the set of interconnections comprising: component selection interconnections, coupled to all components in a first region of a gate array circuit, said component selection interconnections enabling selective activation of predefined groups of said components; test signal interconnections, coupled to all components in said first region of said gate array circuit, carrying test signals generated by activated components in said gate array circuit; and input/output connections coupled to components in a second region of said gate array circuit, including input connections coupling said component selection interconnections to input pads along the periphery of the array of components and output connections coupling said test signal interconnections to output pads along the periphery of the array of components; said test signals identifying defective components, if any, in said first and second regions of said gate array circuit.

2. The set of gate array circuit interconnections set forth in Claim 1 , further including additional connections coupled to substantially all remaining components in said gate array circuit not included in said first and second regions of said gate array circuit, said additional connections coupling said remaining components to input/output pads along the periphery of the array of components to enable testing of said remaining components for defects; wherein said gate array circuit interconnections enable testing of substantially all components of said gate array circuit for defects.

3. A set of interconnections for testing components of a gate array integrated circuit, the gate array integrated circuit having an array of components arranged in rows and columns and a set of input/output pads along the periphery of the array of components, the set of interconnections comprising: component selection interconnections, coupled to all components in a first region of a gate array circuit, said component selection interconnections enabling selective activation of predefined groups of said components; test signal interconnections, coupled to all components in said first region of said gate array circuit, carrying test signals generated by activated components in said gate array circuit; decoder interconnections, coupled to components in a second region of said gate array circuit and to a set of input pads along the periphery of said gate array circuit, said components in said second region of said gate array circuit being interconnected by said decoder interconnections so as to selectively couple said set of input pads to selected ones of said component selection interconnections; wherein activation signals transmitted via said input pads are selectively asserted on said component selection interconnections so as to activate selected groups of components in said first region of said gate array; multiplexer interconnections, coupled to components in a third region of said gate array circuit and to a set of output pads along the periphery of said gate array circuit, said components in said third region of said gate array circuit being interconnected by said multiplexer interconnections so as to couple predefined ones of said output pads to selected ones of said test signal interconnections; wherein test signals transmitted via said test signal interconnections are selectively asserted on said set of output pads, said test signals identifying defective components, if any, in said first, second and third regions of said gate array circuit.

4. The set of gate array circuit interconnections set forth in Claim 3, further including additional connections coupled to substantially all remaining components in said gate array circuit not included in said first, second and third regions of said gate array circuit, said additional connections coupling said remaining components to input/output pads along the periphery of the array of components to enable testing of said remaining components for defects; wherein said gate array circuit interconnections enable testing of substantially all components of said gate array circuit for defects.

5. A set of interconnections for testing components of a gate array integrated circuit, the gate array integrated circuit having an array of components arranged in rows and columns and a set of input/output pads along the periphery of the array of components, the set of interconnections comprising: row and column interconnections, coupled to all components in a core region of a gate array circuit, said row interconnections enabling selective activation of predefined groups of said components, said column interconnections carrying test signals generated by activated components in said gate array circuit; row decoder interconnections, coupled to said row interconnections and to components in at least a first peripheral region of said gate array circuit, and coupled to a set of input pads along the periphery of said gate array circuit, said row decoder interconnections selectively coupling said set of input pads to selected ones of said row interconnections; wherein row activation signals transmitted via said input pads are selectively asserted on said row interconnections so as to activate selected groups of components in said core of said gate array; column multiplexer interconnections, coupled to said column interconnections and to components in at least a second peripheral region of said gate array circuit, and coupled to a set of output pads along the periphery of said gate array circuit, said column multiplexer interconnections selectively coupling predefined ones of said output pads to selected ones of said column interconnections; wherein test signals transmitted via said column interconnections are selectively asserted on said set of output pads; said test signals identifying defective components, if any, in said core, first peripheral and second peripheral regions of said gate array circuit.

6. The set of gate array circuit interconnections set forth in Claim 5, further including additional connections coupled to substantially all remaining components in said gate array circuit not included in said core, first peripheral and second peripheral regions of said gate array circuit, said additional connections coupling said remaining components to input/output pads along the periphery of the array of components to enable testing of said remaining components for defects; wherein said gate array circuit interconnections enable testing of substantially all components of said gate array circuit for defects.

AMENDED CLAIMS

[received by the International Bureau on 4 September 1992 (04.09.92) ; original claims 1 and 5 amended; other claims unchanged (3 pages) ]

1. A method for fabricating gate array integrated circuits comprising the steps of: (a) generating a first set of base masks defining an initial set of base layers of an array of circuit components arranged in rows and columns;

(b) generating a set of test interconnection masks defining a set of interconnections enabling selective activation of said circuit components;

(c) fabricating integrated circuits using the base and test masks; (d) applying a sequence of test signals to said interconections and analyzing corresponding output signals generated by circuit components activated by said sequence of test signals so as to detect defects in said array of circuit components;

(e) if greater than a predefined number of defects are found in step (d), generating an additional set of base masks defining an additional set of base layers of said array of circuit components;

(f) repeating steps (b) through (e) until use of a final set of base masks in step (c) results in detection of a number of defects less than or equal to said predefined number of defects; (g) defining application specific integrated circuit (ASIC) interconnect masks;

(h) fabricating application specific integrated circuits using said final set of base masks and said ASIC interconnect masks.

2. The method of claim 1 wherein said set of interconnections includes a component selection interconnections enabling selective activation of predefined groups of said components with said sequence of test signals, and further includes test signal interconnections for carrying said corresponding output signals.

3. The method of claim 2 wherein said component selection interconnections include a first set of interconnections that interconnect ones of said circuit components so as to form decoder circuits that decode a first subset of said test signals and activate corresponding portions of the circuit components in said array of circuit components, and said test signal interconnections include a second set of interconnections that interconnect ones of said circuit components so as to form multiplexer circuits that selectively transmit ones of said output signals in accordance with a second subset of said test signals.

4. The method of claim 3 wherein step (d) includes the step of formulating a test program for generating said sequence of test signals and comparing said corresponding output signals to a predefined test pattern derived in accordance with said test program so as to identify defective components, if any, included within said array of circuit components.

5. A method for fabricating defect-free gate array integrated circuits comprising the steps of:

(a) generating a first set of base masks defining an initial set of base layers of an array of circuit components arranged in rows and columns;

(b) generating a set of test interconnection masks defining a set of interconnections enabling selective activation of said circuit components; (c) fabricating integrated circuits using the base and test masks;

(d) applying a sequence of test signals to said interconections and analyzing corresponding output signals generated by circuit components activated by said sequence of test signals so as to detect defects in said array of circuit components; (e) if defects are found in step (d), generating an additional set of base masks defining an additional set of base layers of said array of circuit components;

(f) repeating steps (b) through (e) until use of a final set of base masks in step (c) results in detection of no defects in step (d); (g) fabricating a plurality of base-layer integrated circuits using said final set of base masks in order to create a bank of said base-layer integrated circuits; (h) defining application specific integrated circuit (ASIC) interconnect masks;

(i) fabricating application specific integrated circuits by forming an interconnection pattern on said base-layer integrated circuits using said ASIC interconnect masks.

6. The method of claim 5 wherein said set of interconnections includes a component selection interconnections enabling selective activation of predefined groups of said components with said sequence of test signals, and further includes test signal interconnections for carrying said corresponding output signals.

7. The method of claim 6 wherein said component selection interconnections include a first set of interconnections that interconnect ones of said circuit components so as to form decoder circuits that decode a first subset of said test signals and activate corresponding portions of the circuit components in said array of circuit components, and said test signal interconnections include a second set of interconnections that interconnect ones of said circuit components so as to form multiplexer circuits that selectively transmit ones of said output signals in accordance with a second subset of said test signals.