WO1991019258A1 - Dimensionally reconfigurable multi-dimensional processor array - Google Patents
Dimensionally reconfigurable multi-dimensional processor array Download PDFInfo
- Publication number
- WO1991019258A1 WO1991019258A1 PCT/US1991/003341 US9103341W WO9119258A1 WO 1991019258 A1 WO1991019258 A1 WO 1991019258A1 US 9103341 W US9103341 W US 9103341W WO 9119258 A1 WO9119258 A1 WO 9119258A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processor
- dimensional
- cells
- array
- data signal
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/803—Three-dimensional arrays or hypercubes
Definitions
- This invention relates to parallel processors and more particularly, to a multi-dimensional processor system.
- Natural phenomena such as electric and magnetic fields, fluid flow, sound waves, and heat flow are, at any given moment in time, represented as spatially distributed data in a three dimensional manner by a number or set of numbers whose indices represent spacial positioning along three mutually orthogonal axes.
- a fourth dimension namely time, must also be considered.
- scientists and other computer users wishing to solve partial differential equations that involve spatially distributed data such as Poisson's or Maxwell's equations, have had limited data processing capabilities because prior art processors systems and processor arrays have been limited to one or two-dimensional architectures.
- Prior art attempts at dealing with three-dimensional data also include the utilization of an interconnection arrangement such as that disclosed in U.S. Patent No. 4,814,973 in which routers may be instructed to switch data between processor cells in a fashion that mimics the behavior of a three-dimensional processor array.
- Routers require a large amount of processor overhead to move data between the various processor cells.
- supporting control circuitry is required to perform the switching function.
- System throughput or bandwith is significantly compromised by the router overhead, and system cost and reliability are compromised due to the necessity of including the routers and associated control circuitry.
- the problem space of a given system of equations may be reduced to fewer dimensions, in which case a large number of processor cells within the multi-dimensional processor array would be unutilized and would not serve to provide additional processors to enlarge the problem solving space in the required dimensions.
- multi-dimensional processor arrays of 3 or more dimensions cannot utilize software developed to operate on processor arrays of fewer than 3 dimensions.
- a reconfigurable multi-dimensional processor array for processing data structured in one or more dimensions.
- the array may be automatically reconfigured as an array having one or more fewer dimensions, to provide a larger number of physical processors in the required dimensions, thereby increasing the size of the problem space without adding additional physical processors.
- Such a dimensionally reconfigurable processor array includes a plurality of processor cells arranged in N-dimensions and having a plurality of N-l dimensional processor subarrays.
- Each of the processor cells includes 2N data signal ports, operative for transmitting and receiving data to and from 2N dimensionally adjacent processor cells or data communications devices.
- Each of the N-l dimensional processor subarrays includes a number of processor cells coupled to 2N dimensionally adjacent processor cells or other data communications devices.
- Each N-l dimensional processor subarray also includes a selected group of processor cells coupled to fewer than 2N processor cells or data communication devices, and having at least one uncoupled data signal port operable for transmitting and receiving data to and from at least one additional processor cell or data communication device.
- An intermediate member connects selected uncoupled data ports from at least a first N-l dimensional processor subarray, to selected uncoupled data signal ports from a second N-l dimensional processor subarray, thereby forming selected data signal paths between selected processor cells from at least first and second N-l dimensional subarrays.
- Fig. 1 is an illustration of a three-dimensional
- processor array comprised of 36 processor cells
- Fig. 2 is a partially exploded view of the three-dimensional processor array of Fig. 1;
- Fig. 3 is a representation of a four dimensional 3 x 3 x 4 x 4 processor array
- Fig. 4 is an illustration of the four dimensional array of Fig. 3 reconfigured as a three dimensional 6 x 6 4 array;
- Fig. 5 is an illustration of a two dimensional 12 x 12 array reconfigured from the three dimensional array of Fig. 4;
- Fig. 6 is an illustration of the reconfiguration of the two dimensional array of Fig. 5 into a single dimension 144 cell array.
- the reconfigurable multi-dimensional processor array herein disclosed includes a multi-dimensional array, typically of three or more dimensions.
- Three dimensional processor array 10, Fig. 1 is a 3 x 3 x 4 array, comprised of (4) four, two dimensional 3 x 3 subarrays of processor cells 12, such as two dimensional subarrays 15-18.
- Each processor cell of an N dimensional array includes 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent other processor cells or data communication devices.
- each processor cell 12, Fig. 2, of each subarray such as subarray 16, shown in an exploded view includes six data signal ports 20a-20f which allow each processor cell to send and receive data to and from up to six adjacent processor cells or other data communication devices such as input/output devices.
- each processor cell is adapted for transferring data to and from up to six adjacent other processor cells or data communication devices, not all processor cells are conceptually positioned adjacent to six processor cells.
- processor cells 12a are conceptually located on one of the "faces" of the multi-dimensional processor array, and have at least one data signal port 22 which, for a given array configuration, is unused or whose input is ignored.
- data signal ports 22 form the basis of the reconfigurable multi-dimensional array described in greater detail below.
- Fig. 3 illustrates a four dimensional 3 x 3 x 4 x array 40 comprised of three dimensional 3 x 3 x 4 subarrays 42-48.
- interconnections forming four dimensional array 40 are omitted.
- Detailed functional and connectivity information about such an array may be found in co-pending U.S. Patent Application No. 07/530,027 entitled Multi-Dimensional Processor System and Processor
- Each subarray 42-48 includes a selected plurality of processor cells each of which has at least one previously unconnected data signal port 22.
- the processor array may be reconfigured to form a larger array of one or more fewer dimensions.
- the processor array may be reconfigured to form a larger array of one or more fewer dimensions.
- three dimensional subarrays 42-48 may be reconfigured to form a three dimensional 6 x 6 x 4 array 60, Fig. 4.
- Interconnecting member 50 may include a wire link, hardwiring to previously uncoupled signal ports together or alternatively, may be merely a software controlled and activated interconnection.
- three-dimensional subarrays 42-48 have been reconfigured in both the X and Y axes by joining subarrays 42 to 44 and 46 to 48 along the X axis, and subarrays 46 to 42 and 48 to 44 along the Y axis.
- this reconfiguration arrangement also maintains the previously defined data shifting paths among the individual processor cells in both the X and Y dimensions.
- three dimensional array 60 is now comprised of four, 6 6 two dimensional subarrays 52-58, reconfiguring the two dimensional arrays results in a 12 x 12 two dimensional array 70, Fig. 5.
- subarrays 52-58 In order to maintain a generally "square" two dimensional array while preserving the previously defined data shifting paths in both the X and Y dimensions, subarrays 52-58 have their previously unused or unconnected data signal ports selectively connected in the X and Y dimensions forming two dimensional array 70.
- two dimensional array 70 includes the plurality of one dimensional arrays in either the X or Y dimensions such as 12 x 1 subarrays 72, 74 and 76 these subarrays may be further reconfigured and joined in the X dimension forming 144 x 1 array 80, Fig. 6.
- the two dimensional array 70 of Fig. 5 could also have been reconfigured in a similar manner in the Y dimension.
- an array of N-dimensions may be reconfigured as an array of N-l, N-2, down to a one dimensional array directly, and is not limited to reconfiguring to an array of only one lesser dimension.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3511174A JPH09500740A (en) | 1990-05-29 | 1991-05-14 | Dimensionally reconfigurable multidimensional processor array |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US529,962 | 1990-05-29 | ||
US07/529,962 US5133073A (en) | 1990-05-29 | 1990-05-29 | Processor array of N-dimensions which is physically reconfigurable into N-1 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991019258A1 true WO1991019258A1 (en) | 1991-12-12 |
Family
ID=24111905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1991/003341 WO1991019258A1 (en) | 1990-05-29 | 1991-05-14 | Dimensionally reconfigurable multi-dimensional processor array |
Country Status (5)
Country | Link |
---|---|
US (1) | US5133073A (en) |
EP (1) | EP0532663A1 (en) |
JP (1) | JPH09500740A (en) |
AU (1) | AU8077291A (en) |
WO (1) | WO1991019258A1 (en) |
Cited By (3)
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WO1993019432A1 (en) * | 1992-03-17 | 1993-09-30 | Massachusetts Institute Of Technology | Low-neighborhood three-dimensional interconnect |
EP0610938A1 (en) * | 1993-02-11 | 1994-08-17 | Universities Research Association, Inc. | Three dimensional flow processor |
US5691885A (en) * | 1992-03-17 | 1997-11-25 | Massachusetts Institute Of Technology | Three-dimensional interconnect having modules with vertical top and bottom connectors |
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US6070003A (en) * | 1989-11-17 | 2000-05-30 | Texas Instruments Incorporated | System and method of memory access in apparatus having plural processors and plural memories |
US5367642A (en) * | 1990-09-28 | 1994-11-22 | Massachusetts Institute Of Technology | System of express channels in an interconnection network that automatically bypasses local channel addressable nodes |
US5280607A (en) * | 1991-06-28 | 1994-01-18 | International Business Machines Corporation | Method and apparatus for tolerating faults in mesh architectures |
US5659778A (en) * | 1992-02-03 | 1997-08-19 | Tm Patents, L.P. | System and method of mapping an array to processing elements |
JPH06325005A (en) * | 1993-05-14 | 1994-11-25 | Fujitsu Ltd | Reconstructible torus network system |
US5748942A (en) * | 1995-06-07 | 1998-05-05 | Xilinx, Inc. | Efficient three-dimensional layout method for logic cell arrays |
US5842034A (en) * | 1996-12-20 | 1998-11-24 | Raytheon Company | Two dimensional crossbar mesh for multi-processor interconnect |
KR100269174B1 (en) * | 1997-09-19 | 2000-11-01 | 윤종용 | Indirect rotator graph network |
US6973559B1 (en) * | 1999-09-29 | 2005-12-06 | Silicon Graphics, Inc. | Scalable hypercube multiprocessor network for massive parallel processing |
AU2471001A (en) | 1999-10-26 | 2001-05-08 | Arthur D. Little, Inc. | Multiplexing n-dimensional mesh connections onto (n + 1) data paths |
US6728863B1 (en) | 1999-10-26 | 2004-04-27 | Assabet Ventures | Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory |
US20040115995A1 (en) * | 2002-11-25 | 2004-06-17 | Sanders Samuel Sidney | Circuit array module |
TW200416522A (en) | 2003-02-25 | 2004-09-01 | Asustek Comp Inc | Portable computer carrying desktop computer processor and power management method thereof |
US7185138B1 (en) | 2004-05-14 | 2007-02-27 | Peter Galicki | Multi-dimensional data routing fabric |
US7725679B1 (en) * | 2004-09-13 | 2010-05-25 | The Mathworks, Inc. | Distributed arrays in parallel computing environments |
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- 1991-05-14 EP EP91912053A patent/EP0532663A1/en not_active Withdrawn
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Also Published As
Publication number | Publication date |
---|---|
EP0532663A1 (en) | 1993-03-24 |
AU8077291A (en) | 1991-12-31 |
JPH09500740A (en) | 1997-01-21 |
US5133073A (en) | 1992-07-21 |
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