WO1990015385A1

WO1990015385A1 - System and method for cyclical, offset multiport register operation

Info

Publication number: WO1990015385A1
Application number: PCT/US1990/002999
Authority: WO
Inventors: David L. Needle; Javier Solis; Glenn Keller
Original assignee: Atari Corporation
Priority date: 1989-06-02
Filing date: 1990-06-01
Publication date: 1990-12-13
Also published as: AU5857990A

Abstract

A multiport register set (50) has an eight deep addressable stack (52) of N-bit wide data words (54). The stack (52) has a port (56) at the bottom of the stack and a port (58) at the top of the stack. A read counter (59) is connected by bus (60) and a write counter (62) is connected by bus (64) to the stack (52) to provide 3-bit read and write addresses to the stack. Port (56) is connected to processing circuit (66) by an N-bit wide bus (68) to receive inputs from the stack (52). The output of the processing circuit (66) is connected by an N-bit wide bus (70) to port (58) to supply inputs to the stack (52). In operation of the register set (50), the multiport register set (50) does the reading and storing of data for the pipe, and the processing circuit (66) does the operation. Port (58) does all of the writing to the stack (52) and port (56) does all of the reading from the stack (52). The period for each address from the counters (59) and (62) is two of the clock cycles (80). The read address (82) needs to be ahead of the write address (84) by one clock cycle, thus allowing one cycle of overlap (86) when both counters (59) and (62) have the same address. Read and write counters (59) and (62) are allowed to count freely in a loop.

Description

SYSTEM AND METHOD FOR CYCLICAL, OFFSET MULTIPORT REGISTER OPERATION

BACKGROUND OF THE INVENTION

1. Field of the Invention;

The present invention relates generally to reading and storing information in multiport register sets. More particularly, it relates a way of operating such registers to increase processing throughput.

2. Description of the Prior Art;

The storage and retrieval of data from memory devices introduces dead time between the time data is read and the time the result is ready to be stored back into the location from which it was read. This arises from the sequential nature of the operations involved: first wait for data to read, then process the data, then save the results. With multi-ported memory devices, these operations can be done in parallel in order to eliminate some of the dead time that happens while the various operations take place. The concept of parallel operation is referred to as "pipelining" and has been used in places where an increase in processing throughput is needed. Pipelining does have an overhead to encounter every time the process needs to be started, commonly referred to as "filling the pipeline". This overhead can include putting data in special registers ready to be fed to the pipe, waiting for the various stages in the pipeline to have valid information, and the like. Once filling the pipeline has taken place, the increased performance obtained with pipelining will continue as long as the data lasts. Once the data has been handled, the pipeline will empty, and the entire process will have to be started all over again the next time it is used.

Many data processing environments include intermittently performed operations. An example is sound generation in a video game. Many game sounds are generated only on the happening of certain events, such as collisions, scoring or other sporadic events. Using conventional pipelining for the audio function of a video game results in substantially less improvement in processing throughput than continuously performed operations due to the repetitive overhead each time processing of audio information is restarted. A potential therefore exists to increase performance substantially if the overhead in setting up pipelined operations repeatedly can be eliminated by establishing uninterrupted operation of the pipeline for intermittently performed functions.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a pipelined data processing system and method in which full pipelining performance gains can be achieved with intermittently performed data processing operations.

It is another object of the invention to provide a pipelined data processing system and method in which the pipeline operation will run in an uninterrupted manner. It is a further object of the invention to provide such a pipelined data processing system and method which provides the pipelined performance gains in the processing of audio information for a video game.

The attainment of these and related objects may be achieved through use of the novel system and method for cyclical, offset ultiport register operation herein disclosed. A system for continuously pipelining information in accordance with this invention has an addressable memory with a plurality of access ports. A means is connected to the memory for supplying a read address to the memory identifying a location in the memory of information to be supplied to a first one of the access ports. A means is connected to the memory for supplying a write address to the memory identifying a location in the memory to which information is to be written from a second one of said access ports. The means for supplying a read address and the means for supplying a write address are connected to supply the read and write addresses in an overlapped period including two clock cycles, with one cycle of overlap in which the read and write addresses are the same.

In the method for continuously pipelining information, a read address is supplied to an addressable memory having a plurality of access ports, identifying a location in the memory of information to be supplied to a first one of said access ports. A write address is supplied to the memory identifying a location in the memory to which information is to be written from a second one of the access ports. The read address and the write address are supplied in an overlapped period including two clock cycles, with one cycle of overlap in which the read and write addresses are the same.

The attainment of the foregoing and related objects, advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention, taken together with the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a perspective view of a system in which the present invention is useful.

Figure 2 is a block diagram of the system shown in Figure 1.

Figure 3 is a block diagram of a multiport register set incorporating the present invention.

Figure 4 is a set of waveform diagrams useful for understanding operation of the multiport register set of Figure 3.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to the drawings, more particularly to Figure 1, there is shown a hand held electronic game system 10 which utilizes the present invention to improve processing throughput of audio information used to generate sounds in operation of the electronic game system 10. A conventional 6502 type microprocessor is used to provide real time graphics with an impression of three dimensions and perspective for a color liquid crystal display 12 used in the system 10. The system 10 includes conventional controls 14 and redundant sets 16 of buttons for firing weapons and similar functions. In use, the game system is grasped by handles 18 and 20 in the left and right hands, respectively, in the orientation shown. The redundant sets 16 of buttons allow the system 10 to be inverted for left hand operation of the buttons 16. When this is done, the orientation of the images on the display is flipped, so that it appears right side up when the sets 16 of buttons are on the left side of the system 10.

Those skilled in the art of graphics processing will appreciate the demanding memory and processing requirements for presenting real time, color graphics with realistic motion and an impression of three dimensions and perspective on the display 12. In fact, most personal computers are unable to present such realistic, graphics with rapid enough motion to make games interesting. Usually, only arcade games presently have such capability. This is why the displays for most personal computer based video games are crude and are only two-dimensional. Conventional hand held electronic games have even cruder, monochrome graphics. The system 10 is even more remarkable in that the real time, color graphics with realistic motion and an impression of three-dimensions and perspective are achieved by using a conventional 6502 type microprocessor, an early microprocessor design that has been available since the late 1970s. The system and method for cyclical, offset multiport register operation of this invention is one of the techniques used in the system 10 to enhance the performance of the 6502 microprocessor so that it is able to handle the data processing requirements of the system 10.

Figure 2 is a block diagram of electronics 30 for the system 10. A custom microprocessor integrated circuit 32 includes a standard 65C02 microprocessor CPU cell 34 and on chip interface and support circuits. The integrated circuit 32 is connected by a control bus 36 to a custom sprite engine integrated circuit 38, which also includes switch reader circuits for the switches 14 and 16 and read only memory (ROM) reader circuits for the ROM reader 40, included in the sprite engine integrated circuit 38 due to pin limitations on the microprocessor integrated circuit 32.

The integrated circuit 32 is connected to a 64K x 8 random access memory (RAM) 42 by 8-bit address and data busses 44 and 46 and by a 3-bit RAM control bus 48. The RAM 42 houses the video buffer(s) and collision buffer in addition to the game software. The RAM 42 has a 120 nanosecond row address strobe (RAS) access time and 60 nanosecond page mode column address strobe (CAS) access time. This allows a 250 ns (4 egaHertz) page mode memory access rate and a 312 ns (3.2 MHz) normal memory access rate.

The microprocessor integrated circuit 32 is connected to the liquid crystal display (LCD) 12 by a 4-bit video data bus 50 and an 11-bit video control bus 52. The LCD has a resolution of 160 horizontal color pixels by 102 vertical color pixels. The column drivers for the display 12 can generate 16 levels of intensity for each pixel, resulting in a palette of 4,096 colors. The present invention provides more efficient processing of audio information in the microprocessor integrated circuit 32 for producing sounds with the video game system 10. For purposes of this application, the remaining elements shown in Figure 2 are conventional in nature, and they therefore will not be described further.

Figure 3 shows a multiport register set 50, which is contained in the microprocessor integrated circuit 32, having an eight deep addressable stack 52 of N-bit wide data words 54. The stack 52 has a port 56 at the bottom of the stack and a port 58 at the top of the stack. A read counter 59 is connected by a 3-bit bus 60 and a write counter 62 is connected by a 3-bit bus 64 to the stack 52 to provide 3-bit read and write addresses to the stack. Port 56 is connected to processing circuit 66 by an N-bit wide bus 68 to receive inputs from the stack 52. The output of the processing circuit 66 is connected by an N- bit wide bus 70 to port 58 to supply inputs to the stack 52.

In operation of the register set 50, the multiport register set 50 does the reading and storing of data for the pipe, and the processing circuit 66 does the operation. Port 58 does all of the writing to the stack 52 and port 56 does all of the reading from the stack 52. The write counter 62 addresses the write port 58, and the read counter 59 addresses the read port 56. The two counters 59 and 62 must work in a particular manner, understanding of which is facilitated by the waveform diagrams of Figure 4. The period for each address from the counters 59 and 62 is two of the clock cycles 80. The read address 82 needs to be ahead of the write address 84 by one clock cycle, thus allowing one cycle of overlap 86 when both counters 59 and 62 have the same address. Latch signal 88 captures data that is being read from the read address 82. This signal needs to happen at the same time the write address 84 changes. The moment the write address 84 changes, the processing circuit 66 is ready to process the new data accessed from the read address. Write signal 90 happens at the end of a write address 84. By this time, the data that came in at the beginning of the current write address 84 has propagated through the processing circuit 66, and there is a result ready to be stored at the current write address 84.

Read and write counters 59 and 62 are allowed to count freely in a loop. When the maximum number has been reached, the counter will begin at zero again in this fashion:

0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,... This allows the register set 50 to continue operating indefinitely. Since the reading of data and the processing of data are always overlapped, the only net time used to process data is the time allocated for propagation through the processing circuit 66. The dead

^' time for reading new data has been eliminated, since the reading of the next data is done at the same time the current data is being processed. This increases the amount of data that can be processed because, as soon as the current data has been processed, new data is ready for the processing circuit 66.

In essence, this is a pipeline process that does not end. The results are stored right back in the same location where the data was accessed. This means that the data for the pipe will always be available to be continuously fed to the pipe. The process will never run out of data. Therefore, the overhead involved in starting conventional pipelined operations does not exist. This translates into a increase in the performance of the circuit. It should now be readily apparent to those skilled in the art that a novel system for cyclical, offset multiport register operation capable of achieving the stated objects of the invention has been provided. In this pipelined data processing system and method, full pipelining performance gains can be achieved with intermittently performed data processing operations. In the pipelined data processing system and method, the pipeline operation will run in an uninterrupted manner. The pipelined data processing system and method provides the pipelined performance gains in the processing of audio information for a video game.

It should further be apparent to those skilled in the art that various changes in form and details of the invention as shown and described may be made. It is intended that such changes be included within the spirit and scope of the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. A system for continuously pipelining information, which comprises an addressable memory having a plurality of access ports, means for supplying a read address to said memory identifying a location in said memory of information to be supplied to a first one of said access ports, and means for supplying a write address to said memory identifying a location in said memory to which information is to be written from a second one of said access ports, said means for supplying a read address and said means for supplying a write address being connected to supply the read and write addresses in an overlapped period including two clock cycles, with one cycle of overlap in which the read and write addresses are the same.

2 . The system for continuously pipelining information of Claim 1 in which said memory is a register stack.

3. The system for continuously pipelining information of Claim 1 in which said means for supplying a read address and said means for supplying a write address comprise counters which count in a recirculating loop to define successive read and write addresses.

4. The system for continuously pipelining information of Claim 1 in which said first one of said access ports is connected to an input of a processing means, said processing means having an output connected to said second one of said access ports.

5. A method for continuously pipelining information, which comprises providing an addressable memory having a plurality of access ports, supplying a read address to said memory identifying a location in said memory of information to be supplied to a first one of said access ports, and supplying a write address to said memory identifying a location in said memory to which information is to be written from a second one of said access ports, the read address and the write address being supplied in an overlapped period including two clock cycles, with one cycle of overlap in which the read and write addresses are the same.

6. The method for continuously pipelining information of Claim 5 in which said memory is provided in the form of a register stack.

7. The method for continuously pipelining information of Claim 5 in which the read address and the write address are supplied by counting in a recirculating loop to define successive read and write addresses.

8. The method for continuously pipelining information of Claim 5 additionally comprising the steps of processing the information supplied to the first one of said access ports to produce a result and supplying the result to the second one of said access ports as the information to be written from a second one of said access ports.