WO1990009666A1 - Improvements relating to control systems for chained circuit modules - Google Patents

Abstract

A control system for chained circuit modules includes global clock and command lines connected to all the modules in the chain and a serial line along which signals are clocked from module to module. A token bit received on the serial line is injected into a shift register on the module and then clocked along the shift register during the presence of a signal on the command line. A command for the module is invoked in dependence upon the position of the token bit in the shift register at the end of the command signal. The module also includes a means to park a token bit on the module ready for injection into the shift register.

Description

  
 



   IMPROVEMENTS RELATING TO   WNTROL      SYSTEMS       FOR CHAINED cIRwrnT #DDUT#S   
 The present invention relates to   improvements    in a control system, for chained circuit   modules    of the type which is, for example, described in GB 2177825.



   It is well known to connect a plurality of memory or processing circuit   modules    in a chain   (GB    1377859 for example). The   modules    could be a plurality of chips on a circuit board, or may be a plurality of undiced chip areas on an integrated circuit wafer.



   The chips are all accessed from a single I/O port   or    bondsite. A method for growing the chain of   modules    is described in
GB 2177825. A global command line connected to all the modules is provided to send instructions to all the modules simultaneously. This is achieved by asserting the global command (CMND) line for an integral number of clock cycles. The number of clock cycles for which
CMND remains asserted determines the specific instruction executed by the chips in accordance with the stage of a shift register arrangement into which a bit is clocked while CMND remains asserted. In the case of a wafer scale integrated circuit (WSI) the clock is the wafer clock   (WCK)    and is connected to all the chips on the wafer   by a    global line
WCK, thereby clocking them simultaneously.

  A portion of a WST circuit including the WOK and   CMND    global lines and global power lines Vss and
VDD is shown in Figure 1. The global lines form a grid around the   modules    10 (undiced chip areas) and all go to a bondsite on the edge of the wafer.



   In addition to global functions it is also necessary to be able to send instructions to individual chips. These are shown as local functions. One method of   implementing    these local functions is described in GB 2177825.



   Transmit input paths XINN, XINE, XINS, XINW, and transmit output paths   XOUTN, XCUTE,      XOUTS,    XOUTW between neighbouring   mDdales    10 (see Figure 2) connect the modules in a chain. The transmit path through the modules has 1-bit latency per module and is set up by four selection signals SELN, SELE, SELS, SELW which act on à transmit path logic circuit and a receive path logic circuit in a return path.  
The transmit path and the return path   ( IIT    and   READ7)    extend respectively from and to terminals at   the      oorldsite    on a wafer.



   To assert a local function a single bit of one clock pulse duration is sent along the XMIT path. The single bit is known as a token. This single bit is clocked from chip to chip by WOK along the   XMTT    path which is grown between the chips 10 in accordance with data from a spiral path list. The chain of modules configured by data from the spiral path list therefore forms an N bit shift register along which the token is clocked, where N is the number of chips in the chain.



   If   CMND    is asserted whilst the token is present in a chip, then that chip will be addressed and a local function will be executed on that chip. This is achieved by latching the token within the transmit path logic and clocking it along a shift register in the configuration logic of the chip. The position that the token has reached in the shift register when   CMND    goes low will determine which local function is executed.



   This method of executing local functions involves a time delay between the generation of a token at the bondsite and its arrival at a chip where it is desired to execute a local function.



  This time delay will be particularly long for chips at the end of a chain remote from the bondsite and on average of length N/2 clock pulses where there are N chips in the chain. N may be 256 for example.



   One object of the present invention is to reduce the time delay in executing at least one of the local functions on chips in a chain of circuit   modules.   



   Various aspects of the present invention are defined in the appended claims.



   The invention will now be described in more detail by way of example with reference to the drawings in which:
 Figure 1 shows the prior art arrangement of global lines between modules described above;
 Figure 2 shows the prior art arrangement of transmit paths between   modules    described above;
 Figure 3 is a block diagram of the configuration logic and memory of a DRAM chip in a control circuit embodying the invention;  
 Figure 4 is a   more    detailed block   diagram,    of the configuration logic of Figure 3;
 Figure 5 is a block diagram of the   global    logic portion of
Figure 4;
 Figure 6 is a block diagram of the selection logic portion of Figure 4, and
 Figure 7 shows circuits involved in controlling the read/write address counter of a chip.



   The block diagram of a DRAM chip shown in Figure 3 comprises a   inory    area 20 and a configuration logic area 22. The memory area is essentially a conventional DRAM, e.g. a 1 Mbit DRAM and the configuration logic provides a means of communication between nearest neighbour chips and the control of memory accesses within any given chip.



   The XIN, XOUT, BIN and ROUT wires on each chip provide a method of   communication    between nearest neighbour chips in a manner described in GB 2177825.



   Data is read in and out of the   memory    area 20 by the RAMDATA
Bus under the control of signals provided by the configuration logic along the RAM Control Bus   (RAb##ThL).    RAMDATA is a 4 line bus and   RAMCTRL    a 13 line bus including 9 address lines plus RAS, CAS, OEL and WEL as required by a normal DRAM. The 9 address lines used for both a row and a column address allow 256k address to be accessed. Each access is to 4 bits, so total capacity is 1Mb, and there is serialparallel conversion between the 4-bit-parallel structure on the
RAMDATA bus and the bit-serial structure on XMIT and   RECV.   



   In addition to the method of invoking local   commands    described in   GB    2177825 there is a supplementary method of invoking local   commaods.    This removes any time delay (latency) in generating the token at the bondsite and clocking it through the chips in the chain to the desired chip. This method uses the concept of a "Parked
Token" on a chip, which can be used to invoke local functions by controlling only the CMND line.



   An injected token is parked on a chip when that chip is addressed by a   XMIT/CMND    sequence to invoke a particular local function. The chip is then said to be in an addressed state and   will    remain in this state until an explicit global   command    is sent to de  address the chip by clearing the parked token. Once the token is parked, certain local functions can be invoked by controlling   onsy      #iND    line. In this particular embodiment of the invention there are several functions that can only be invoked after the execution ot particular local functions. These are called Primed Functions and are only invoked after a previous local function has parked a token on the chip.

  These primed functions are invoked in the same way as global functions and consequently can be executed quickly since there is no delay waiting for a token to reach the chip to be addressed.



   The local, global, and primed functions which can be
 invoked in the embodiment described here are listed in table 1 below
 which also explains briefly what each function does:
 TABLE I
Global:   CMND=01:    INIT - reset the wafer to a known state, used
 after initial power up.



  Primed:   AND=02:    ACONE - set address counter bit to logical one,
 used to initiate start address value for
 read or write (requires chip to be in
 address counter load mode as a
 consequence of executing a local   ACLOAD   
 function before the first ACONE
 function). The MSB of the address
 counter is loaded first in any load
 sequence.



  Primed:   CMND=03:    ACZERO - as for ACONE, setting address counter
 bit to zero.



  Primed:   CMND=04:    TRP - trigger a   memory    row pre-charge sequence
 during read or write (requires chip to
 be in read or write mode as a
 consequence of executing a local READ or
 WRITE function before the first   TRP   
 function).



  Primed:   CMND=05:    STSP - start or stop data transfer if in read
 or write mode (requires chip to be in
 read or write mode as a consequence of
 executing a local READ or WRITE function
 before the first STSP function). This
 is a toggling function, set initially to  
 STOP by INIT.   After    INIT any successive
 STSP function   Wi    assert and negate
 alternatively the START state (STOP   ¯s   
 NOT START). STSP requires the presence
 of a parked   token.   



     Global:    CMND=06: CLR SEL - Resets value in SELECTION REGISTER to
 logical zero.



  Global: CMND=07: CLR PARK - Clears any parked   tokens.   



  Global: CMND=08: CLR FUN - Resets value in FUNCTION REGISTER to
 logical zero.



  Local: CMND=09: SELN - Select the northern exit direction of
 the XMIT path from addressed chip in the
 SELECTION REGISTER.



  Local: CMND=10: SELE - Select the eastern exit direction of the
 XMIT path from addressed chip.



  Local: CMND=11: SEES - Select the southern exit direction of
 the XMIT path from addressed chip.



  Local: CMND=12: SELW - Select the western exit direction of
 the XMIT path from addressed chip.



  SELN to   SELW    also select the appropriate entry direction for the   RECV    path into the addressed chip.



  Local: CMND=13: READ - Selects READ mode for data transfer from
 memory.



  Local: CMND=14: WRITE - Selects WRITE mode for data transfer
 into memory.



  Local: CMND=15; ACLOAD - Selects address counter load mode;
Local: CMND=16:   SCR    - Resets SKEW COUNTER (contained in
 addressed chip) to logical zero.



  Local: AND=17:   SCREEN    - Selects length of SKEW COUNTER.



  Local: CMND=18: RPON - Toggles RAM   POWER-ON    LATCH (RPON). RPON
 set to zero by INIT.



  The last three   commands    will not be considered further herein. Each chip has a free running refresh address counter (separate from the  read/write address counter described below) for effecting   DRAM    refresh. The skew counters are used to stagger the refresh cycles   0    the chips so as to even out power supply demands, as explained   in   
GB 2 178 204, which also describes the use of RPON.



   A block circuit diagram of the configuration logic of Figure 3 is shown in Figure 4. For the purposes of clarity not all the connections between the blocks of the circuit are shown.



   The configuration logic comprises a global logic unit 24 which decodes global functions and primed functions and generates control signals for the other blocks in the diagram. A selection logic unit 26 decodes four local functions   SELN    to SELW and latches a parked token after an   XMlW(24ND    sequence. A function logic unit 28 decodes a further six local functions, READ, WRITE,   AGLOAD,      SCR,      SCORN,    and RPON, of which only the   ACLOAD    function is shown in this figure.



   These three units 24, 26, 28 all contain parts of a shift register known as the   command    register   (COMREG)    which allows a single logical one generated on the first clock cycle that   OMND    is asserted to propagate along it. This logical one is generated by the global logic. The stages of the   COMREG    in the selection and function logic also require the presence of an XMIT token, or a parked token in the selection logic 28, to propagate the logical one.



   The four XIN lines from neighbouring chips are OR's together to provide the serial input signal XMIT, which is applied to the selection logic 28 and a RAM interface logic unit 32. The selection logic 28 propagates the XMIT path to an XMIT path logic unit 34 which selects one of four outputs XOUTN to XOUTW in accordance with a SEL signal received from the selection logic 36, as in
GB 2177825.



   A receive path   rmiltiplexer    36 selects the receive input from one of four neighbouring chips, the selected input corresponding to the direction selected for the XMIT path logic 34 by the SEL signal.



  This provides a signal   RECV    to a receive path logic unit 38 which selects a source of data from   RECV,      RUM TEA    provided by the RAM interface logic 32, or TEST data (not shown) and   makes    the selected source available at four outputs (RON to   R:W).     



   An 18-bit address counter 40 generates addresses for the   DRAM    20 and supplies them to an address   multiplexer    42   which    can scramble the address lines for a fault masking technique described in our   European   
Patent Application filed on the same day as this application   with    the title "Fault Masking in Semiconductor Memories" claiming priority from
British Patent application 8903180.1. The address counter 40 can   be    preset to a desired address by using the   ACIDAD,    ACONE, and   ACZERO    functions so as to access a particular area of the   DRAM    20.



   The RAM interface logic unit 32 generates all the conventional timing signals required by the DRAM 20 and includes two shift registers for conventional serialisation and deserialisation of data read to and from the DRAM four bits at a time.



   The global logic unit 24 is shown in more detail in   Figure    5 and is idle until it detects that   CMND    has been asserted. The   global    logic 24 comprises a D type flip-flop 44 with its input connected to the   CMND    line and its output connected to an AND gate 47. The other input to the AND gate 47 is also the   OMND    line. When   CMND    is asserted this flip-flop and AND gate arrangement generate a single bit when the flip-flop 44 is clocked by WOK. This single bit is the input to a shift register arrangement formed from eight cascaded D type flipflops 48.

  Each of these flip-flops is clocked by the wafer clock WOK and the single bit therefore   moves    along the shift register and   is,    available at the output of the respective flip-flop 48 after each clock pulse.



   The outputs of the flip-flops 48 are connected to further flip-flops 50 which act as latches when clocked. The clock inputs to these flip-flops 50 are connected to   ONND    and they will all be clocked when   OMND    goes low. Thus the single bit in the shift register will be latched onto the appropriate flip-flop. The outputs of these latches 50 are used to invoke the global   cammands    with which they are labelled in other parts of the configuration logic.



   The shift register arrangement of   Fig. 5    is the portion of the   CCMREG    in the global logic 24.



   The   CMND    line is inverted at its input to provide an   ENDOMND    signal at an output and then inverted back to its original state.



      If a bit is clocked all the way through the' ## portion    of the global logic 24, it then becomes available at an output     NGGLDBt#L    which is used to enable the selection logic 26.



      reset of the complete CiR¯G Is performed by the output of    the flip-flop 46, which is connected to the clear inputs of all the flip-flops 48, going false. This RSTSHIFT signal is also available as an output from the global logic and forms a clear input to the selection logic 26 and the function logic 28.



   The other output of the global logic is the output of the first stage of the shift register. This is known as the   octricand    pulse   OPI    and is also available at an input to the selection logic 26.



   The first eight functions listed above in Table 1 will be invoked according to the number of clock pulses for which   CMND    remains asserted. These include the four primed functions ACONE, ACZERO,   TRP,    and STSP. All the functions described will generate a single pulse of one clock cycle duration except for the STSP function which toggles a static start/stop signal connected to the RAM interface logic 32. This static signal is held on a further latch 52 and inverter 54.



   The primed functions ACONE and   AOZERO    require a previous   AOLDAD    command to have been invoked and this will have parked a token in the selection logic 26.   AOLDAD    switches the Adddress Counter 40 into shift register mode and ACONE and   ACZERO    switch the input of this shift register between high and low to load a desired start address into the address counter. TRP and STSP both require a chip to be in
READ or WRITE mode as a consequence of executing a local READ or WRITE function and these functions will also have parked a token in the selection logic 26.



   When   CMND    is asserted for   more    than eight clock pulses, the global logic 24 provides a signal   NO#LOBAL    to the selection logic 26.



  This enables an XMIT pulse or a parked token to be injected into a four stage parallel shift register which generates the four SEL signals, which are of course mutually exclusive, and is the next stage of the   COMREG.   



   A block diagram of the selection logic 26 is shown in Figure 6. It comprises a fast acting flip-flop 56 with inputs   81    and XMIT.



  The further inputs INIT and   CERPARK    each clear the   flipflop    56 which acts as a token park. A token is parked on the flip-flop 56 every time a local command on the chip is invoked by a CMWD/XMIT sequence.  



  The PARK output of the flip-flop 56 is connected to one input of an   AI\TD    gate 58. The   other    input to this AND gate is the   NOGLOBAL    line and thus   when      NOGLOBAL    and PARK are   high,    a token bit is available at the output of the AND gate 58.



   This token bit is injected into the first stage of a further portion of the COMREG which is formed from a four stage shift register comprising four D type flip-flops 60. The token is clocked along this shift register by successive clock pulses WOK. The output of each flip-flop 60 is available at the input to one of four further D type flip-flops 62 which act as latches to enable one of the four SEL outputs. The respective flip-flop 62 has its output latched by the   ENDCMND    signal from the global logic which is ANDed in AND gate 64 with the output of OR gate 66. The inputs to OR gate 66 are the outputs of the four flip-flops 60.



   The four flip-flops 60 can be cleared by the   RSTSHIFT    signal provided by the global logic.



   If a token bit is clocked all the way along the   CCMREG    portion of the selection logic, it then becomes available as a NOTSEL output which forms an input to the function logic 28.



   Once set, the selected output of the selection logic is preserved independently of other global, local, or primed functions apart from a subsequent SEL local   command,    the global   command      IRIT    or the global function   CLRSEL    which clears all the flip-flop latches, 62.



   A SEL function can be invoked by either a   CMND/XMIT    sequence or by a   CMND    pulse of the required duration   after    a token has been parked by an earlier   CMND/XMIT    sequence. The SEL function is invoked by a   CMND/XMIT    sequence if the token coincides with the rising edge of the ninth clock cycle after a   CMND    sequence was started or if a token is present in the first flip-flop.



   The status of the selection logic can be tested by observing a self-selection output (SELSEL), which will give a pulsed output of duration 1, 2, 3, or 4 clock pulse widths depending on the SEL   output    selected.



   If one of the local functions implemented in the function logic 28 is to be invoked then an injected or parked token   must    be passed on as   NOTSEL    from the selection logic 26 on the rising edge of the thirteenth clock cycle after   CMND    is asserted. Thereafter the  function logic decodes the READ, WRITE, ACLOAD,   SCR,      SCORN,    or RPON   functions    on the 13th to 18th clock cycles respectively for which   CMND    remains invoked. This is achieved by clocking the token which is received from the NOTSEL output of the selection logic 26 (parked or injected) with successive clock pulses along a shift register in the function logic until   CMND    goes low.

  This shift register (COMREG) acts in a   similar    manner to that in the selection logic and is therefore not illustrated.



   The function logic decodes are   mutually    exclusive but they are static signals and remain unchanged independently of other local, global, or primed decodes except for a subsequent READ, WRITE, or   ACCORD    local decode, or the CLRFUN global function that returns the shift register outputs and latches to the all zero condition.



   The Park output of the selection logic is an input to the
RAM interface logic 32 and is used to enable the primed functions STSP and TRP when a   OMND    pulse of the appropriate length is received.



   It will be appreciated that using this method of parking tokens leads to considerable savings in time for invoking local functions on chips in a chain. For   example    if a READ instruction is to be sent to the fiftieth chip in a chain which does not have the facilities to park tokens then firstly fifty clock cycles will be needed to clock an injected token to that chip. Then another thirteen clock cycles will be required for the   CMND    line to be invoked for the correct length of time to involve the READ function. This gives a total of 63 clock cycles in all to invoke the function. If, however, the chip had a parked token on it, only 13 clock cycles would be needed to invoke the READ function.



   Fig. 7 shows part of the RAM interface logic 32, including the address counter 40, just the first   flipflop    70 thereof being shown specifically. The counter is   composed    of eighteen flip-flops which constitute an 18-bit conventional   binary-counter    in normal counting mode, in which each   flip-flop    (other than the first) changes state only when the preceding flip-flop switches   from    "1" to "0". The first flip-flop 70 changes state on every WOK pulse, provided through an AND gate 72 and an OR gate 74 to all flip-flops of the counter.



  The AND gate 72 is enabled via an inverter 76 when   ACLSAD    is false.



     ACLQAD    determines whether the normal counting   mDde    obtains or whether     (AGILIAD    true) the counter 40 is switched to a shift register connection in which each flip-flop (other than the first) copies the state of the preceding flip - the load mode. Such a change of counter configuration is known per se and is controlled in   Fig.7    by the signal on a line 78.



   Reverting to consideration of the normal mode, the change of state of the first flip-flop 70 on each clock pulse WOK requires the presence of a signal ENABLE and   AODIAD    false. ENABLE true causes the output of the flip-flop 70, inverted by an inverter 80 to produce an inverted output on the D input of the flip-flop via an exclusive OR gate 82, an AND gate 84 and OR gate 86. The AND gate 84 has to be enabled, which requires   AODDAD    false. If ENABLE is false the output of the flip-flop 70 is copied back to its input so that the state of the counter 40 is frozen.



   ENABLE is essentially a copy of the primed   corrpaand      SIIISP    provided by way of a flip-flop 88. However the flip-flop is clocked by   WOK/4    since the fact that the DRAM is written and read four bits at a time means that   memory    accesses are actually at quarter clock rate and ENABLE must change state only at the correct phase of a fourclock-pulse cycle. The second point to note about the flip-flop 88 is that it is held cleared so long as PARK is false. This is the way in which STSP is made a primed function. If PARK is false, ENABLE is held false. If PARK is true, ENABLE will copy STSP and turn the address counter 40 on and off for reading or writing, as selected by the local   commands    READ, WRITE.

  The implementation of these commands is not illustrated since it is a conventional aspect of any RAM.



   Turning now to the load mode of the counter 40, the clock pulses which will act to shift the shift register into which the counter is now configured are now provided only one at a time whenever either an   AC0NE      command    or an ACZERO   command    is received.



  Thus these signals are applied to an OR gate 90 whose output is applied to an AND gate 92. This gate is enabled by   ACLQXD    (and the gate 72 is disabled) and the gate 92 then provides the clock pulses via the OR gate 74.



   ACONE buffered in a flip-flop 94 moreover provides the D input for the flipflop 70 via an AND gate 96   when    this is enabled by   ACIDAD    (and the gate 84 is disabled). Each occurrence of ACONE  causes a "1" to be clocked into the first counter flip-flop 70.



  Each occurrence of   ACZERO    causes a "0" to be clocked in. A sequence of eight ACONE and   ACZERO    commands is required to enter all eighteen bits of a new address, in order of decreasing significance. These commands are assigned to short values of   CMND    (Table 1) to allow a new address to be set up quickly.



     ACIDAD    is a local command which can only be asserted when a token bit from XMIT has been passed to the function logic 28 (Fig.3) as NOTSEL, via the selection logic 26. Accordingly   ACLOAD    is a special case of a parked token and it determines whether or not the primed commands ACONE and   AOZERO    act on the counter 40.



   As noted above the function logic 28 is not described, being no different in principle from the selection logic 26. It will be noted that the local command CLRFUN clears any flip-flop in the function logic latching a   command    and will, in particular, clear   AOLDAD.    CLRFUN is therefore used at the end of setting up a new address in the counter 40, prior to use of either READ or WRITE and then use of STSP to control the flow of data from or to the DRAM 20.



   The implementation of TRP is not illustrated. It is concerned with a detail of RAM refresh during read and write operations and it is treated as a primed   command    in a manner analogous to the treatment of STSP, as described above with reference to Fig.7.



  The implementation of SEEN to   SELW    is likewise not described, being in substance as in GB 2 177 825. INIT behaves as a conventional initializing or reset signal. 

Claims

cL#JT##:

A control system for chained circuit modules (10) ea#ch of atich can execute a selected one of a plurality of commands, wherein each module includes at least a first shift register arrangement (26) resFOnsiveL to clock pulses provided to all modules in the chain, all the modules are connected to a global command line and each module is capable of,, being,

addressed by a command signal received on the global command lin# and the coincident presence of a token bit injected into its first shift register arrangement (26) through the preceding itodules in the chain to execute a selected command determined by the position of the token bit at the end of the command signal, characterized by a means (56)for parking a token bit on a module to place the module in a latched addressed state.

2. A control system according to claim 1, characterized in that a token bit parked in the parking means (56)is injected into the first shift register arrangement in response to the command signal received on the global command line, in lieu of a bit supplied through the preceding modules in the chain.

3. A control system according to claim 1 or 2, characterized by a second shift register arrangement (24) preceding the first shift register arrangement (26)into which a bit is injected in response to the command signal and selecting further commends in dependence upon the location of the bit therein at the end of the command signal, and further tut characterized in that the injection of a bit into the following first shift register arrangement (26)is conditional on the emergence- of a bit from the second shift register arrangement (24).

4. A control system according to claim 3, characterized in that the execution of at least one command selected by the second shift register arrangement (24)is conditional upon the presence of a parked token bit.

5. A control system according to claim 3, characterized in that the execution of at least one command selected by the second shift register arrangement (24)is conditional upon the prior execution of a particular command selected by the first shift register arrangement (26).

6. A control system according to any of claims 1 to 5, characterized in that one of the commands clears the parked token bit.

7. A control system for chained circuit modules (10) each of which can execute a selected one of a plurality of commands, wherein each module (1G) includes logic (22) for decoding the commands and a random access memory (20) addressed by an address counter (40) clocked in response to a clock pulse distributed to all the modules for at least read out of data to a path extending through the chain of modules to an external terminal, characterized in that the commands decoded by the said logic (22) include, in addition to a read command, at least one further command for starting and stopping the counter to control the reading of data from the RAM.

8. A control system as claimed in claim 7, characterized in that a single further command toggles the address counter (40) between freerunning and stopped states.

9. A control system for chained circuit modules (10) each of which can execute a selected one of a plurality of casmEnds, wherein each module (10) includes logic (22) for decoding the commands and a random access memory (20) addressed by an address counter (40) clocked in response to a clock pulse distributed to all the modules for at least read out of data to a path extending through the chain of modules to an external terminal, characterized in that the ccgrmands decoded by the said logic include a first command which reconfigures the address counter (40) into a shift register, a second command for clocking a "1" bit into the shift register, and a third command for clocking a "0" bit into the shift register,

for establishing an initial address therein determined by the sequence of second and third commands sent to the module following a first corranand.

10. A control system as claimed in claim 9, characterized in that the commands decoded by the said logic (22) further include a fourth corrpnand for reconfiguring the address counter as an address counter again after the said initial address has been established.

control syscemcontrolsystemas claimed in claim 7 or 8, characterized in that the said logic (22) includes a shift register arrangement responsive to the clock pulses and to a command signal provided to all modules toi clock a token bit along the shift register arrangement, the selected, command being determined by the position of the token bit at the end of the command signal, in that the shift register arrangement comprises a first portion (24)into which a token bit is injected in response to the command signal and a second, subsequent portion (26,

28) in which propagation of the token bit only continues when the module is in an addressed' state established by coincidence between a token bit sent to that module along the chain of modules and the command signal, and in that the said, further command is decoded by the first portion of the shift register arrangement whereas the read command is decoded by the second portion of the shift, register arrangement.

12. A control system as claimed in claim 9 or 10, characterized in that the said logic comprises a shift register arrangement responsive to the clock pulses and to a command signal provided to all modules to clock a token bit along the shift register arrangement, the selected command being determined by the position of the token bit at the end of the command signal, in that the shift register arrangement comprises a first portion (24) into which a token bit is injected in response to tbe command signal and a second, subsequent portion (26,

28) in which propagation of the token bit only continues when the module is in an addressed state established by coincidence between a token bit sent to that module along the chain of modules and the command signal, and in that the first command is decoded by the second portion of the shift register arrangement whereas each of the second and third commands is decoded by the first portion of the shift register arrangement.