WO1988007722A3 - Improvements in or relating to cellular array processing devices - Google Patents

Improvements in or relating to cellular array processing devices Download PDF

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Publication number
WO1988007722A3
WO1988007722A3 PCT/GB1988/000235 GB8800235W WO8807722A3 WO 1988007722 A3 WO1988007722 A3 WO 1988007722A3 GB 8800235 W GB8800235 W GB 8800235W WO 8807722 A3 WO8807722 A3 WO 8807722A3
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WO
WIPO (PCT)
Prior art keywords
processing
pes
network
circuit
arrangement
Prior art date
Application number
PCT/GB1988/000235
Other languages
French (fr)
Other versions
WO1988007722A2 (en
Inventor
William Howard Considine
Original Assignee
Stonefield Systems Plc
William Howard Considine
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stonefield Systems Plc, William Howard Considine filed Critical Stonefield Systems Plc
Publication of WO1988007722A2 publication Critical patent/WO1988007722A2/en
Publication of WO1988007722A3 publication Critical patent/WO1988007722A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/20—Image enhancement or restoration by the use of local operators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Abstract

In each processing element of an array an input gate arrangement IG is provided with parallel AND-gates, holding register and ranking network which can be selected to provide outputs (derived from multiple bit neighbouring pixel values) for supply to either a generally conventional processing element PE2 or to a processing circuit PES which together with element PE2 forms an enhanced processing element. A bit summing network (11) in the circuit PES forms a count value signal representing the number of bits of a predetermined logic type supplied to inputs of the network (11), e.g. from the parallel AND-gates in arrangement IG. This count value signal is processed in adder (12) and accumulator (13) for example to form a convolution image value. The ranking network in the arrangement IG can be used to select for further processing a neighbouring pixel value of predetermined rank. Thus the components provided in circuit PES supplement the generally conventional element PE2 to enable simultaneous processing of a plurality of corresponding bits (same bit plane) of neighbouring pixel values so that convolutions and other image processing operations previously requiring inordinate time or hardware outlay are made economically possible at high speed. The components provided in device PES can be used in providing addition, substraction, multiplication and division operations as well as geometric transformations at enhanced speed.
PCT/GB1988/000235 1987-03-28 1988-03-28 Improvements in or relating to cellular array processing devices WO1988007722A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8707493 1987-03-28
GB878707493A GB8707493D0 (en) 1987-03-28 1987-03-28 Cellular array processing

Publications (2)

Publication Number Publication Date
WO1988007722A2 WO1988007722A2 (en) 1988-10-06
WO1988007722A3 true WO1988007722A3 (en) 1988-10-20

Family

ID=10614878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1988/000235 WO1988007722A2 (en) 1987-03-28 1988-03-28 Improvements in or relating to cellular array processing devices

Country Status (2)

Country Link
GB (1) GB8707493D0 (en)
WO (1) WO1988007722A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2711436B1 (en) * 1993-10-18 1996-01-05 France Telecom Improved method of operating several computing units in parallel, in particular in image processing, and corresponding architecture.
SE9402551L (en) * 1994-07-22 1995-10-30 Integrated Vision Prod Device for an image processing processor
US7035331B2 (en) 2002-02-20 2006-04-25 Intel Corporation Method and apparatus for performing a pixel averaging instruction

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3941990A (en) * 1972-12-29 1976-03-02 Compagnie Industrielle Des Telecommunications Cit-Alcatel Series type adder for adding plural binary numbers
EP0073116A2 (en) * 1981-08-18 1983-03-02 National Research Development Corporation Integrated data processing circuits
EP0144123A2 (en) * 1983-10-05 1985-06-12 National Research Development Corporation Digital data processor for multiplying data elements by coefficients
EP0147857A2 (en) * 1983-12-28 1985-07-10 Hitachi, Ltd. Parallel data processing system
EP0206892A1 (en) * 1985-06-10 1986-12-30 Commissariat A L'energie Atomique Processing method for digital signals representing an original picture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3941990A (en) * 1972-12-29 1976-03-02 Compagnie Industrielle Des Telecommunications Cit-Alcatel Series type adder for adding plural binary numbers
EP0073116A2 (en) * 1981-08-18 1983-03-02 National Research Development Corporation Integrated data processing circuits
EP0144123A2 (en) * 1983-10-05 1985-06-12 National Research Development Corporation Digital data processor for multiplying data elements by coefficients
EP0147857A2 (en) * 1983-12-28 1985-07-10 Hitachi, Ltd. Parallel data processing system
EP0206892A1 (en) * 1985-06-10 1986-12-30 Commissariat A L'energie Atomique Processing method for digital signals representing an original picture

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Conference Proceedings, IEEE Southeastcon '85, Raleigh, North Carolina, 31 March - 3 April 1985, IEEE (New York, US), D.K. Fronek et al.: "Vision -- Real time image processing using a hard-ware neighborhood convolver", pages 182-186 *
IBM Technical Disclosure Bulletin, volume 19, no. 11, April 1977, (New York, US), M. Cukier et al.: "Multiple input serial adder using counter", pages 4215-4216 *

Also Published As

Publication number Publication date
GB8707493D0 (en) 1987-08-05
WO1988007722A2 (en) 1988-10-06

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