WO1988002210A1

WO1988002210A1 - Electrical isolation device

Info

Publication number: WO1988002210A1
Application number: PCT/AU1987/000313
Authority: WO
Inventors: Graham John Rogers
Original assignee: Baysage Pty. Ltd.
Priority date: 1986-09-15
Filing date: 1987-09-15
Publication date: 1988-03-24

Abstract

An electrical isolation device and circuit mounted on a circuit board for providing at least 7kV isolation between low voltage (of the order of 10-50V) and high voltage (of the order 120V AC-420V AC) components when mounted on the circuit board or equivalent. Isolation is accomplished, in part, by provision of an air gap (13) of specified dimensions in the circuit board located beneath integrated circuit isolator chips (10, 11, 12). A particular low voltage logic drive circuit for an opto-isolator/Triac driver chip (IC3) is also disclosed wherein the chip (IC3) has high and low voltage connecting pins and opto-isolation means having conduction disable means (IC2) operable during a predetermined period of time connected between a first one of the low voltage connecting pins; the opto-isolation means having logical power supply means connected to a second one of the low voltage connecting pins (pin 2 of IC3); the logical power supply means (IC1) arranged to supply power for a predetermined period of time to the second one (pin 1 of IC3) of the low voltage connecting pins. The device is particularly suited as a solid state replacement for relay based coin operation mechanisms as used in fairground equipment and the like.

Description

ELECTRICAL ISOLATION DEVICE

TECHNICAL FIELD

The present invention relates to electrical isolation devices, and in particular, to devices suited to provide adequate electrical isolation under predetermined conditions between consumer mains supplies of the order of 240 volts AC and low voltage control supplies (of the order of 10 volts).

BACKGROUND ART

Means for isolation between main supply and control circuit supplies are known. One of the earliest forms involves the use of an electromechanical relay. In the relay the coil is arranged to operate on either the high or the low voltage and the contacts operated by the relay coil are arranged to operate on the corresponding low or high voltage.

In some applications the isolation provided by an electromechanical relay may be sufficient. However, the relay does suffer from a number of drawbacks. These include:

The relay is susceptible to vibration;

The relay characteristics can vary with temperature and age;

The relay is susceptible to electrical leakage particularly in the smaller sizes and where the humidity or moisture level is relatively high;

Under severe or cyclic vibration conditions arcing can occur across the relay contacts resulting in welding closed of the contacts (ie failure in the ON position).

The relay can be relatively bulky for the electrical isolation it affords.

An advantage of the relay is that it is relatively insensitive to electrical noise.

It is an object of the present invention to provide an electrical isolation device which overcomes one or more of the stated disadvantages of the known prior art whilst still retaining the advantages thereof.

One non-limiting application of the isolation device of the present invention is in amusement equipment, for example fairground games, video games and arcade games. This form of equipment typically requires coin operation. In the past relay operated devices have formed part of the coin operation mechanism. As enumerated above these relay devices suffer from certain disadvantages. Instances have been known in recent times where these devices have failed in such a way that electrocution of users of the device has resulted. There is therefore clearly a need for an isolation device which is simple, inexpensive, compact and preferably provides improved performance over the previously used relay based coin operation mechanisms, such device also providing the required electrical isolation under all necessary conditions and being capable of approval by the relevant safety and electrical authorities.

DISCLOSURE OF INVENTION

In one broad form there is provided an electrical isolation assembly comprising a circuit board, an isolator device having high electrical isolation between high and low voltage terminals, sai d isolator device having a plurality of low voltage connecting pins located along a first edge and a plurality of high voltage connecting pins located along a second edge parallel to and opposite said first edge of said isolator device, certain ones of said high and low voltage connecting pins connected in an electrically conductive manner to electrically conductive tracks located on a surface of said circuit board and an elongate slot cut in said board; said isolator device located on said board so that said high and low voltage connecting pins are located on respective opposite elongate sides of said elongate slot; and wherein the minimum creep distance between respective ones of said high and low voltage connecting terminals is at least 8.0mm; and wherein the minimum distance between respective ones of said high and low voltage connecting terminals is at least 10.7mm.

Preferably the minimum creep distance is at least 8.2mm.

In a further broad form there is provided an electrical isolation assembly comprising a circuit board and at least one opto-isolator integrated circuit package having high electrical isolation between high and low voltage terminals thereon, said opt-isolator package having a plurality of low voltage connecting pins along a first surface and a plurality of high voltage connecting pins along a second surface; said opto-isolation package mounted on said circuit board so that said high and low voltage connecting pins are located on respective opposite elongate sides of an elongate slot cut in said board; the minimum width across said slot being at least 2.7mm, said slot being at least 16mm in length when located symmetrically beneath a standard IC DIP package.

Preferably the minimum width across said slot is 4mm. Preferably the said slot is at least 16mm in length when located symmetrically beneath an MOC 3021 IC DIP package or other opto-isolator package of equal dimension.

In a further form, the above electrical isolation assembly includes additional opto-isolator integrated circuit packages lying in line with said package, the longitudinal separation between ends of said packages being at least 8mm, said additional packages otherwise installed in the same manner as the above package.

In another form, the electrical isolation assembly includes additional packages lying in adjacent rows beside said package, said additional packages in said adjacent rows being separated from said package by an additional longitudinal slot cut in said board, said additional slot being at least 2.7mm in width, said additional packages otherwise being installed in the same manner as the package above described.

Preferably said additional slot is at least 4mm wide. Preferably each said package or additional package is approximately 8mm long and approximately 6mm wide, with connecting pins lying along the longer sides.

Preferably said longitudinal slot beneath said package extends at least 4mm beyond both ends of said package.

Preferably the maximum voltage applied to the circuit on said board is in the range 120 volts (RMS) to 420 volts (RMS) at a frequency generally in the range 45 Hz to 65 Hz and more preferably in the range 50 Hz to 60 Hz.

In a further form, there is disclosed a circuit comprising opto isolation means having high and low voltage connecting pins, said opto isolation means having conduction disable means operable during a predetermined period of time connected between a first one of said low voltage connecting pins, said opto isolation means having logical power supply means connected to a second one of said low voltage connecting pins, said logical power supply means arranged to supply power for a predetermined period of time to said second one of said low voltage connecting pins.

Preferably said predetermined period of time relating to said disable means is greater than said predetermined period of time relating to said logic power supply means.

BRIEF DESCRIPTION OF THE DRAWINGS

One embodiment of the present invention will now be described with reference to the drawings in which:

Fig. 1 is a schematic diagram of a solid state electrical isolation device according to a preferred embodiment;

Fig. 2 is a plan view of the underside of part of the circuit board incorporating the preferred embodiment; and

Fig. 3 is a timing diagram illustrating the operation of the preferred embodiment.

Fig. 4 is a plan view of the top of a circuit board incorporating a plurality of isolator chips, laid out in accordance with a preferred embodiment of the present invention.

MODES OF CARRYING OUT THE INVENTION

Referring initially to the schematic diagram of Fig. 1 there is shown two 555 timers IC1 and IC2 controlling an opto-isolator circuit IC3. - The high voltage side of the optocoupler .forms part of the 240 volt AC circuit which is suitable to operate an electric motor or equivalent by means of TRIAC TC1.

The low voltage circuit performs two functions:

1. By means of IC 2 there is a predetermined delay after power up of the control circuit before the opto-isolator circuit IC3 is enabled.

2. IC1 provides an enable signal to the IC3 for a predetermined time after the coin operation switch is operated by a coin.

In the present situtation the component values and connections are arranged so that IC1 provides a predetermined ON time of approximately 60 seconds and IC2 provides an initial disable signal of approximately 70 seconds after power up.

The circuit of Fig. 1 is arranged so that the whole assembly is supplied with mains power at 240 volts AC. A step down transformer T1 by means of suitable regulation circuitry provides 12 volt DC regulated input for the low voltage control circuit. The same 240 volt AC supply is also connected by means of the TRIAC TC1 to a motor load or equivalent.

One of the problems of using a solid state drive arrangement is that upon initial power up the TRIAC TC1 may turn on for a very short period of time. In certain applications, including the coin operated amusement devices to which reference was previously made, it i s desirable if not imperative that this does not occur. The circuit of Fig. 1 incorporates means to prevent this happening. In particular, IC2 is arranged so that, upon turn on, PIN3 is high. Approximately 70 seconds later IC2 times out and PIN3 goes low. At this stage, if PIN3 of IC1 were to go high then a supply becomes available to PIN1 of IC3 which then connects via PIN2 of IC3 through diode Dl and via PIN3 of IC2 to common. PIN 3 of ICl goes high when the coin switch is operated (by insertion of a coin in the machine). Upon insertion of a coin PIN3 goes high for a period of approximately 60 seconds i.e. for the intended predetermined period of operation of the machine.

Upon power being applied at terminal 1 of IC3 and the conduction path to common existing from terminal 2 of IC3 then TRIAC TCI is gated on by means of conduction through terminals 6 and 4 of IC3.

Referring to Fig. 3, typical timing wave forms for the circuit of Fig. 1 are shown. IC2 operates much more quickly than IC3. i.e. The rise time of the signal at terminal 3 of IC2 is much faster than the rise time of the output signal at terminal 4 of IC3. By-virtue. of this timing relationship, upon initial power up, IC2 will always inhibit IC3 (high on terminal 3 of IC2) before IC3 can gate TRIAC TC1 on).

Further, should any electrical noise in the environment of the controller be sufficient to activate IC1 then it can be expected to be sufficient to activate IC2 as well. The result will be that with the circuit in a ready state (i.e. 240 volts applied and IC2 timed out) should noise trigger ICl rather than a coin operation then IC2 will also be triggered resulting in an inhibit of IC3 for a period of time greater than the ON time of IC1. By this arrangement the circuit fails to the off state in the event of noise causing operation of the circuit.

In normal operation of course the sequence of events will be:

1. Apply 240 volt power to circuit.

2. Upon time out of IC2, terminal 3 of IC2 goes low, allowing IC3 to be enabled.

3. Upon insertion of a coin ICl will turn ON for a predetermined period, thereby activating IC3 which gates TCI ON.

Whilst desired operational characteristics have been incorporated in the above circuit an important requirement, namely electrical isolation, also needs to be addressed. Opto-isolator circuit IC3 provides nominal 7.5kV isolation between its high and low voltage sides. To ensure this isolation is maintained once the integrated circuit is actually placed onto a circuit board, certain circuit board design constraints must be considered.

With reference to Fig. 2 the integrated circuit placement and track layout therein disclosed has been found advantageous in maintaining the necessary electrical isolation even under conditions of high humidity and condensation on the board. Generally the parameters adopted are greater in magnitude than those usually specified. Further, it has been found necessary to use a combination of measures to achieve the required isolation under specified conditions.

In Fig. 2, the underside of the circuit board holding the circuit of Fig. 1 is shown in part. IC3 has been located near an edge of the board with the high and low voltage pin pads stradling a slot of length 1 and width wl cut out of the board. Pins 1, 2, 4 and 6 of IC3 are shown connected to solder pads. In the preferred embodiment dimension 1 is 16mm and wl is at least 2.7mm, preferably 3mm and more preferably 4mm. The distance w2 between the high and low voltage pins of IC3 is at least 10.7mm. Also, by virtue of the cut out, the creep distance, being the minimum distance between any high and low voltage pad is at least 8mm and preferably 8.2mm. In a further preferred form the slot width wl is extended to be equal to w2. Tests on a circuit board prototype built using the dimensions and the circuit of the preferred embodiment disclosed above have exhibited an isolation of at least 7kV under required conditions of humidity and temperature.

The slot should be located symmetrically beneath the opto-isolator chip as generally shown in Fig. 2.

It has also been found necessary to maintain separation of at least 5mm between the 555 timers ICl and IC2 on the board. In the prototype built according to the preferred embodiment TRIAC TCI is rated at 15 amps, 400 volts with gate turn on current of 50mA (SC151D). The opto-isolated TRIAC driver, IC3, is an M0C3021 TRIAC driver chip rated 7.5kV isolation.

The dimension of MOC3021 is approximately 8mm in length by 6mm in width by approximately 3mm in thickness (exluding pins). In general terms it is required that the slot extend 4mm beyond either end of the IC package. For this particular chip the slot length, when located symmetrically beneath the chip, is therefore 4mm plus 8mm plus 4mm equals 16mm.

Many opto-isolator chips are of similar dimension to MOC3021 DIL chips. However for DIL isolator chips in general the slot should extend 4mm beyond either end of the IC package.

Referring to Fig. 4, where more than one isolator chip is to be used on one board then where the chips are to be placed in line as, for example, chips 10, 11 and 12, the slot 13 should extend continuously with the chips all stradling the slot. The minimum separation distance between chip ends is 8mm. The slot width should be as previously specified, namely at least 2.7mm and most preferably 4mm or greater.

If additional chips are placed in rows, also as shown in Fig. 4, then they should also stradle a slot 14 as shown. In addition a separation slot 15 should be included which separates the rows of integrated circuit chips from each other, i.e. separates chips 10, 11 and 12 from chips 16, 17 and 18.

The above dimensions and isolation characteristics apply particularly for situations where the maximum voltage likely to be applied to the isolation device lies in the range 120 volts (RMS) to 420 volts (RMS) and being within the frequency range approximately 45 Hz to 65 Hz.

In the preferred embodiment the isolator chip is a 6 pin DIL package located on a fibreglass circuit board of thickness in the range 0.3mm - 1mm and being sealed with an epoxy resin based sealant.

A formula for the width Wl of the slot (air gap) beneath the chip

where Wl is slot width in mm

V is maximum RMS volts applied to the high voltage device activated by the isolator chip

F is frequency of V in cycles per second.

Typical widths resulting from the use of this formula are:

V (Volts) F (Hz) Wl (mm)

120 50 3.24552

120 60 3.32

240 50 3.7499

240 60 3.82

420 50 4.250

420 60 4.31402 The foregoing describes only one embodiment of the present invention and modifications, obvious to those skilled in the art, can be made thereto without departing from the scope and spirit of the present invention.

For example, the isolation circuit of the present invention clearly has application in any environment which requires use of integrated circuit devices having high resistance to noise, high electrical isolation between high and low voltage circuits, and arranged to fail in the OFF condition.

The embodiments of the present invention can also be used to drive flood lamps, three phase motors and various household appliances (particularly where maximum current requirement is less than 16 amps at 240 volts AC).

The preferred embodiment is also suitable for encapsulation.

Where a three phase system is required the circuit of the present embodiment can be adapted and repeated threefold.

Whilst a particular opto-isolator chip has been described in the present application the principle of the present invention is applicable to opto-isolator and other voltage isolation type chips of varying package dimension and package shape. The slot beneath the chip should, in all cases, extend at least 4mm beyond the ends of the chip.

The manufacturer's data sheets for the MOC 6xxA, MOC 3021 and similar isolator chips (Motorola) are incorporated herein by cross-reference, particularly those portions which relate to isolation precautions for such devices.

Claims

CLAIMSELECTRICAL ISOLATION DEVICE

1. An -electrical isolation assembly comprising a circuit board, an isolator device having high electrical isolation between high and low voltage terminals, said isolator device having a plurality of low voltage connecting pins located along a first edge and a plurality of high voltage connecting pins located along a second edge parallel to and opposite said first edge of said isolator device, certain ones of said high and low voltage connecting pins connected in an electrically conductive manner to electrically conductive tracks located on a surface of said circuit board and an elongate slot cut in said board; said isolator device located on said board so that said high and low voltage connecting pins are located on respective opposite elongate sides of said elongate slot; and wherein the minimum creep distance between respective ones of said high and low voltage connecting terminals is at least 8.0mm; and wherein the minimum distance between respective ones of said high and low voltage connecting terminals is at' least 10.7mm.

2. The electrical isolation assembly of claim 1 wherein said minimum creep distance is at least 8.2mm.

3. An electrical isolation assembly comprising a circuit board and at least one opto-isolator integrated circuit package having high electrical isolation between high and low voltage terminals thereon, said opt-isolator package having a plurality of low voltage connecting pins along a first surface and a plurality of high voltage connecting pins along a second surface; said opto-i solation package mounted on said circuit board so that said high and low voltage connecting pins are located on respective opposite elongate sides of an elongate slot cut in said board; the minimum width across said slot being at least 2.7mm, said slot being at least 16mm in length when located symmetrically beneath a standard IC DIP package.

4. The electrical isolation assembly of claim 3 wherein said minimum width across said slot is 4mm.

5. The electrical isolation assembly of claim 3 or 4 wherein said slot is at least 16mm in length when located symmetrically beneath an MOC 3021 IC DIP package or other opto-isolator package of equal dimension.

6. The electrical isolation assembly of any one of claims 3 to 5 further including additional opto-isolator integrated circuit packages l yi ng in line with said package, the longitudinal separation between ends of said packages being at least 8mm, said additional packages otherwise installed in the same manner as the package of any one of claims 3 to 5.

7. An electrical isolation assembly according to any one of claims 3 to 6 wherein additional packages lie in adjacent rows beside said package, said additional packages in said adjacent rows being separated from said package by an additional longitudinal slot cut in said board, said additional slot being at least 2.7mm in width, said additional packages otherwise being installed in the same manner as the package of any one of claims 3 to 6.

8. An electrical isolation assembly as claimed in claim 7 wherein said additional slot is at least 4mm wide.

9. An electrical isolation assembly according to any previous claim wherein each said package or additional package is approximately 8mm long and approximately 6mm wide, with connecting pins lying along the Longer sides.

10. The electrical isolation assembly of any previous clafm wherein said longitudinal slot beneath said package extends at least 4mm beyond both ends of said package.

11. An electrical isolation assembly according to any previous claim wherein the maximum voltage applied to the circuit on said board is in the range 120 V (RMS) to 420 V (RMS) at a frequency generally in the range 45 Hz to 65 Hz.

12. A circuit comprising opto isolation means having high and low voltage connecting pins, said opto isolation means having conduction disable means operable during a predetermined period of time connected between a first one of said low voltage connecting pins, said opto isolation means having logical power supply means connected to a second one of said low voltage connecting pins, said logical power supply means arranged to supply power for a predetermined period of time to said second one of said low voltage connecting pins.

13. The circuit of claim 12 wherein said predetermined period of time relating to said disable means is greater than said predetermined period of time relating to said logic power supply means.

14. An electrical isolation assembly as claimed in claim 1 or claim 3 and as hereinbefore particularly described with reference to Fig. 2.

15. An electrical isolation assembly as claimed in claim 3 and as hereinbefore particularly described with reference to Fig. 4.

16. A circuit according to claim 12 and as hereinbefore particularly described with reference to Figs. 1 and 3.