WO1986001017A1

WO1986001017A1 - The multi input fast adder

Info

Publication number: WO1986001017A1
Application number: PCT/LK1985/000001
Authority: WO
Inventors: Arya Keerthi Kumarasena
Original assignee: Arya Keerthi Kumarasena
Priority date: 1984-07-30
Filing date: 1985-07-01
Publication date: 1986-02-13
Also published as: AU4490185A; EP0188458A1

Abstract

A multi input arithmatic logic unit by combination of breaking down the inputs into several stages of bitwise processing followed by shifting of outputs according to the power of bits. This process may also be repeated or serially combined, combined with carry look ahead stages or used for producing modular units by introducing carry-in and carry outs. This may also be incorporated to process negative numbers, produce logical functions, multipliers, dividers, mathematical functions, control units, etc.

Description

THE MULTI INPUT FAST ADDER Introduction

This invention is related to the speed ing up of arithmetic logic units of computers and micro computers. It leads to manufacturing of integrated circuits for real time and fast digital processing , and control applications.

Addition of more than two numbers cannot be done by a human being except using the cumulative law, where one adds two numbers at first, and add the third number to the result and so on. This technique has been adopted in computer technology and therefore has inherent limitations. Addition of several numbers must be done using the above technique. As one number consists of several digits,additon has to be started from lowest bit and a carry has to be passed to higher bits. Carry look-ahead technique is used to speed up this operation. It is described in detail in reference (1).

However there is no existing method to carry out a faster addition with more than two numbers at a t i me . A lth ough a boolean expression can be used for one bit addition, the problem of carry propagation results in a significant delay. To reduce the time of adding several var iables,more arithmetic logic units can be used in parallel , reducing the number of steps to a logarithmic figure. But this i s an expensive solution. Multiplication which is done as a series of additions also suffers from this technological Iimitation. If one coefficient is fixed, this can be speeded up by using read only memories,which depends on known coefficients, in digital filters this technique is being applied to speed up operation. However this requires a customer designed filter for each application, which is described in reference(2).

In large computers fast multipliers are used with special design for a specific configuration.Boolean expression for full processing are extremely expensive. Due to irregularities of these expressions,a microprocessor has not been built with this facility, up to now.

Invention

This invention enables the faster arithmetic operations by incorporating more than two additions at a time. Several inputs of several bits can be added in a single unit. Addition of the same level bits of several variables are done by programmable logic array units, which produce certain number of out put bits of different powers. Each of these out put bits are considered as input to the next stage. Shifting of higher power bits to appropriate position is required. After shifting these bits of same power are added again, using programmable logic array units. Stage to stage , number of outputs per stage decreases. At the last stage there are only two outputs corresponding to each bit position, which can be treated as the addition of two numbers consisting of several bits, which is the normal application in present day technology. Incorporating carry look ahead technique at this stage will lead to faster speeds . However one can use these two inputs, with normal carry propagation procedures, depending on the requirement. Several bits of several inputs can be grouped into , blocks of bits of all the inputs, to produce modular units. Each block will have certain number of intermediate carry bits in addition to the normal carry.

Numbers are represented in 2's complement form, and can be positive or negative. To remove overflow, a sufficient number of additional sign bits are introduced , before processing. In hardware implementation this is quite simple as , only the sign bit is fed in parallel to the required number of positions. This operation can be considered as a mere division, to guarantee that the result is within the limits of 2's complement representation (1 > result >= -1 ). The technique is valid for integer representation of numbers as well as for normalized representation of numbers.

Given below is one embodiment of carrying out above invention, and is in the form of explanation only, and not limiting in scope.

Figure (1) shows the general block diagram of this application

Figure (2) shows the 5 inputs of each digit and its three out puts from PLA corresponding to the equations given below.

These three outputs are shifted according to their values and added using another PLA to obtain two out puts. Figure (3) shows the implementation of this PLA in detail . (2 nd stage of addition requires 3 carriers from previous stage modular unit, and similarly first stage of addition generates these carriers for the next stage )

Equations governing the 2nd stage are

Yi,o = X (i,o) X (i-1,1) X (i-2,2) + X (i,o) X'(i-1,1) X' (i-2,2)

X'(i,o) X (i-1,1) X'(i-2,2) + X'-(i ,o) X'(i-1,1) X (i-2,2)

Yi,1 = X (i ,o) X (i-1,1) + X (i ,o) X (i-2,2) + X (i-1,1) X(i-2,2)

The outputs obtained from the second addition are shifted again according to their positions which reduces the problem to a two input case. Third PLA (as shown in Figure (4) is used to produce Generators and Propagators required for carry look ahead process ing. Equations governing this PLA are given below.

Si = Y(i,o) + Y(i-1,1) + Ci

Pi = Y(i,o) + Y(i-1,1)

Gi = Y(i ,o) Y(i-1,1) These generators (Gi) , propagators (Pi) and carry in (Ci) are combined in the carry look ahead unit to produce carries C1,C2,C3,Cout, block generator (Gb) and block propagator (Pb).These block outputs can be used for further stages of carry look ahead processing.

Figure (5) explains the PLA implementation of this carry look ahead unit.

Cl =Go + Po Co C2 =G1 + P1 Go + P1 Po Co C3 =G2 + P2 G1 + P2 P1 Po Co Cout =G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 Go + P3 P2 P1 Po Co Pb =P3 P2 P1 Po Gb =G3 + P3 G2 + P3 P2 G1 P3 P2 P1 Go + P3 P2 P1 Po Co

When negative number manipulation is required , same technique can be used .Principle of operation is similar with additional sign bits introduced to inputs . However the result has only one sign bit , and the speed of operation has increased by a order of magnitude.

delays associated with few types of ALUs are shown below

4bits 16bit, 64bits 256bits

1. Two numbers only 9 13 17 with carry look ahead

2.Five numbers (4 additions) 20 36 52 68

3.Five numbers (3 stages) 15 27 33 51 Parallel addition used

4. Five numbers 9 13 17 21 Proposed method

All delays are given in basic gate delays.

Still higher improvement can be obtained in adding more numbers at once.

Carrying out of the invention

As mentioned before this invention can be carried out in several ways, depending on the application. Five input four bit standard configuration can be produced as a MSL I/C. This will have 20 inputs, 5 carry ins and 5 carry outs (including 3 first stage car r i es , 1 second stage carry and the normal carry),block generator and block propagator out puts for further stages of car ry look ahead processing , and four out put bits. After considering clocks and power connections it can be concluded that this configuration can fit into a 40 pin package. This will have many applications in real time processing. In microprocessors this can be used as a building block of the ALU Configuration can be changed from 4 bits to any number requi red.number of parallel inputs also can be changed to a convenient number.

Main frames can use the same technique to produce fast multipliers and adders to speed up operation.

Advantages (i) The system suggested enables the design of a modular unit , possibly a chip , which can be used for fast addition and thereby improve the capabilities of digital filters by allowing a smaller sampling time during two successive samplings of a real time processing system. This opens a new avenue for filters which require a higher frequency response . Certain present requirements , which cannot be carried out due to a technological limitation of processing speed become possible. (ii) The system suggested can be incorporated in fast multipliers in main frames as well as in microprocessors , as a functional unit . Flexibility of having different stages makes the component cheaper and allows for more design variations. (iii) The system suggested requires only , very elementary programmable logic array units and standard carry look ahead units , enabling the design to be more regular and therefore accurate and , very fast design at chip level. (iv ) The method suggested does not have any technological I i mi tat ion and is available for production in a v e r y short time. ( v ) The method suggested can change the concept of normal computing , as new instructions of multiple additions can be incorporated at micro instruction level . This will speed up the overall performance of computers. (vi ) This has a special application in cascade digital filters , where all figures require addition of only five numbers . Present technology of fixed coefficients and associated ROMs can be changed to that of programmable digital filters. This will reduce digital filter cost by an order of magnitude as customer built ROMs can be completely eliminated.

Industrial applications

(a) Production of a fast operation chip

A Radar moving target indicator (MTI) is atypical example for this application. The MTI filter has to process its data within the pulse repetetion interval and provide the processed information for displaying purposes. The same information is required for antenna controlling in tracking radars. Therefore filter complexity is basically limited by the processing time. Any improvement in processing time enables the use of better filters and hence is quite useful as an aviation aid. Applications can be extended to controls and military uses. (b) At present digital filters in various applications require different ROMs depending on the filter coefficients. This chip will reduce the cost of these filters as customerized production is completely eliminated. One filter may replace a group of filters depending on the applications reducing customer costs further. TypicaI example is a communication channeI which uses several frequencies, depending on time of operation, sun spots and atmospheric conditions. As one programmable filter can accommodate all these filtering facilities, a number of filters is no more required. (c) Present compiler structure has only the addition instruction for adding two numbers. Software has to reduce any arithmetic statement into a set of machine instructions of adding two numbers at a time. With this type of processor this may become simpler.lt improves throughput and system software development facilities simultaneously. This will have special application in statistical and weather data processing computers, as very large number of repetetive additions are to be carried out. (d) At present multiplication is done mainly by, using addition in stages. This technique reduces multiplication time by an order of magnitude. Fast division algorithems which require fast multipliers are not used in microprocessor level at present. This technique solves this technology problem , and hence faster divisions become possible at this level. (e)Extension of above techniques can be used for any mathematical function generation and multiple nput compar isons using logical functions. Both functions have tremendous applications in electronic and control fields. (OImplementation of the technique can be extended to software, where hard ware shifting of outputs can be simulated using software shifting. This will have a wide application in multi processor environment, when array processing and pipelining principles are used for faster operations,

Given above is one variation, and the description is with an one embodiment in the way of an example only, and not limiting scope.Other embodiments and variations, yet within the concept is possible and is covered in this application.

Reference (1): FUNDAMENTALS HAND BOOK OF ELECTRICAL AND COMPUTER

ENGINEERING III -

Sheldon S.L. Chang, Editor - in - Chief pages 47 - 49

Reference (2): DIGITAL FILTERS ANALYSIS AND DESIGN -

Andreas Antoniou pages 426 - 431

Claims

1. A multi input Arithmetic Logic Unit (ALU) by combination of breaking down the inputs into several stages of bitwise processing (one or more bit positions can consist of a single block in this breaking down procedure ) followed by shifting of outputs according to the power of bits.

2. An Arithmetic Logic unit where the process as claimed in claim one is applied repeatedly (that is process is repeated or the two or more stages of processes as in claim one are serially combined).

3. Process consisting of, Combination of one or more of above claimed processes with one or more of carry look ahead stages.

4. Process consisting of, breaking down of the bit chain of, one or more of the processes, as claimed in claims one to three above, to produce modular units , by introducing one or more of carry ins and carry outs.

5 Process which incorporates one or more of above c laims one to four to process negative numbers.

6. Process which incorporates one or more of above claims one to five to produce logical functions.

7. process which incorporates one or more of above claims one to six to produce multipliers.

3. process which incorporates one or more of above claims one to seven, to produce dividers,

9. process which incorporates one or more of above claims one to eight, to produce any other mathematical function.

10. process which incorporates one or more of above claims one to nine, to produce control units,

11. process which incorporates one or more of above claims one to ten, to produce digital filters.

12. Software techniques which use one or more of above claims one to eleven.

13. Techniques substantially similar to the usage given in above claims one to twelve, or as described in the description.