WO1985000460A1

WO1985000460A1 - A byte wide memory circuit having a column redundancy circuit

Info

Publication number: WO1985000460A1
Application number: PCT/US1984/000757
Authority: WO
Inventors: Elvan S. Young; Steven J. Schumann
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1983-07-14
Filing date: 1984-05-17
Publication date: 1985-01-31
Also published as: EP0150194A4; JPS60501878A; EP0150194A1

Abstract

A 4-bit byte wide memory circuit (12) having a column redundancy scheme including a plurality of bit segments (BS), each having columns (18, 20), for storing data, a plurality of data lines (DL), corresponding, respectively, to the plurality of bit segments (BS), a plurality of I/O ports (PM) coupled, respectively, to the plurality of data lines (DL), a plurality of redundant columns (RC) for storing data and corresponding, respectively, to the plurality of I/O ports (PM), and a programmable circuit (28) for coupling, respectively, the plurality of redundant columns (RC) to one or another of the data lines (DL) while decoupling the bit segments (BS) from the data lines (DL).

Description

A BYTE WIDE MEMORY CIRCUIT HAVING A COLUMN REDUNDANCY CIRCUIT

Background of the Invention Field of the Invention The present invention relates generally to apparatus for accessing data and, more particularly, to a byte wide memory circuit having a column redundancy circuit or scheme.

Discussion of Background and Prior Art A wide variety of apparatus exists for storing and accessing data. One type of apparatus is a memory circuit, such as a byte wide memory circuit having a column redundancy scheme. The memory circuit includes a main memory array for storing the data and circuitry for accessing the stored data. The main memory array, for example, a static random access memory (SRAM), generally includes a number of bit segments, each having a plurality of addressable columns for storing the data. The circuitry used to access the data stored

OMPI in the main memory array includes, for each bit segment, a column address decoder which receives and decodes column addresses to activate the corresponding columns. The memory circuit can be manufactured, for example, as an integrated circuit (IC) on a semiconductor chip.

In the manufacture of the memory circuit, one or more defects can occur which cause one or more columns in the bit segments to be unusable for storing the data. For example, one defect can constitute two columns in a bit segment being shorted together, thereby making both columns defective. Consequently, the memory circuit typically is manufactured with redundant columns which can be used to replace defective columns, together with programmable redundant column address decoders which are programmed to decode addresses to the defective columns. Thus, when a given address to a defective column in a bit segment is generated, the redundant column address decoder programmed with that address responds by activating the corresponding redundant column to replace the defective column.

One particular byte wide memory circuit having a column redundancy scheme is known as a four-bit byte wide memory circuit. The architecture of this memory circuit includes four bit segments, four input/output (I/O) ports and four data lines which couple the bit segments to the I/O ports, respectively. This memory circuit has symmetrical left and right half planes, with each half plane including two bit segments, two data lines and two I/O ports. Each half plane also has four redundant columns arranged in two pairs of

OMPI redundant columns to replace defective columns in the two bit segments, thereby providing a ratio of four redundant columns per two I/O ports. Two redundant columns of one pair are coupled, respectively, to the two data lines and two redundant columns of the other pair are also coupled, respectively, to the two data lines. The two redundant columns of a pair are activated as a pair when addressing a defective column in a bit segment.

In particular, with the above-mentioned architecture, for each half plane the two pairs of redundant columns are used to replace different combinations of defective columns in the bit segments. For example, if two columns in one bit segment coupled to one data line are shorted together, then one pair of redundant columns is activated when one of these defective columns is addressed and the other pair of redundant columns is activated when the other defective column is addressed. That is, the one redundant column of one pair connected to the one data line and the one redundant column of the other pair connected to the one data line are used to replace, respectively, the shorted columns in the one bit segment.

As another example of a manufacturing defect, assume that one distinctly defective column exists in one bit segment coupled to one data line and another distinctly defective column exists in the other bit segment coupled to the other data line. Then again one pair of redundant columns is activated when one of these defective columns is addressed and the other pair of redundant columns is activated when the other defective column is addressed. The one redundant column in the one pair coupled to the one data line and the one redundant column in the other pair coupled to the other data line are used to replace the two distinctly defective columns in the respective bit segments.

One disadvantage with the architecture of the above-mentioned byte wide memory circuit is that, for each symmetrical half plane, four redundant columns per two I/O ports are utilized. Specifically, there are two pairs of redundant columns that are provided to replace two defective columns. This ratio of redundant columns to I/O ports is inefficient in that four redundant columns are provided to replace two defective columns.

Another disadvantage or inefficiency is that if, for example, and as another manufacturing defect, only one column in the two bit segments of a given half plane is distinctly defective, then still two pairs or four redundant columns are provided, with only one redundant column actually being used for the replacement of the one defective column. Other disadvantages include the increased manufacturing costs and complexity that are associated with requiring these numbers of redundant columns relative to the numbers of I/O ports, and the additional space that is needed on the semiconductor chip to provide these redundant columns.

Summary of the Invention

It is an object of the' present invention to provide a novel apparatus for accessing data. It is another object of the present

OMPI invention to provide a byte wide memory circuit having a more efficient column redundancy scheme.

Yet another object of the present invention is to simplify, and reduce the costs of, manufacturing a byte wide memory circuit having a column redundancy scheme.

Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be- learned of by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.

Statement of the Invention

To achieve the foregoing and other objects in accordance with the purposes of the present invention, as embodied and broadly described herein, the apparatus of the invention can comprise a plurality of memory means for storing data, a plurality of data lines corresponding, respectively, to the plurality of memory means, a plurality of port means coupled, respectively, to the plurality of data lines, a plurality of redundant means for storing data and corresponding, respectively, to the plurality of port means, and means for coupling, respectively, the plurality of redundant means to one or another of the plurality of data lines while decoupling one or another of the plurality of memory means from one or another of the plurality of data lines. Preferably, each of the redundant means is a redundant column and the means for coupling and decoupling is programmable to couple or switch a given redundant column to one or the other data line. Thus, a given redundant column can be coupled or switched to the one or another data line by programming the programmable coupling and decoupling means.

The programmable coupling and decoupling means includes, for a given redundant column, a programmable address decoder that is programmed to decode an address to a defective column, a pair of pass gates for coupling the given redundant column to one and the other data lines, respectively, and a programmable multiplexer which is programmed to select and switch a gate enabling signal produced by the programmed address decoder to one of these two pass gates, thereby, for example, gating data stored in the redundant column onto one of the data lines. Simultaneously, the programmed coupling and decoupling means effectively decouples the bit segment having the defective column replaced by the given redundant column from the corresponding data line.

Statement of Derived Benefits and Advantages

With the present invention, in which a given redundant column can be coupled or switched to one of two data lines, only one redundant column per I/O port is needed for replacing the same defective columns as with prior column redundancy schemes. Furthermore, as a result of this flexibility in the coupling of a given redundant column to one or the other data line, the present invention also provides only two redundant columns, with only one of these redundant columns being necessary to replace a distinctly defective column. Also, by being able to couple two redundant columns of the present invention to the same one of two data lines and, hence, a corresponding I/O port, the column redundancy scheme of the present invention advantageously effectuates a two redundant column per I/O data transfer for byte wide memory circuits. Consequently, more efficient redundant column usage and reduced costs and simplicity of manufacturing are achieved with the present invention, while providing the ability to replace the same defective columns as prior column redundancy schemes.

Brief Description of the Drawings

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings:

Fig. 1 is a simplified block diagram of the present invention; Fig. 2 is a more detailed block diagram of the present invention; and

Fig. 3 is a partial schematic illustration of the present invention.

Detailed Description of the Invention Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings.

Fig. 1 illustrates an apparatus 10 for accessing data and, in particular, a byte wide memory circuit 12. As one example, and as will become appreciated below, the byte wide memory circuit 12 can be a 4-bit byte wide memory circuit, although the principles of the present invention can be applied to other types of byte wide memory circuits. And, while implemented as an integrated circuit (IC), the memory circuit 12 can constitute other types of circuit implementation..

The memory circuit 12 has a left-hand portion or plane 12A, shown in detail, and a symmetrical or similar right-hand portion or plane 12B shown only generally in one block. The discussion of left-hand plane 12A will be sufficient for an understanding of the right-hand plane 12B and the overall principles of the present invention. The memory circuit plane 12A has a main memory array 14A divided into a plurality of memory means shown generally at 16A for storing data. In particular, memory means IβA includes a bit segment BS, having a plurality of addressable data storage columns shown generally at 18 and an address decoder AD, for decoding column addresses to access the respective columns 18. Memory means 16A includes another bit segment BS₂ which has a plurality of addressable data storage columns shown generally at 20 and an address decoder AD_ for decoding column addresses to access the respective columns 20. Address decoder AD' and address decoder AD_ receive the addresses to the columns 18 and columns 20 over control lines shown generally at 22. As one example, bit segment BS, can have 32 columns 18 and bit segment BS r, can have 32 columns 20 , whereby address decoder AD, and address decoder AD- will decode 5-bit addresses on lines 22. A plurality of data lines of memory circuit plane 12A, shown generally at DL, is coupled to the plurality of memory means 16A, respectively, to conduct or transfer the data that can be stored in memory means 16A. In particular, the data lines DL include a data line DL, that is coupled to the bit segment BS, and a data line DL₂ that is coupled to the bit segment BS„. The memory circuit plane 12A also includes a plurality of port means shown generally at PM, which is coupled to the plurality of data lines DL, respectively.

Specifically, the port means PM includes a port means PM, that is coupled to the data line DL, and a port means PM„ that is coupled to the data line DL₂. In the overall operation of the memory circuit plane 12A thus far described, to access data, a given column address is supplied on lines 22 and received by address decoder AD, and address decoder AD₂. This column address is then decoded by address decoder AD, and address decoder AD-, wnereby one of the columns 18 and one of the columns 20, respectively, is accessed. Then, a data transfer can be made between the port means PM, and the one addressed column 18 over the data line DL, , and between the port means PM₂ and the one addressed column 20 over the data line DL-. For example, if data are to be read from one of the columns 18, then an address to that one column is supplied over the lines 22 and decoded by the address decoder AD,. In response, the given addressed column 18 is accessed by the output of the address decoder AD,, whereby the data stored in the addressed column 18 are transferred over data line DL, to the port means PM,.

A number of defects can occur during the course of manufacturing the bit segment BS, and the bit segment BS„ that can cause one or more of the columns 18 and columns 20 to be unusable for data storage purposes. For example, as indicated in Fig, 1, a column 18, and a column 13- -in bit segment BS, can be shorted, thereby making both of these columns defective for storing data, or a column 20, and a column 20_ in bit segment BS- can be shorted, thereby making these two columns defective for storing data. Another manufacturing defect can have two separate columns being unusable, such as a column 18.. in bit segment BS, and a column 20-. in bit segment BS_ being distinctly defective. Yet another manufacturing defect may result in only one column, for example, column 18., being defective throughout the entire main memory array 14A. The present invention will be described below on the assumption that the overall main memory array 14A is manufactured with any one of these four defective column conditions. Memory circuit plane 12A has a plurality of redundant means shown generally at 26A for replacing one or more defective columns 18 in bit segment BS, and/or one or more defective columns 20 in bit segment BS₂« In particular, redundant means 26A has a plurality of redundant columns shown generally at RC corresponding in number, respectively, to the plurality of port means PM.

f OMPI The plurality of redundant columns RC includes a redundant column RC, for replacing a defective column 18 in bit segment BS. or a defective column 20 in bit segment BS- and a redundant column RC₂ for replacing a defective column 18 in bit segment BS, or a defective column 20 in bit segment BS₂» These two redundant columns RC, and RC₂ correspond in number to the number of port means PM, i.e., to the port means PM, and port means PM-. In other words, the architecture of the memory circuit plane 12A is such that there is a like number, of bit segments BS, and BS-, data lines DL, and DL₂ , port mmee,ans PM, and PM- and redundant columns RC, and

Memory circuit plane 12A also includes means 28 for coupling, respectively, the plurality of redundant columns RC to one or another of the plurality of data lines DL while simultaneously effectively decoupling one of the plurality of memory means 16A from one or the other of the data lines DL. Specifically, means 28 includes a control circuit 29 which, as will be further described, is programmable to respond to column addresses on lines 22 to defective columns. Means 28 also includes a switch means 30, controlled by control circuit 29, for connecting redundant column RC, to the data line DL, over a line 32 or to the data line DL- over a line 34. Means 28 further includes a switch means 36 for simultaneously effectively decoupling bit segment BS, from the data line DL, if redundant column RC, is coupled to data line DL, , and a switch means 38 for simultaneously effectively decoupling bit segment BS₂ from the data line DL₂ if redundant column RC,

OMPI IO is coupled to data line DL₂- Switch means 36 and switch means 38 are also controlled by control circuit 29.

Also, specifically, means 28 includes a switch means 40, controlled by control circuit 29, for connecting redundant column RC- to the data line DL, over a line 42 or to the data line DL₂ over a line 44. Simultaneously, means 28 will effectively decouple, via the switch means 36, bit segment BS, from the data line DL, if redundant column RC- is coupled to data line DL, .or, via the switch means 38, bit segment BS- from the data line DL₂ if redundant column RC- is coupled to data line DL₂. Thus, redundant column RC, can be switched to data line DL, or data line DL_, while bit segment BS, is effectively decoupled from data line DL, or bit segment BS- is effectively decoupled from data line DL₂, respectively. Also, redundant column RC- can be sv/itched to data line DL, or data line DL₂, while bit segment BS, is effectively decoupled from data line DL, or bit segment BS₂ is effectively decoupled from data line DL₂, respectively. Defective Column Condition No. 1

In the overall operation of the redundant means 26A, assume that, as manufactured, a column defect condition exists such that, for example, only column 18, and column 18- are shorted and, thereby, not usable for the storage of data.

Consequently, redundant column RC, and redundant column RC₂ are used to store the same data that otherwise would be stored by defective column 18, and defective column 18.,. Since bit segment BS, and, therefore, defective column 18, and defective column 18-, communicate with port means PM, only by the data line DL, , the means 28 will be programmed to couple redundant column RC, to the data line DL, via the line 32 and redundant column RC- to the data line DL, via the line 42 whenever column addresses on lines 22 are received to access defective column 18, and defective column 18-. Simultaneously, means 28 will respond to the column addresses on lines 22 to defective column 18, and defective column 18- by effectively decoupling bit segment BS, from the data line DL,.

Thus, when the column address on lines 22 to defective column 18, is received, means 28 responds by coupling redundant column RC, to data line DL, via line 32. Simultaneously, means 28 will respond by effectively decoupling the bit segment BS, from the data line DL, via switch means 36. Therefore, though address decoder AD, will also decode the address on lines 22 to access defective column 18,, the means 28 will enable a data transfer between redundant column RC, and port means PM, over data line DL, while disabling a data transfer between bit segment BS, and port means PM, over data line DL,.

Similarly, when the column address is received on lines 22 to access defective column 18-, means 28 responds by coupling redundant column RC- to data line DL, via line 42. Simultaneously, means 28 effectively decouples the bit segment BS, from the data line DL, via switch means 36. Thus, though address decoder AD, will also decode the address on lines 22 to access defective column 18-, the means 28 will enable a data transfer between redundant column RC„ and port means PM, over data line DL, while disabling a data transfer between bit segment BS, and port means PM, over data line DL₁. Thereafter, as will be further described, whenever a column address is received on lines 22 to a good or non-defective column 18 in bit segment BS, , means 28 decouples redundant column RC, and redundant column RC- from data line DL, via line 32 and line 42, respectively, and enables the coupling of the bit segment BS, to data line DL,- via switch means 36. Thus, a data transfer can occur between the non-defective columns 18 of bit segment BS, and port means PM, via data line DL,. Defective Column Condition No. 2

Assume now that, as manufactured, only column 20, and column 20- in bit segment BS- are shorted. Redundant column RC, and redundant column

RC- are now used to replace defective column 20, and defective column 20-. Since bit segment BS- and, hence, defective column 20, and defective column 20-, communicate with port means PM- via data line DL₂, the means 28 will couple redundant column RC, and redundant column RC- to data line DL₂ via respective line 34 and line 44 in response to the column addresses on lines 22 to defective column 20, and defective column 20-, respectively. Simultaneously, means 28 will respond to these column addresses on lines 22 to defective column 20, and defective column 20₂ by effectively decoupling bit segment BS- from data line DL_ via switch means 38.

Specifically, in response to the column address to defective column 20, on lines 22, means 28 will couple redundant column RC, to data line DL₂ via line 34 and effectively decouple, via switch means 38, the bit segment BS- from data line DL₂. Therefore, though address decoder AD- will also decode the address on lines 22 to access defective column 20,, the means 28 will enable a data transfer between redundant column RC, and port means PM₂ over data line DL₂ while disabling a data transfer between bit segment BS₂ and port means PM- over data line DL₂.

Similarly, in response to the column address on lines 22 to defective column 20-, means 28 will respond by coupling redundant column RC- to data line DL_ via line 44. Simultaneously, means 28 will effectively decouple bit segment BS₂ from data line DL- via switch means 38. Thus, though address decoder AD- will also decode the address on lines 22 to- access defective column 20₂, the means

28- will enable a data transfer between redundant column RC- and port means PM₂ over data line DL₂ while disabling a data transfer between bit segment BS- and port means PM- over data line DL-.

Thereafter, and as will be further described, whenever an address is received on lines 22 to a good or non-defective column 20 in bit segment BS-, means 28 decouples redundant column RC, and redundant column RC₂ from data line DL-, respectively, and enables the coupling of bit segment BS₂ to data line DL₂ via switch means 38. Therefore, the non-defective columns 20 can communicate with the port means PM via data line DL₂ for data transfer purposes. •

Defective Column Condition No. 3 Assume now that, as manufactured, only column 18- in bit segment BS, and column 20^ in bit segment BS- are defective. Consequently, redundant column RC, can be used to replace defective column 18- and redundant column RC- can be used to replace defective column 20.,. Since bit segment BS, and, hence, defective column 18-, communicate with port means PM, via data line DL,, redundant column RC, will be coupled by means 28 to data line DL, in the manner previously described whenever the column address to defective column 18- is on lines 22. Also, since bit segment BS₂ and, hence, defective column 20.,, communicates with port means P ₂ via data line DL₂, redundant column RC₂ will be coupled by means 28 to data line DL_ in the manner previously described whenever the column address to defective column 20-, is on lines 22.

Furthermore, in response to the column address on lines 22 to defective column 13-., means 28 effectively decouples bit segment BS, from data line DL, as previously described. And, in response to the column address to defective column 20- on lines 22, means 28 effectively decouples bit segment BS₂ from data line DL₂ as described above. Thus, data transfers can occur between port means PM, and redundant column RC, via data line DL, whenever the column address to defective column 18- is produced on lines 22, or data transfers can occur between port means PM_ and redundant column RC₂ via data line DL₂ whenever the column address to defective column 20_ is produced on lines 22. Thereafter, and as will be further described, whenever a column address is received on lines 22 to a good or non-defective column 18 in bit segment BS, , means 28 decouples redundant column RC, from data line DL, and enables the coupling of bit segment BS, to data line DL,, so that the non-defective column 18 can communicate with port means PM, via data line DL, . Or, whenever a column address is received on lines 22 to a good or non-defective column 20 in bit segment BS-, means 28 decouples redundant column RC- from data line DL₂ and enables the coupling of bit segment BS- to data line DL_ , so that the non- defective column 20 can communicate with port means PM_ via data line DL₂.

Defective Column Condition No. 4 Assume now that, as manufactured, only column 18. is defective. Under this condition, one of the redundant columns, e.g., redundant column RC, , can be used to replace the defective column

18.. In particular, whenever the column address to defective column 18. is received on lines 22, the means 28 responds by coupling redundant column RC, to data line DL, while effectively decoupling the bit segment BS, from data line DL, , as mentioned above. Whenever a column address to a non- defective column 13 in bit segment BS, is on lines 22, the means 28 responds by decoupling redundant column RC, from data line DL, and coupling bit segment BS, to data line DL,, as mentioned above.

In accordance with this defective condition, only one redundant column, e.g., redundant column RC, , is utilized and only coupled to data line DL,. Redundant column RC- is not used at all and always is decoupled from data line DL, and data line DL₂. However, in the manner previously described, redundant column RC- is available for use should another column 18 or a column 20 be defective. The memory circuit plane 12B is similar to memory circuit plane 12A and need not be disclosed in the same detail. Circuit plane 12B will have a comparable plurality of means 16A and a comparable redundant column circuit 26A. Circuit plane 12B also will have two additional data lines DL (not shown) similar to data lines DL, and data lines DL-, as well as two additional port means PM (not shown) similar to port means PM, and port means PM-, respectively. The manner in which the circuit plane 12B operates is identical- to the above-described operation of circuit plane 12A.

As can now be seen, the present invention can provide one redundant column RC per one port means PM. In addition, the two redundant columns RC, and RC₂ can be switched to the same data line, e.g. , data line DL, , thereby effecting a two redundant column per port means data transfer. This architecture has the advantages previously mentioned, such as the efficient usage of redundant columns.

Fig. 2 shows in more detail the memory circuit plane 12A of Fig. 1, and, in particular, the port means PM and the means 28. Fig. 2 shows in a similar manner as Fig. 1 the memory storing means 16A having the bit segment BS, , the address decoder AD, and the data line DL, , and the bit segment BS₂, the address decoder AD₂, and the data line DL₂, together with the lines 22 carrying the column addresses. Fig. 2 also shows the redundant column RC, and the redundant column RC-.

The port means PM, includes a sense amplifier SA, which is coupled to data line DL, and an input/output port I/O, coupled to the sense

OMPI * ^WI?° ti& a piifier SA, . The port means PM- includes a sense amplifier SA- which is coupled to the data line DL₂ and an input/output port I/O., coupled to the sense amplifier SA_. The sense amplifier SA, and sense amplifier SA- will amplify and output data on data line DL and data line DL₂ to port I/O, and port I/O-, respectively. While not shown, two data input buffers would be used to buffer and output data received from port I/O, and port I/O- onto data line DL, and data line DL-, respectively.

The means 28 includes programmable means shown generally at 46, responsive to defective column addresses on lines 22, for enabling a data transfer between the redundant column RC, and data line DL, via line 32 or between redundant column

RC, and data line DL- via line 34. In particular, as shown, overall programmable means 46 is a part - of control circuit 29,and also includes the switch means 30. A programmable address decoder means 48 of programmable means 46, when programmed, as will be described below, is responsive to a column address on lines 22 for producing a gate enabling signal on a line 52 or a gate enabling signal on a line 54. A pass gate 56 of switch means 30 is enabled by the gate enabling signal on line 52 to couple data between the redundant column RC, and the data line DL, via line 32. A pass gate 58 of switch means 30 is responsive to the gate enabling signal on line 54 to couple data between the redundant column RC, and the data line DL- via line 34.

The programmable address decoder means 48 includes a programmable redundant address decoder 60 that can be programmed to decode any one address to any column in bit segment BS, or bit segment BS-. The programmable redundant address decoder means 48 also includes a programmable multiplexer 62 having a programmable circuit 64 with one input coupled to the output of the decoder 60 over a line 66 and an output coupled to the line 52, as well as another programmable circuit 68 having one input coupled to the output of decoder 60 over the line 66 and an output coupled to the line 54. As will be further described, redundant address decoder 60 will be programmed to decode one column address to a defective column in bit segment BS, or bit segment BS₂. Also, either circuit 64 or circuit 68 will be programmed to select and switch the output of decoder 60 on line 66 to line 52 or line 54, respectively. The programming of either circuit 64 or circuit 68 will depend on the data line DL, or data line DL- to which the redundant column RC, should be coupled. Thus, in the operation of means 46, generally, assume that redundant address decoder 60 has been programmed to decode an address to a defective column in bit segment BS, which, as- previously described, communicates with the data line DL,. Consequently, only circuit 64 will be programmed to select and switch the output of decoder 60 on line 66 to line 52 to provide the gate enabling signal. Therefore, when the column address to this defective column is received on lines 22, decoder 60 will decode this address and produce an output signal, e.g., logic 1, on line 66. Multiplexer circuit 62 then. will couple this signal onto line 52 to enable the gate 56, whereby, for example, the data stored in redundant column RC, will be coupled through gate 56 and line 32 onto data line DL,.

On the other hand, assume that the redundant address decoder 60 has been programmed to decode a column address to a defective column in bit segment BS₂. As previously described, bit segment BS- communicates with data line DL-. Consequently, only circuit 68 will be programmed to couple line 66 to line 54. Therefore, when the address to this defective column is received on lines 22, redundant address decoder 60.produces a signal, e.g., logic 1, on line 66 that is selected and switched by circuit 68 onto line 54. In response, pass gate 58 is enabled to, for example, gate the data stored in redundant column RC, onto line 34 and, hence, data line DL-.

Programmable means 46 also includes a NOR gate 70 having one input coupled to the line 52 carrying the gate enabling signal and an output coupled over a line 72 to a pass gate 74 of switch means 36. When enabled, pass gate 74 couples data on data line DL, between the bit segment BS, and sense amplifier SA,. When disabled, pass gate 74 effectively decouples or inhibits data flow between the bit segment BS, and the sense amplifier SA, . Similarly, programmable means 46 includes a NOR gate 75 having one input coupled to the line 54 and an output coupled over a line 76 to a pass gate 78 of switch means 38. When enabled, pass gate 78 gates data on data line DL₂ between the bit segment BS- and the sense amplifier SA_. When disabled, pass gate 78 effectively decouples or inhibits data ffllooww bbeettwweeeenn tthe bit segment BS- and the sense amplifier SA₂.

OMPI XNATl- Thus, when the gate enabling signal is produced on line 52, e.g., a logic 1, NOR gate 70 responds by producing a logic 0 on line 72 to disable pass gate 74. When the gate enabling signal on line 52 is not produced, e.g., logic 0, NOR gate 70 may produce a logic 1 on line 72 to enable pass gate 74, depending on the other input to gate 70, as will be further described. Similarly, when the gate enabling signal on line 54 is produced, e.g., a logic 1, NOR gate 75 will produce a logic 0 on line 76 to disable pass gate 78. When the gate enabling signal on line 54 is not produced, e.g., logic 0, the NOR gate 75 may produce a logic 1 on line 76 to disable pass gate 78, depending on the other input to gate 75, as will be further described.

Thus, in the overall operation of programmable means 46, assume, as mentioned above, that redundant address decoder means 48 has been programmed to decode a defective column in bit segment BS,. Accordingly, when the address on lines 22 to this defective column is received by address decoder means 48, the logic 1 gate enabling signal on line 52 will be produced to enable gate 56, whereby redundant column RC, will, for example, output its data onto data line DL, via pass gate 56 and line 32. Simultaneously, the logic 1 gate enabling signal on line 52 will be inverted by NOR gate 70, which will produce a logic 0 on line 72 to disable pass gate 74. Consequently, the bit segment BS, , and in particular the defective column that is currently being addressed by address decoder AD, , is effectively decoupled from the data line DL,. -23-

Similarly, assume that address decoder means 48 has been programmed to decode a defective column in bit segment BS-. Consequently, when the address to that defective column is produced on lines 22, address decoder means 48 will produce the logic 1 gate enabling signal on line 54, whereby gate 58 will be enabled, for example, to couple data from the redundant column RC, onto the data line DL-. Simultaneously, NOR gate 75 will respond to the logic 1 on line 54 by outputting a logic 0 on line 76 to disable the pass gate 78. Accordingly, bit segment BS₂ and, in particular, the defective column currently being addressed by address decoder AD- , is effectively decoupled from the data line DL₂.

Means 28 also has a programmable means shown generally at 80 for enabling a data transfer between the redundant column RC₂ and the data line DL, via line 42 or between the redundant column RC- and the data line DL₂ via line 44, respectively.

In particular, as shown, overall programmable means 80 is a part of control circuit 29 and also includes switch means 40. A programmable redundant address decoder means 82 of programmable means 80, when programmed, produces a gate enabling signal on an output line 84 or a gate enabling signal on an output line 86 in response to a column address on lines 22. A pass gate 88 of switch means 40, in response to the gate enabling signal on line 84, couples or gates data between the redundant column RC₂ and the data line DL, via line 42. A pass gate 90 of switch means 40, in response to the gate enabling signal on line 86, couples or gates data between the redundant column RC₂ and the data line

_ OMPI DL₂ via line 44.

The programmable redundant address decoder means 82 includes a programmable decoder 92 that can be programmed to respond to an address to any one of the columns in bit segment BS, or bit segment BS-. A programmable multiplexer 94 includes a programmable circuit 96 having an input coupled to the output of decoder 92 over a line 98 and an output coupled to the line 84. A programmable circuit 100 of multiplexer 94 has an input coupled to the line 98 and an output coupled to the line 86.

In operation, first assume that redundant column RC₂ is to replace a defective column in bit segment BS, which, as previously mentioned, communicates only with the data line DL, . Accordingly, address decoder 92 is programmed to decode the column address on lines 22 to the defective column in bit segment.BS,. And, since bit segment BS, communicates with data line DL, , programmable circuit 96 is programmed to couple line 98 to line 84. Therefore, whenever, the column address to this defective column is produced on lines 22, address decoder 92 responds by producing an output signal on line 98, e.g., logic 1, that is selected and switched by circuit 96 onto line 84 as the gate enabling signal. In response, pass gate 88 is enabled to couple the redundant column RC- to data line DL, via line 42. Simultaneously, the logic 1 gate enabling signal on line 84 is provided as the other input to NOR gate 70, whose output then goes to a logic 0 on line 72 to disable pass gate 74. Consequently, bit segment BS, and, in particular the defective

OMPI colu n, is effectively decoupled from data line DL_χ.

Assume now that the redundant column RC 2 is to replace a defective column in the bit segment BS- which, as mentioned above, communicates only with the data line DL₂. Accordingly, address decoder 92 is programmed to decode the column ^• address on lines 22 to the defective column in bit segment BS-. And, therefore, programmable circuit 100 is programmed to couple line 98 to line 86. Thus, when the column address to this defective column in bit segment BS- is on lines 22, address decoder 92 responds by producing a logic 1 output signal on line 98 that is selected and switched by circuit 100 onto line 86 as the gate enabling signal. The pass gate 90 then is enabled to couple the redundant column RC- to data line DL- via line 44.

Also, simultaneous with the generation of the logic 1 gate enabling signal on line 86, which is the other input to NOR gate 75, a logic 0 is produced on line 76 to disable the pass gate 78. Consequently, the bit segment BS₂ and, in particular, the defective column in this bit segment BS-, is effectively decoupled from the data line DL₂.

If a defective column in bit segment BS, or bit segment BS- is not being addressed, but any one of the other good or non-defective columns in bit segment BS, or bit segment BS₂ is being addressed, then address decoder 60 and address decoder 92 output a logic 0 on line 66 and line 98, respectively. Consequently, line 52, line 54, line 84 and line 86 are at logic 0 to disable pass gate 56, pass gate 58, pass gate 88 and pass gate 90, respectively, whereby redundant column RC, and redundant column RC_ are decoupled from data line DL, and data line DL_2< However, NOR gate 70 and NOR gate 75 will respond by producing a logic 1 on line 72 and on line 76, respectively, whereby pass gate 74 and pass gate 78 are enabled. Accordingly, bit segment BS, and bit segment BS₂, and in particular, the non-defective columns, are effectively coupled to the data line DL, and data line DL-, respectively.

Fig. 3 shows a partial schematic of several of the components described in connection with Fig. 2. In particular. Fig. 3 illustrates schematically the programmable circuit 64 of programmable multiplexer 62 having the input line 66 and the output line 52. A transistor 101 has one electrode coupled to a node 102 and another electrode coupled to a line 104, while a programmable device 106 is coupled between line 104 via a node 108 and digital ground. The programmable device 106 can be, for example, a laser-blown type fuse or an electrically-blown type fuse. A circuit path shown generally at 110 is coupled between V and digital ground, and includes a series-connected transistor 112 and transistor 114. The transistor 114 has its gate electrode coupled to line 104 and, therefore, is turned on or off in response to a gating signal on line 104, The output of circuit path 110 is taken via a node 116 on a line 118 to control the gating on or off of a transistor 120.

Another circuit path shown generally at

OMPI ■ - 122 is coupled between +V and digital ground and has, in series-connection, a transistor 124, a transistor 126 and a programmable device 128. The output of circuit path 122 is taken via a node 130 over a line 132 to control the gating on or off of a transistor 134 which is in series circuit with the transistor 120. The programmable device 128 can be, for example, a laser-blown fuse or an electrically-blown fuse. A capacitor 136 is charged via V , transistor 124, transistor 126, node 130 and a node 138. The node 130 and the node 138 are electrically indistinguishable. Charged capacitor 136 is then used to hold on, via node 138, the transistor 101 and, via node 130, the transistor 134. A line 140 couples one electrode of transistor 134 to node 102, while output line 52 is coupled to a node 142 between electrodes of transistor 120 and transistor 134. Line 52 can be coupled to line 66 by programming both programmable device 106 and programmable device 128, i.e., by opening device 106 and device 128. Line 52 can be permanently decoupled from line 66 by not programming programmable device 106 and programmable device 128, i.e., by maintaining these programmable devices closed. The programming of device 106 and device 128 can occur using conventional programming techniques and depending on whether these devices are laser-blown or electrically-blown fuses.

Thus, assume first that programmable device 106 and programmable device 128 are both programmed. Consequently, node 130 and, hence, line 132 are at logic 1 since the path 122 to digital ground through the opened device 128 is open. Consequently, transistor 134 is gated on by the logic 1 at line 132.

Also, with the device 106 being opened, the path from node 108 to digital ground through opened device 106 is open. Therefore, when the signal on line 66 is at logic 1, transistor 101, which is gated on via source 136 and node 138, couples this logic 1 signal to line 104 and, thereby, gates on transistor 114. Therefore, the circuit path 110 is closed between +V - and digital ground, whereby node 116 and line 118 are at logic 0 to gate off transistor 120. Also, therefore, with transistor 134 being gated on, and with line 140 being at logic 1 via node 102, transistor 134 couples this logic 1 via node 142 to output line 52 as the previously mentioned logic 1 gate enabling signal.

However, when the signal on line 66 is at logic 0, then line 104 will be at logic 0 via transistor 101, whereby transistor 114 will be gated off and line 118 will go to logic 1. Consequently, transistor 120 will be gated on to couple line 52 via node 142 to digital ground, so that the previously mentioned logic 0 gate enabling signal is now on line 52.

Assume now that device 106 and device 128 are not programmed. Therefore, line 104 is coupled to digital ground through node 108 and closed device 106, so that line 104 is permanently at logic 0 to gate off transistor 114 and, thereby, gate on transistor 120. And, line 132 is coupled to digital ground via node 130 and device 128, so that line 132 is permanently at logic 0 to gate off transistor 134. Consequently, line 52 is always at logic 0, whereby line 52 is decoupled from line 66.

The other circuit 68 of programmable multiplexer 62 is similar to circuit 64 and can be programmed or not programmed, with similar results as described above. Lircuit 96 and circuit 100 of programmable multiplexer 94 are similar to circuit 64 and can be programmed or not programmed, with similar results as described above. Also shown schematically is the pass gate

56 which includes a transistor 144 having a gate electrode coupled to line 52, an electrode, coupled to redundant column RC, and another electrode coupled to line 32. Thus, when the gate enabling signal on line 52 is at logic 1, transistor 144 is gated on to couple redundant column RC, to data line DL, and when at logic 0, transistor 144 is gated off to decouple redundant column RC, from data line DL, . Pass gate 58 is illustrated schematically and includes a transistor 146 having a gate electrode coupled to line 54, one electrode coupled to redundant column RC, and another electrode coupled to data line DL-. Transistor 146 is gated on or off in a similar manner as transistor 144 to couple or decouple redundant column RC, with respect to data line DL-.

Pass gate 74 includes a transistor 148 which is in circuit with data line DL, . Transistor 148 has a gate electrode coupled to the output of NOR gate 70 over line 72, one electrode coupled to bit segment BS, and another electrode coupled to sense amplifier SA,. Pass gate 78 includes a transistor 150 which is in circuit with data line

SυR£Λ,

OMPI ' DL_. Transistor 150 includes a gate electrode coupled to the output of NOR gate 74 over line 76, one electrode coupled to bit segment BS₂ and another electrode coupled to sense-^amplifier SA₂. When line 72 is at logic 1 or at logic 0, transistor 148 is, respectively, gated on or off to enable or disable data flow between bit segment BS, and sense amplifier SA,. Transistor 150 operates in a similar manner for controlling data flow between bit segment BS- and sense amplifier SA₂.

As indicated generally in Fig. 3, data for each column 18 of bit segment BS, and each column 20 of bit segment BS₂ are accessed by using a conventional enhancement transistor T„ ϊ_* which typically has a 1-volt threshold that must be exceeded before the data are accessed. However, the data for redundant column RC, and redundant column RC, can be accessed by using a conventional zero threshold transistor which has only a zero voltage threshold that must be exceeded before the data are accessed. Consequently, by using the zero threshold transistor T„ for redundant column RC, and redundant column RC-, data are accessed more quickly. As indicated in Fig. 3, transistor 144, transistor 146 and the transistors (not shown) of pass gate 88 and pass gate 90 are the zero- threshold transistors T .

In the overall use and operation of memory circuit plane 12A, assume, as one example, that bit segment BS, has been manufactured with a defective column 18- and that bit segment BS₂ has been manufactured with a defective column 20-.. Therefore, address decoder 60 will be programmed in a conventional manner to decode the column address

OMPI to defective column 18- and circuit 64 will be programmed as described above to couple line 66 to line 52, with circuit 68 not being programmed. Also, address decoder 92 will be programmed in a conventional manner to decode the column address to defective column 20, and circuit 100 will be programmed, as described above, to couple line 98 to line 86, with circuit 96 not being programmed. Accordingly, the coupling and decoupling of redundant column RC, and the corresponding decoupling and coupling of bit segment .BS, with respect to data line DL, will occur as previously described, depending on whether defective column 18- is addressed or the other non-defective columns 18 are addressed. Also, the coupling and decoupling of redundant column RC- , and the corresponding decoupling and coupling of bit segment BS- with respect to data line DL- will occur as previously described, depending on whether defective column 20, is addressed or the other non- defective columns 20 are addressed.

In addition to the advantages of the present invention mentioned above, the architecture of the byte wide memory circuit 12, particularly the 4-bit byte wide architecture specifically described, requires only one, relatively low power sense amplifier SA per data line DL. The one sense amplifier SA such as sense amplifier SA, receives all data on data line DL, , whether from bit segment BS, or redundant column RC, or redundant column RC- for amplifying this data. This advantageously reduces the number of components' required for the present invention and the power requirement of the sense amplifier SA,. Furthermore, as illustrated, the redundant columns RC are coupled to the respective data lines DL at points along the data lines DL near the port means PM. This means that the loading on the data lines DL required to transfer the data from or to the redundant columns RC is reduced relative to the loading that would be required if the redundant columns RC were so coupled further away from port means PM. Moreover, unlike other types of architecture, the data in bit segment BS, or bit segment BS₂ and redundant column RC, or redundant column RC₂ are coupled through one or more pass gates only onto the data lines DL, thereby simplifying and expediting the processing of this data. The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modification as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

OMPI

Claims

1. Apparatus for accessing data, comprising: a) a plurality of memory means for storing data; b) a plurality of data lines corresponding, respectively, to said plurality of memory means; c) a plurality of port means coupled, respectively, to said plurality of data lines; d) a plurality of redundant means for storing data and corresponding, respectively, to said plurality of port means; and e) means for coupling, respectively, said plurality of redundant means to one or another of said plurality of data lines while decoupling one or another of said plurality of memory means from said one or another of said plurality of data lines.

2. Apparatus, according to claim 1, wherein said means for coupling and decoupling comprises programmable means for enabling a data transfer between one of said plurality of redundant means and said one or another of said plurality of data lines while disabling a data transfer between said one or another of said plurality of memory means and said one or another of said plurality of data lines.

3. Apparatus, according to claim 2, wherein each of said plurality of memory means has a plurality of addressable locations, and wherein said programmable means comprises: a) programmable address decoder means, responsive to an address to one addressable location of said plurality of addressable locations, for producing a first enabling signal or a second enabling signal; b) first means, responsive to said first enabling signal, for coupling data between said one redundant means and said one of said plurality of data lines; and c) second means, responsive to said second enabling signal, for coupling data between said one redundant means and said another of said plurality of data lines.

4. Apparatus, according to claim 3, wherein said programmable address decoder means comprises: a) a decoder being programmed to decode the address; and b) a multiplexer being programmed to couple said decoder to one of said first coupling means or said second coupling means.

5. Apparatus, according to claim 3, wherein said programmable means further comprises: a) first means, responsive to said first enabling signal, for disabling data flow between said one of said plurality of memory means and said one of said data lines; and b) second means, responsive to said second enabling signal, for disabling data flow between said another of said plurality of memory means and said another of said data lines.

6. A byte wide memory circuit, comprising: a) a main memory array having at least a first bit segment and a second bit segment, said first bit segment having a first plurality of columns for storing data and said second bit segment having a second plurality of columns for storing data; b) a first data line coupled to said first bit segment; c) a second data line coupled to said second bit segment; d) a first redundant column for storing " data; e) a second redundant column for storing data; f) programmable means for coupling said first redundant column to said first data line or said second data line while decoupling said first bit segment or said second bit segment from said first data line or said second data line, respectively, and for coupling said second redundant column to said first data line or said second data line while decoupling said first bit segment or said second bit segment from said first data line or said second data line, respectively; g) first means, coupled to said first data line, for sensing and amplifying all data on said first data line; h) second means, coupled to said second

OMPI data line, for sensing and amplifying all data on said second data line; i) a first data port coupled to said first sensing and amplifying means; and j) a second data port coupled to said second sensing and amplifying means.

7. A byte wide memory circuit, according to claim 6, wherein said programmable means for coupling and decoupling comprises: a) first programmable means -for enabling a data transfer between said first redundant column and said first data line or said second data line and for disabling a data transfer between said first bit segment or said second bit segment and said first data line or said second data line, respectively; and b) second programmable means for enabling a data transfer between said second redundant column and said first data line or said second data line and for disabling a data transfer between said first bit segment or said second bit segment and said first data line or said second data line, respectively.

8. A byte wide memory circuit, according to claim 7, wherein said first programmable means comprises: a) programmable address decoder means, responsive to an address to one column of said first plurality of columns or one column of said second plurality of columns, for-producing a first enabling signal or a second enabling signal; b) a first gate, responsive to said first enabling signal, for gating data between said first redundant column and said first data line; and c) a second gate, responsive to said second enabling signal, for gating data between said first redundant column and said second data line.

9. A byte wide memory circuit, according to claim 8, wherein said first programmable means further comprises: a) a third gate, coupled to said first data line, for gating data between said first bit segment and said first sensing and amplifying means; b) a fourth gate, coupled to said second data line, for gating data between said second bit segment and said second sensing and amplifying means; c) first means, responsive to said first enabling signal, for disabling said third gate; and d) second means, responsive to said second enabling signal, for disabling said fourth gate.

10. A byte wide memory circuit, according to claim 8, wherein said programmable address decoder means comprises: a) a decoder being programmed to decode the address; and b) a multiplexer being programmed to couple said decoder to one of said first gate or said second gate.

11. A byte wide memory circuit, according to claim 7, wherein said second programmable means comprises: a) programmable address decoder means, responsive to an address to one column of said first plurality of columns or one column of said second plurality of columns, for producing a first enabling signal or a second enabling signal; b) a first gate, responsive to said first enabling signal, for gating data between said second redundant column and said first"data line; and c) a second gate, responsive to said second enabling signal, for gating data between said second redundant column and said second data line.

12. A byte wide memory circuit, according to claim 11, wherein said second programmable means further comprises: a) a third gate, coupled to said first data line, for gating data between said first bit segment and said first sensing and amplifying means; b) a fourth gate, coupled to said second data line, for gating data between said second bit segment and said second sensing and amplifying means; c) first means, responsive to said first enabling signal, for disabling said third gate; and d) second means, responsive to said second enabling signal, for disabling said fourth gate.

13. A byte wide memory circuit, according to claim 11, wherein said programmable address decoder means comprises: a) a decoder being programmed to decode the address; and b) a multiplexer being programmed to couple said decoder to one of said first gate or said second gate.

14. A byte wide memory circuit, according to claim 6, wherein said first bit segment and said second bit segment include enhancement transistors for accessing data with respect to said first plurality of columns and said second plurality of columns, respectively, and said programmable means includes zero threshold transistors for accessing data with respect to said first redundant column and said second redundant - column.

15. A 4-bit byte wide memory circuit, comprising two memory circuit planes, each of said two memory circuit planes including: a) a first bit segment, having a first plurality of columns, for storing data and a second bit segment, having a second plurality of columns, for storing data; b) a first address decoder for decoding addresses to said first plurality of columns and a second address decoder for decoding addresses to said second plurality of columns; c) a first data line ^'coupled to said first bit segment and a second data line coupled to said second bit segment; d) a first redundant column for storing data and a second redundant column for storing data; e) a first pass gate coupled between said- first redundant column and said first data line and a second pass gate coupled between said first redundant column and said second data line; f) a first programmed address decoder, responsive to an address to one column of said first plurality of addressable columns or to one column of said second plurality of addressable columns, for producing a first gate enabling signal; g) a first programmed multiplexer for selecting and switching the first gate enabling signal to one of said first pass gate or said second pass gate; h) a third pass gate coupled between said second redundant column and said first data line and a fourth pass gate coupled between said second redundant column and said second data line; i) a second programmed address decoder, responsive to an address to another column of said first plurality of addressable columns or to another column of said second plurality of addressable columns, for producing a second gate enabling signal; j) a second programmed multiplexer for selecting and switching the second gate enabling signal to one of said third pass gate or said fourth pass gate; k) first input/output- port means for transferring all data on said first data line and second input/output port means for transferring all data on said second data line;

OMPI 1) a fifth pass gate, coupled to said first data line, for gating data between said first bit segment and said first input/output port means, and a sixth pass gate, coupled to said second data line, for gating data between said second bit segment and said second input/output port means; and m) first logic gate means, responsive to the enabling of said first pass gate or said third pass gate, for disabling said fifth pass gate and second logic gate means, responsive to -the enabling of said second pass gate or said fourth pass gate for disabling said sixth pass gate.

OMPI_ ;-θ