WO1982002276A1

WO1982002276A1 - Multi-bit read only memory cell sensing circuit

Info

Publication number: WO1982002276A1
Application number: PCT/US1980/001723
Authority: WO
Inventors: Corp Mostek
Original assignee: Jiang Ching Lin
Priority date: 1980-12-24
Filing date: 1980-12-24
Publication date: 1982-07-08

Abstract

Multi-bit read only memory sensing circuit (10). A plurality of storage transistors (30, 32, 34, 36) are arranged in rows (28) and columns (20, 22) and each have a predefined permanent threshold voltage. A plurality of reference transistors (40, 42, 44) are provided. Circuitry (100, 102, 104, 106) is provided for selectively comparing the output voltage of ones of the plurality of reference transistors (40, 42, 44) to the output voltage of the plurality of storage transistors (30, 32, 34, 36) to thereby determine the voltage level stored in each of the plurality of storage transistors (30, 32, 34, 36).

Description

MULTI-BIT READ ONLY MEMORY CELL SENSING CIRCUIT

TECHNICAL FIELD

This invention relates to read only memories, and more particularly to a multi-bit read only memory cell sensing circuit.

BACKGROUND ART

Large scale integration techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multi-component circuits in a conventional bistable configuration. There are numerous advantages of such semiconductor storage devices including high packing density and low power requirements of such memory cells. In previously developed prior art binary field-effect transistor read only memories, a plurality of address input lines and selection lines form a matrix with regions of a semiconductor substrate. Binary information is stored at locations between adjacent semiconductor regions by the presence or absence of field-effect transistors at that location. Alternate semiconductor regions are selectively connected to a voltage reference and the remaining regions lying in between are selectively connected to a common output by selecting a field- effect transistor in series with each region. Selection signals applied to the selection transistors of an adjacent pair of regions connect one region to the voltage reference and the other region to an output to provide a binary output signal which is a function of the data stored at a particular address storage location.

With the development of semiconductor storage device technology, there has been a need to increase the number of storage devices per unit area on the semiconductor chip. The increased storage capacity decreases the cost of manufacture of a semiconductor memory. In the course of the evolution of the semiconductor industry, the technique of ion irr.plantation into the channel region of a field-effect transistor

-£3E_-__ o...?ι device has been developed to adjust the threshold voltage for the device so that the gate voltage at which the device will switch can be customized. With the use of ion implantation, memory cells have utilized field-effect transistors having different threshold voltages requiring sensing circuitry for determining the voltage levels stored in such memory cells. One such sensing scheme is described in U.S. Patent No. 4,202,044 issued to Beilstein, Jr. et al on May 6, 1980 and entitled "Quaternary FET Read Only Memory" .

A need has thus arisen for a multi-bit read only memory cell sensing circuit for use with read only memory storage devices utilizing multi-level ion implantation to set multi-level threshold voltage levels in the storage devices. Such a sensing circuit must be simple in construction and operation to complement the advantages of multi-bit read only memory cells.

DISCLOSURE OF THE INVENTION

In accordance with the present invention, a sensing circuit is provided for use with a multi-bit read only memory cell. ^* In accordance with the present invention, a multi-bit read only memory having a plurality of storage transistors, each having drain, source and gate terminals, arranged to form rows and columns is provided. Each of the plurality of storage transistors has a predefined permanent threshold voltage. The gate terminals of a row of the plurality of storage transistors are each connected to a common word line input. The source terminals of a column of the plurality of storage transistors are each connected to a common bit line. The drain terminals of the plurality of storage transistors are connected to a common reference voltage source. A plurality of reference transistors is provided, each having drain, source and gate terminals arranged into rows and columns. Each of the plurality of reference transistors has a predefined permanent threshold voltage. The gate terminals of a row of the plurality of reference transistors are each connected to one of the common word lines associated with a row of the plurality of storage transistors. The source terminals of a column of the plurality of reference transistors are connected to a source voltage supply, and the drain terminals of the plurality of reference transistors are connected to a common reference voltage source. Circuitry is further provided for selectively comparing the output voltage of ones of the plurality of reference transistors to the output voltage of the plurality of storage transistors to thereby determine the voltage level stored in each of the plurality of storage transistors.

OMPI BRIEF DESCRIPTION OF DRAWINGS

For a more complete understanding of the present invention and for further advantages thereof, reference will now be made to the following Detailed Description taken in conjunction with the accompanying Drawings in which:

FIGURE 1 is a schematic circuit diagram of the present multi-bit read only memory cell sensing circuit; and FIGURE 2 illustrates signal waveforms illustrating the operation of the present read only memory cell sensing circuit.

DETAILED DESCRIPTION

Referring to FIGURE 1, the read only memory (ROM) cell sensing circuit of the present invention is illustrated and is generally identified by the numeral 10^". Sensing circuit 10 is illustrated in FIGURE 1 as only a portion of an array of numerous such ROM memory cells arranged in rows and columns in a conventional manner to form a read only memory. The ROM thereby formed using the present sensing circuit 10 may be fabricated on a single semiconductor chip and is primarily intended for such fabrication utilizing metal-oxide-semiconductor technology.

When arranged in an array of memory cells, the memory cells are disposed in columns and connected to bit lines 20 and 22 and column lines 24 and 26. Since memory cells are typically disposed in separate rows of a read only memory, the rows are addressed or enabled by separate word lines, such as word line 28. Word line 28 enables all memory cells in one row of the read only memory.

Interconnected to word line 28 are memory storage transistors 30, 32, 34 and 36 each having gate, drain and source terminals forming storage cells. Memory storage transistors 30, 32, 34 and 36 are representative of numerous other such storage transistors interconnected to word line 28. The gate terminals of storage transistors 30, 32, 34 and 36 are each connected to word line 28. The respective source terminals are connected to either of bit lines 20 or 22. The respective drain terminals are connected to either of column lines 24 or 26. Each of storage transistors 30, 32, 34 and 36 are capable of having different ion implantations to establish threshold levels of, for example, .5, 2.5, 5 and 8 volts. Each memory cell of the ROM, therefore, has the capability of storing multi-level or multi-bit data within a single memory cell.

OMPI The sensing circuit for determining the voltage level stored within the cells formed by storage transistors 30, 32, 34 and 36 includes reference transistors 40, 42 and 44 each having gate, source and drain terminals. The reference transistors 40, 42 and 44 are provided for each word line of the ROM and, as illustrated in FIGURE 1, are provided for word line 28. Similarly, a set of reference cells is provided for each word line of the ROM utilizing the present sensing circuit 10. The source terminal of reference transistor 40 is interconnected to a reference data line 48. The drain terminal of reference transistor 40 is interconnected to a reference column line 50 at ground potential. The drain terminal of reference transistor 42 is interconnected to a reference column line 52. The source terminal of reference transistor 42 and the source terminal of reference transistor 44 are interconnected to a reference data line 54. The drain terminal of reference transistor 44 is interconnected to a reference column line 56. The threshold levels of reference transistors 40, 42 and 44 may be established at, for example, .5, 2.5 and 5 volts, respectively.

Source voltage supply, _cc. is applied to precharge transistors 60, 62, 64, 66, 68, 70, 72 and 74. The gates of precharge transistors 60, 62, 64, 66, 68, 70, 72 and 74 receive the PC, precharge signal, to be subsequently described with reference to FIGURE 2. Precharge transistor 60 precharges reference data line 48. Precharge transistor 68 precharges reference column line 52. Precharge transistor 64 precharges reference data line 54. Precharge transistor 66 precharges reference column line 56. Precharge transistor 68 precharges bit line 20. Precharge transistor 70 precharges column line 24. Precharge transistor 72 precharges bit line 22. Precharge transistor 74 precharges column line 26. All bit lines, column lines, reference column lines and reference data lines are precharged to a value of V less one threshold.

Reference column lines 52 and 56 are activated to provide a ground voltage potential to the drains of reference transistors 42 and 44 by actuation of transistors 80 and 82. The gate of transistor 80 is activated by an address change to the ROM by detecting a one bit change in the address. This one bit change, designated as the most significant bit

(MSB), is applied in one of two states, MSB and MSB to transistors 80 and 82, respectively. The MSB address bit also controls the voltage level on word line 28. When MSB is a logic high, the voltage on word line 28 is bootstrapped to a value greater than V , for example, 8 volts. When MSB is a logic low, the voltage on word line 28 is at V , for example, 5 volts. An important aspect of the present sensing circuit 10 is the use of this multi-level word line addressing scheme for determining the value of data stored within storage transistors 30, 32, 34 and 36.

The present sensing circuit 10 functions to compare each of the threshold voltage levels stored in the reference cells formed by reference transistors 40, 42 and 44 to each of the cells formed by storage transistors 30, 32, 34 and 36. Four voltage level thresholds can be determined using a minimum number of three reference cells, 40, 42 and 44. This comparison is made by a pair of differential amplifiers associated with each storage transistor 30, 32, 34 and 36. Illustrated in FIGURE 1, for simplicity of illustration, are two such pairs of differential amplifiers associated with storage transistors 30 and 32. Associated with storage transistor 30 are differential amplifiers 100 and 102.

OMPI Associated with storage transistor 32 are differential amplifiers 104 and 106. It is understood that associated with storage transistor 34 are similarly configured differential amplifiers 100 and 102 and associated with storage transistor 36 are similarly configured differential amplifiers 104 and 106. Each differential amplifier 100, 102, 104 and 106 includes three transistors identified by the suffix "a", "b" and "c". Differential amplifiers 100 and 102 are connected in parallel across storage transistor 30 as are differential amplifiers 104 and 106, being connected in parallel across storage transistor 32. It therefore can be seen that only two differential amplifiers for each storage transistor are necessary in the present sensing circuit 10.

The source terminal of storage transistor 30 is interconnected to the gate terminals of transistors 100a and 102a. The drain terminal of storage transistor 30 and drain terminal of storage transis^'tor 32 are connected by column line 24 to the drain terminals of transistors 100c, 102c, 104c and 106c. The differential input to differential amplifier 100 is applied to the gate terminal of transistor 100b via reference data line 54. The differential input to differential amplifier 102 is applied to the gate terminal of transistor 102b via reference data line 48. Similarly, the differential input to differential amplifier 104 is applied to the gate terminal of transistor 104b from reference data line 54. The differential input to differential amplifier 106 is applied to the gate terminal of transistor 106b via reference data line 48.

The outputs of differential amplifier 100 are applied from the source terminal of -transistor 100a via an output ^ line Dl, 110, and from the source terminal of transistor 100b via an output line Ϊ5X, 112. The outputs of differential amplifier 102 are applied from the source terminal of transistor 102a via output line Dl' , 114, and from the source terminal of transistor 102b via output line Dl¹, 116. The outputs of differential amplifier 104 are applied from the source terminal of transistor 104a to an output line D2, 118, and from the source terminal of transistor 104b via an output line 1)2., 120. The outputs of differential amplifier 106 are applied from the source terminal of transistor 106a via an output line D2' , 122, and via the source terminal of transistor 106b via an output line D2', 124.

The outputs of differential amplifier 100 via output lines 110 and 112 are applied to a flip-flop circuit 130. The outputs of differential amplifier 102 via output lines 114 and 116 are applied to a flip-flop circuit 132. Similarly, the outputs of differential amplifiers 104 and 106 are applied via output lines 118 and 120, and output lines 122 and 124 to flip-flop circuits (not shown) similar to flip-flop circuits 130 and 132. The outputs of differential amplifiers 100 and 102, Dl and Dl" identify the voltage threshold levels of data stored within storage transistor 30.

The output of flip-flop circuit 130, DΪ, is applied via signal line 134 to a NOR circuit 136 which generates the DATA signal. The DATA signal represents the decoded output of differential amplifiers 100 and 102 to provide the data value stored within a particular storage transistor 30. The output of flip-flop circuit 132, Dl' , is applied to an AND circuit 138 which also receives the MSB, most significant bit, from the address to the random access memory. The output of AND circuit 138 is applied to NOR circuit 136.

Applied to column line 24 through a transistor 150 is the CD, column decode, signal which, as will subsequently be described with respect to FIGURE 2, provides a ground voltage potential to column line 24. Interconnected to reference data lines 48 and 54 are capacitors 152 and 154 which provide a delay for the application of the signals on reference data lines 48 and 54 to differential amplifiers 102, 106 and 100, 104, respectively.

In operation of the present sensing circuit 10, the value of the' threshold voltage of reference transistors 40 • nd 42 or reference transistors 40 and 44 are each compared to the voltage level stored in each of the storage transistors 30, 32, 34 and 36 to determine the value actually stored within these storage cells. The output of reference transistor 40 is always applied to differential airiplifiers 102 and 106. The determination of whether the output of reference cells 42 or 44 will be applied to differential amplifiers 100 and 104 via reference data line 54 is determined by the state of address to the read only memory by changing the MSB. The presence of MSB applied to the gate terminal of transistor 80 applies the output of reference transistor 42 via reference data line 54 to differential amplifiers 100 and 104. Alternatively, the presence of the MSB signal from the address to the read only memory, applied to the gate terminal of transistor 82 permits the output of reference transistor 44 to be delayed by capacitor 154 and applied via reference data line 54 to differential amplifiers

100 and 104. In this way, the address can control which of the two reference cells 42 and 44 provide a differential input to differential amplifiers 100 and 104. The differential input to differential amplifiers 100 and 102 is applied from storage transistor 30 by supplying a ground reference potential to the drain terminal of storage transistor 30 via column line 24. This ground reference potential is also supplied to the ^"*r__vde formed between transistors 100c and 104c of differential amplifiers 100 and 104 and the node formed

OMPI between transistors 102c and 106c of differential amplifiers 102 and 106. Storage transistor 30 will then, in turn, supply data on bit line 20 for application to differential amplifiers 100 and 102. Because column line 24 is shared between storage transistors 30 and 32, .^{' •} storage transistor 32 provides its data on bit line 22 for application to differential amplifiers 104 and 106. •. " Therefore, it can be seen that storage transistors 30 and:: 32 are read simultaneously to thereby read two memory^{' '} . cells at once.

The rate at which the differential inputs are ^"applied to each of the differential amplifiers 100, 102, 104 and 106 will determine the state of the output signal of each of the differential amplifiers 100, 102, 104 and 106, which indicates the V_. of a storage transistor..- These output signals are applied via flip-flop circuits^' 130 and 132 to NOR circuit 136 and AND circuit 138 which decode the differential outputs to provide the data value of the voltage stored within storage cells 30, 32, 34 and 36. The present sensing circuit 10 operates in a two page mode, such that two levels or pages of data can be stored within each memory transistor 30, 32, 34 and 36. In page one mode, the MSB signal is a logic low to place word line 28 at the level of V_cc. for example, 5 volts. The logic outputs of differential amplifiers 100 and 102, Dl and Dl', and the DATA signal representing the data value stored within storage transistor 30 for each of the four possible V_τ levels of memory transistors 30, 32, 34 and 36 are indicated in Table 1 below.

O PI Table 1 v_τ Level (^* ^*/o Its)

.5 2.5 5 8

Logic Output

Signal

Dl 1 1 0 0

Dl' 1 0 0 0

DATA 1 1 0 0

In the page two mode, word line 28 is bootstrapped such that the voltage level on word line 28 is bootstrapped above V_cc when the MSB signal is high. The logic outputs of differential amplifiers 100 and 102, Dl and Dl', and the DATA signal for the page two mode of operation are indicated in Table 2 below.

Table 2 V_τ Level (volts)

.5 2.5 5 8

Logic Output

Signal

Dl 1 1 1 0

Dl' 1 0 0 0

DATA 0 1 1 0

The coding scheme for each V_τ voltage level of the four possible V_τ voltage levels for the page one and page two modes of operation are set forth in Table 3 below.

Table 3 V_τ Level (volts)

.5 2.5 5 8

Page Data

Page 1 1 1 0 0

Page 2 0 1 1 0

OWl It therefore can be seen that two levels of data can be stored within each storage transistor 30 and read by utilizing the multi-level word line addressing scheme of the present invention. For example, at a V-. voltage level of .5 volts, the data stored in storage transistor

^■ 30 for page one is a logic 1 and at page two is a logic 0. To further understand the operation of the present

^■ sensing circuit 10, reference will now be made

' ' . simultaneously to the waveforms of FIGURE 2 wherein

10 ^* FIGURE 2a illustrates the voltage level of the precharge •^* signal, PC; FIGURE 2b illustrates the voltage waveform .^'. present on column lines 24 and 26; FIGURE 2c illustrates ^• the voltage level of the CD signal; FIGURE 2d illustrates the voltage level of word line 28; and FIGURE 2e

15. illustrates the voltage waveform present on bit lines 20 and 22.

Initially, bit lines 20 and 22 are precharged using the PC signal (FIGURE 2a) to a high voltage level of V less one threshold (FIGURE 2e) . The column lines 24 and

20 26 (FIGURE 2b) are also precharged using the PC signal

(FIGURE 2a) applied to column lines 24 and 26 to a value of V less one threshold. This precharging insures that bit lines 20 and 22 and column lines 24 and 26 are guaranteed to a high value when the PC signal goes low.

25 When precharging has been complete, storage transistors 30, 32, 34 and 36 are capable of being read with the application of the column decode, CD, signal (FIGURE 2c). When the CD signal goes high, reference numeral 160, column lines 24 and 26 are pulled to ground, reference

30 numeral 162. The CD signal goes high shown in FIGURE ^'2c at the.end of the precharge cycle (FIGURE 2a), reference line- 164. Column line 24, being grounded, supplies a ground for differential amplifiers 100, 102, 104 and 106 and a ground for storage transistors 30 and 32. In response to the address signal applied to the read only memory, as column line 24 is going low, a voltage on word line 28 will rise. At reference line 166, a ground is provided to storage transistors 30 and 32 such that storage transistors 30 and 32 can be read. Since column line 24 is at ground and the word line 28 continues to rise, eventually a threshold of storage transistors 30 and 32 is reached depending on the voltage level stored. At that point, storage transistors 30 and 32 turn on, such that their respective outputs are applied on bit lines 20 and 22.

The voltage on bit lines 20 and 22 will start to decrease from that previously precharged high level towards a lower level as shown in FIGURE 2e, or remain at a high level depending upon whether the threshold level of storage transistors 30, 32, 34 or 36 is below or above the gate drive provided by word line 28. For example, if the threshold value of storage transistor 30 were .5 volts, then as soon as word line 28 reached .5 volts, storage transistor 30 would begin to turn on and the voltage level on bit line 20 would begin to fall. At that point, none of the reference transistors 40, 42 or 44 would be on. The capacitance provided by capacitor 152 in reference data line 48 insures that the voltage applied to differential amplifier 102 from reference transistor 40 is applied at a slower rate than the input provided by storage transistor 30 to differential amplifiers 100 and 102. Capacitor 152 insures that the rate of fall of the voltage on bit line 20 will be greater than the rate of fall of the voltage on reference data line 48 where the voltage threshold of storage transistor 30 is .5 volts. However, if the voltage threshold level of storage transistor 30 is 2.5 volts, the voltage level on reference data line 48 will fall at a much faster rate than the voltage level on bit line 20. In such a manner, a comparison is made between the output of a reference cell and the output of a storage cell by differential amplifiers 100 and 102 for storage transistor 30. After the comparison of the outputs of reference transistors 40 and 42 have been made to the output of storage transistor 30, the comparison is made between the outputs of reference transistors 40 and 44 to the output of storage transistor 30.

It therefore can be seen that the present sensing circuit 10 provides for the sensing of a read only memory cell that has one of four implanted threshold levels and which operates in a two page mode wherein two bits per cell can be stored. Two differential amplifiers are utilized for each read only memory cell. A comparison is first made between the value stored in a stored cell to a first set of reference values to determine whether the value stored in the ROM cell corresponds to one of two voltage states of the stored cell. A comparison is made to a second reference to determine whether a value stored in the ROM cell is one of the other two states or bit levels. The output of the differential amplifiers provides two bits for each of the two comparisons made, which are subsequently decoded to identify the data value stored within a memory cell of the read only memory. Page mode selection is achieved by utilizing the multi-level addressing scheme on the word line of the ROM.

Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Q_._PI

Claims

1. A multi-bit read only memory comprising: a plurality of storage transistor means for storing data each having drain, source and gate terminals, arranged in a row, each of said plurality of storage transistor means having a plurality of predefined permanent threshold voltage levels for generating an output voltage when actuated; word line means for receiving an input signal; said gate terminals of said plurality of storage transistor means each connected to said word line means, said source terminals of said plurality of storage transistor means each connected to a common bit line and said drain terminals of said plurality of storage transistor means connected to a reference voltage source; a plurality of reference transistor means each having drain, source and gate terminals arranged in a row, each of said plurality of reference transistor means having a predefined permanent threshold voltage level for generating an output voltage when actuated; said gate terminals of said plurality of reference transistor means each connected to said word line means, said source terminals of said plurality of reference transistor means each connected to a source voltage supply and said drain terminals of said plurality of reference transistor means connected to a common reference voltage source; and means for selectively comparing the output voltage of ones of said plurality of reference transistor means to the output voltage of each of said plurality of storage transistor means to thereby determine the voltage level stored in each of said plurality of storage transistor means.

OMPI

2. The multi-bit read only memory of Claim 1 wherein said means for comparing includes: differential amplifier means connected to said plurality of transistor means to receive said output voltage generated by said plurality of storage transistor means and to receive said output voltage generated by said plurality of reference transistor means to generate an output signal representing the voltage level stored in one of said plurality of storage transistor means.

3. The multi-bit read only memory of Claim 2 and further including: means for decoding said differential amplifier means output signal for determining the data value stored in one of said plurality of storage transistor means.

4. The multi-bit read only memory of Claim 2 wherein said differential amplifier means includes: first and second amplifier means each connected in parallel with each one of said plurality of storage transistor means to receive said output voltage generated by one of said plurality of storage transistor means, said first amplifier means connected to receive an output voltage from one of said plurality of reference transistor means and said second amplifier means connected to receive an output voltage from a different one of said plurality of reference transistor means.

5. The multi-bit read only memory of Claim 1 and further including: means for delaying the application of said output voltages from said plurality of reference transistor means to said first and second amplifier means.

6. The multi-bit read only memory of Claim 1 wherein said plurality of reference transistor means comprises first, second and third reference transistor means having first, second and third predefined permanent threshold voltage levels.

7. The multi-bit read only memory of Claim 6 wherein said plurality of predefined permanent threshold voltage levels of said plurality of storage transistor means comprises first, second, third and fourth threshold voltage levels.

8. The multi-bit read only memory of Claim 1 wherein said input signal received by said word line includes first and second voltage levels for determining two voltage levels stored in each of said plurality of storage transistor means.

9. A multi-bit read only memory comprising: a plurality of storage transistor means for storing data each having drain, source and gate terminals, arranged in a row, each of said plurality of storage transistor means having first, second, third and fourth predefined permanent threshold voltage levels for generating an output voltage when actuated; word line means for receiving an input signal; said gate terminals of said plurality of storage transistor means each connected to said word line means, said source terminals of said plurality of storage transistor means each connected to a common bit line and said drain terminals of said plurality of storage transistor means connected to a reference voltage source; first, second and third reference transistor means and having drain, source and gate terminals arranged in a row, and having one of a first, second or third predefined permanent threshold voltage level for generating an output voltage when actuated; said gate terminals of said first, second and third reference transistor means each connected to said word line means, said source terminals of said first, second and third reference transistor means each connected to a source voltage supply and said drain terminals of said first, second and third reference transistor means connected to a common voltage source; and differential amplifier means connected to said plurality of storage transistor means and to said first, second and third reference transistor means to receive said output voltage generated by said transistor means for selectively comparing the output voltage of ones of said first, second and third reference transistor means to the output voltage of each of said plurality of storage transistor means to thereby determine the voltage level stored in each of said plurality of storage transistor means.

^_Υ^E Ti OMPI

10. The multi-bit read only memory of Claim 9 and further including: means for decoding said differential amplifier means output signal for determining the data value stored in one of said plurality of storage transistor means.

11. The multi-bit read only memory of Claim 9 wherein said differential amplifier means includes: first and second amplifier means each connected in parallel with each one of said plurality of storage transistor means to receive said output voltage generated by one of said plurality of storage transistor means, said first amplifier means connected to receive an output voltage from said first reference transistor means and said second amplifier means connected to receive an output voltage from said second and third reference transistor means.

12. The multi-bit read only memory of Claim 11 and further including: means for delaying the application of said output voltages from said first, second and third reference transistor means to said first and second amplifier means.

13. The multi-bit read only memory of Claim. 9 wherein said input signal received by said word line includes first and second voltage levels for determining two voltage levels stored in each of said plurality of storage transistor means.

14. A method for reading a multi-bit read only memory cell having a plurality of memory transistors and a plurality of reference transistors arranged on a common word line comprising the steps of: applying a first voltage to the word line; selectively actuating each of the reference transistors; generating an output signal from the reference transistors when actuated; selectively comparing the output of an actuated memory transistor with ones of the output signals of the reference transistors to generate a first reference signal indicating the voltage level in the actuated memory transistor; and decoding the reference signal to provide a first data signal indicating a first bit of data stored in the actuated memory transistor.

OMPI

15. The method for reading a multi-bit read only memory cell of Claim 14 and further including the steps of: applying a second voltage to the word line; ^* selectively actuating each of the reference transistors; generating an output signal from the reference transistors when actuated; selectively comparing the output of an actuated memory transistor with ones of the output signals of the reference transistors to generate a second reference signal indicating the voltage level stored in the actuated memory transistor; and decoding the reference signal to provide a second data signal indicating a second bit of data stored in the actuated memory transistor.

-ROSEAU"

OMPI