USRE42117E1 - Apparatus for operating a CMOS imager having a pipelined analog to digital converter - Google Patents
Apparatus for operating a CMOS imager having a pipelined analog to digital converter Download PDFInfo
- Publication number
- USRE42117E1 USRE42117E1 US11/896,441 US89644107A USRE42117E US RE42117 E1 USRE42117 E1 US RE42117E1 US 89644107 A US89644107 A US 89644107A US RE42117 E USRE42117 E US RE42117E
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- United States
- Prior art keywords
- analog
- digital
- signals
- converter
- successive
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Definitions
- the reissue applications are ( 1 ) reissue application Ser. No. 11 / 812 , 785 filed on Jun. 21 , 2007 , ( 2 ) Ser. No. 11 / 869 , 441 ( the present application ) filed on Aug. 31 , 2007 , and ( 3 ) Ser. No. 11 / 869 , 442 also filed on Aug. 31 , 2007 .
- the applications Ser. Nos. 11 / 869 , 441 and 11 / 869 , 442 are continuation of reissue application Ser. No. 11 / 812 , 785 .
- CMOS active pixel sensor The basic operation of a CMOS active pixel sensor is described in U.S. Pat. No. 5,471,215 5 , 471 , 515 .
- This kind of image sensor, and other similar image sensors often operate by using an array of photoreceptors to convert light forming an image, into signals indicative of the light, e.g. charge based signals. Those signals are often analog, and may be converted to digital by an A/D converter. Image sensors which have greater numbers of elements in the image sensor array may produce more signals. In order to handle these signals, either more A/D converters must be provided, or the existing A/D converters need to digitize the data from these image sensors at higher signal rates. For example, a high precision CMOS active pixel sensor may require an A/D converter which is capable of 10 bits of resolution at 20 Megasamples per second.
- Image sensors of this type are often limited by the available area or “real estate” on the chip, a and the available power for driving the chip.
- An advantage of using CMOS circuitry is that power consumption of such a circuit may be minimized. Therefore, the power consumption of such a circuit remains an important criteria. Also, since real estate on the chip may be limited, the number of A/D converters and their size should be minimized.
- A/D converters with this kind of resolution may have a power consumption of about 25 mw using a 3.3 volt power supply.
- a CMOS image sensor includes an analog to digital converter to convert successive analog signals, representing at least a portion of an image, into successive digital signals. Multiple clock cycles may be used by the converter to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal.
- the present application describes a system, and a special A/D converter using individual successive approximation A/D converter cells which operate in a pipelined fashion.
- FIG. 1 shows a block diagram of a circuit on a chip including an image sensor and A/D converter
- FIG. 2 shows relative timing of A/D converter cells
- FIG. 3 shows an embodiment with built-in calibration in the system
- FIGS. 4A and 4B show two alternative schemes for implementing the A/D converter timing and control.
- a plurality of successive approximation A/D converter cells are provided.
- the embodiment recognizes that the pixel analog data is arriving at a relatively high rate, e.g. 20 Mhz.
- a plurality of A/D converters are provided, here twelve A/D converters are provided, each running at 1.6 megasamples per second.
- the timing of these A/D converters are staggered so that each A/D converter is ready for its pixel analog input at precisely the right time.
- the power consumption of such cells is relatively low; and therefore the power may be reduced.
- FIG. 1 shows how a single chip substrate 100 includes a photo sensor array 110 .
- Photosensor array 110 can be an array of, for example, photodiodes, photogates, or any other type of photoreceptors.
- the output 115 of the array 110 is coupled to a timing circuit 120 which arranges the data to be sent to the A/D converter array 130 .
- the data is sent such that each A/D converter receives data at a different, staggered time.
- FIG. 2 shows how the timing and switching of the data is carried out.
- the input signals from the image sensor array 110 are staggered and provided to the A/D converters at different times, preferably one clock cycle apart.
- FIG. 2 shows the relative timing of four of the twelve A/D converter cells.
- the first row 200 for example may represent the first A/D converter.
- Data that is input during cycle No. 1 is available at the output of the A/D converter during cycle No. 12 . Different data from different ones of the converters are output in each cycle.
- FIG. 3 shows a block diagram of each of the twelve A/D converter elements.
- the elements may operate using capacitors formed by a capacitor array 300 .
- unit cell capacitors are formed.
- the capacitor array 300 is formed, for example, of N different elements, each of which are identical. Matching each of these capacitors may ensure linearity.
- a switching element 310 may switch the capacitor combinations in the proper way to convert a specific bit. As conventional in a successive approximation A/D converter, different bits are obtained and output during different clock cycles. Hence the clock input at 315 may select the different bits which are used and may hence select the number of the capacitor elements which are used.
- This system may adaptively assign the channels to A/D converters in a different way than conventional. Conventional methods of removing fixed patterned noise, therefore, might not be as effective. Therefore, it becomes important that these A/D converters have consistent characteristics.
- calibration may be used to compensate for offsets between the comparators of the system.
- Successive approximation A/D converters as used herein may have built-in calibration shown as elements 320 . Any type of internal calibration system may be used.
- comparator kickback noise may become a problem within this system. That comparator itself may produce noise which may affect the signal being processed.
- a single preamplifier here shown as a follower 330 , is introduced between the signal and the comparator.
- This system also requires generation of multiple timing and control signals to maintain the synchronization.
- Each successive approximation A/D converter requires about 20 control signals.
- the timing is offset for each of the twelve different A/D converters. Therefore, digital logic is used to replicate control signals after a delay.
- a plurality of flip-flops are used to delay the respective signals.
- the control signals showed as A in and B in are separately delayed using a series of flip-flops; with A in delayed by flip-flops 400 , 408 , 409 ; and B in delayed by flip-flops 404 , 421 , 422 .
- the control signal A in is delayed by flip-flop 400 to produce signal A 1 , line 405 , which is the first control signal for the first A/D converter 402 .
- the B in control signal is delayed by flip-flop 404 to produce the B 1 control signal for the A/D converter 402 .
- the A 1 signal 405 also drives the input of the second D flip-flop 408 .
- the output of flip-flop 408 similarly drives flip-flop 409 and the like.
- Each successive output such as 405 is then delayed by the next flip-flop 408 , and used as the respective second control (here A 2 , B 2 ) for the A/D converters.
- Each cycle of the A/D converter may require finer timing than can be offered by a usual clock.
- the clock input 410 may be a divided higher speed clock.
- Two D type flip-flops are required to delay each signal. Any signal which is only half a clock cycle in length may require falling edge flip-flops, in addition to the rising edge flip-flops, and may also require additional logic.
- FIG. 4B shows an A/D converter cell with a trigger signal that is staggered by one or two flip-flops according to the master clocks. All of the local control signals may be generated locally within the A/D converter. Delayed versions of the clock are still obtained. For example, the D type flip-flops 450 produces a delayed version 452 . Delayed version 452 triggers the next the flip-flop 454 to produce delayed version 456 . Each of the delayed versions, such as 452 , is further processed by the logic block 460 .
- Logic block for 60 outputs the two control signals A 1 and B 1 . For example, the control signal A 1 may be output directly, with control signal B 1 being delayed by a series of logic gates or transistors. Since this system uses fewer flip-flops, and only a single input signal, it may allow for improved symmetry between the A/D converters.
- capacitors can be scaled relative to one another by some amount, e.g. in powers of two.
Abstract
Description
Claims (31)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/896,441 USRE42117E1 (en) | 2000-10-25 | 2007-08-31 | Apparatus for operating a CMOS imager having a pipelined analog to digital converter |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24332400P | 2000-10-25 | 2000-10-25 | |
US10/061,938 US6646583B1 (en) | 2000-10-25 | 2001-10-25 | High speed digital to analog converter using multiple staggered successive approximation cells |
US10/694,759 US6909392B2 (en) | 2000-10-25 | 2003-10-29 | Analog to digital converter using multiple staggered successive approximation cells |
US11/896,441 USRE42117E1 (en) | 2000-10-25 | 2007-08-31 | Apparatus for operating a CMOS imager having a pipelined analog to digital converter |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/694,759 Reissue US6909392B2 (en) | 2000-10-25 | 2003-10-29 | Analog to digital converter using multiple staggered successive approximation cells |
Publications (1)
Publication Number | Publication Date |
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USRE42117E1 true USRE42117E1 (en) | 2011-02-08 |
Family
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Family Applications (7)
Application Number | Title | Priority Date | Filing Date |
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US10/061,938 Expired - Lifetime US6646583B1 (en) | 2000-10-25 | 2001-10-25 | High speed digital to analog converter using multiple staggered successive approximation cells |
US10/694,759 Ceased US6909392B2 (en) | 2000-10-25 | 2003-10-29 | Analog to digital converter using multiple staggered successive approximation cells |
US11/812,785 Ceased USRE41519E1 (en) | 2000-10-25 | 2007-06-21 | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
US11/896,442 Expired - Lifetime USRE41730E1 (en) | 2000-10-25 | 2007-08-31 | Method for operating a CMOS imager having a pipelined analog to digital converter |
US11/896,441 Expired - Lifetime USRE42117E1 (en) | 2000-10-25 | 2007-08-31 | Apparatus for operating a CMOS imager having a pipelined analog to digital converter |
US13/357,118 Expired - Lifetime USRE45282E1 (en) | 2000-10-25 | 2012-01-24 | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
US13/532,165 Expired - Lifetime USRE45493E1 (en) | 2000-10-25 | 2012-06-25 | Analog to digital conversion for a CMOS imager |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
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US10/061,938 Expired - Lifetime US6646583B1 (en) | 2000-10-25 | 2001-10-25 | High speed digital to analog converter using multiple staggered successive approximation cells |
US10/694,759 Ceased US6909392B2 (en) | 2000-10-25 | 2003-10-29 | Analog to digital converter using multiple staggered successive approximation cells |
US11/812,785 Ceased USRE41519E1 (en) | 2000-10-25 | 2007-06-21 | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
US11/896,442 Expired - Lifetime USRE41730E1 (en) | 2000-10-25 | 2007-08-31 | Method for operating a CMOS imager having a pipelined analog to digital converter |
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US13/357,118 Expired - Lifetime USRE45282E1 (en) | 2000-10-25 | 2012-01-24 | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
US13/532,165 Expired - Lifetime USRE45493E1 (en) | 2000-10-25 | 2012-06-25 | Analog to digital conversion for a CMOS imager |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE45282E1 (en) * | 2000-10-25 | 2014-12-09 | Round Rock Research, Llc | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
Families Citing this family (16)
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US6787752B2 (en) * | 2001-07-19 | 2004-09-07 | Micron Technology, Inc. | Pseudorandom assignment between elements of the image processor and the A/D converter cells |
US7068319B2 (en) * | 2002-02-01 | 2006-06-27 | Micron Technology, Inc. | CMOS image sensor with a low-power architecture |
US7274321B2 (en) * | 2005-03-21 | 2007-09-25 | Analog Devices, Inc. | Analog to digital converter |
US7042382B1 (en) * | 2005-05-19 | 2006-05-09 | The United States Of America As Represented By The Secretary Of The Navy | Method of time synchronization of multiple A/D sample data records |
US7218259B2 (en) * | 2005-08-12 | 2007-05-15 | Analog Devices, Inc. | Analog-to-digital converter with signal-to-noise ratio enhancement |
JP4996323B2 (en) * | 2007-04-27 | 2012-08-08 | 株式会社東芝 | Two-dimensional digital data acquisition element and holographic storage device |
DE102007043145B4 (en) * | 2007-09-11 | 2011-12-08 | Texas Instruments Deutschland Gmbh | Method and device for controlling a successive approximation analog-to-digital converter |
JP4900200B2 (en) * | 2007-11-15 | 2012-03-21 | ソニー株式会社 | Solid-state imaging device and camera system |
EP2388923B1 (en) * | 2010-05-21 | 2013-12-04 | Stichting IMEC Nederland | Asynchronous digital slope analog-to-digital converter and method thereof |
US8755460B2 (en) | 2010-07-30 | 2014-06-17 | National Instruments Corporation | Phase aligned sampling of multiple data channels using a successive approximation register converter |
US8560592B2 (en) | 2010-07-30 | 2013-10-15 | National Instruments Corporation | Performing multiplication for a multi-channel notch rejection filter |
US9002917B2 (en) | 2010-07-30 | 2015-04-07 | National Instruments Corporation | Generating filter coefficients for a multi-channel notch rejection filter |
US8237598B2 (en) | 2010-07-30 | 2012-08-07 | National Instruments Corporation | Sampling of multiple data channels using a successive approximation register converter |
US8462240B2 (en) | 2010-09-15 | 2013-06-11 | Aptina Imaging Corporation | Imaging systems with column randomizing circuits |
JP5806539B2 (en) * | 2011-07-22 | 2015-11-10 | ルネサスエレクトロニクス株式会社 | Solid-state imaging device |
US10291251B1 (en) * | 2018-09-21 | 2019-05-14 | Semiconductor Components Industries, Llc | Imaging systems with sub-radix-2 charge sharing successive approximation register (SAR) analog-to-digital converters |
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-
2007
- 2007-06-21 US US11/812,785 patent/USRE41519E1/en not_active Ceased
- 2007-08-31 US US11/896,442 patent/USRE41730E1/en not_active Expired - Lifetime
- 2007-08-31 US US11/896,441 patent/USRE42117E1/en not_active Expired - Lifetime
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2012
- 2012-01-24 US US13/357,118 patent/USRE45282E1/en not_active Expired - Lifetime
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE45282E1 (en) * | 2000-10-25 | 2014-12-09 | Round Rock Research, Llc | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter |
USRE45493E1 (en) | 2000-10-25 | 2015-04-28 | Round Rock Research, Llc | Analog to digital conversion for a CMOS imager |
Also Published As
Publication number | Publication date |
---|---|
USRE41730E1 (en) | 2010-09-21 |
US6909392B2 (en) | 2005-06-21 |
US20040085237A1 (en) | 2004-05-06 |
USRE41519E1 (en) | 2010-08-17 |
US6646583B1 (en) | 2003-11-11 |
USRE45282E1 (en) | 2014-12-09 |
USRE45493E1 (en) | 2015-04-28 |
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