|Publication number||USRE40317 E1|
|Application number||US 09/815,873|
|Publication date||13 May 2008|
|Filing date||22 Mar 2001|
|Priority date||30 Dec 1991|
|Also published as||US5887196|
|Publication number||09815873, 815873, US RE40317 E1, US RE40317E1, US-E1-RE40317, USRE40317 E1, USRE40317E1|
|Inventors||Steven G. Roskowski, Dean M. Drako, William T. Krein|
|Original Assignee||Apple Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (53), Non-Patent Citations (1), Referenced by (1), Classifications (12), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 07/815,696, filed Dec. 30, 1991 now abandoned.
1. Field of the Invention
This invention relates to computer circuitry and, more particularly, to methods and apparatus for increasing the speed with which information is transferred between a source of data and a destination which is to use that data.
2. History of the Prior Art
A computer is typically constructed of a number of components which cooperate with each other to manage information. For example, a typical computer includes a central processing unit which includes circuitry for controlling the manipulation of data, a main memory in which data and instructions are typically stored during the operation of a computer program, a frame buffer in which data is stored for display, various input/output devices, and an output monitor. It is typical of most computer operations that information is constantly being transferred from one of these components to another during the operation of the computer by means of a bus which joins all of the devices.
Often the various individual components used with a computer system operate independently in carrying out operations in order to speed the overall operation of the computer system. In order to accomplish this, the individual components often have their own clocking arrangements to precisely time their internal operations. Examples of such components are those which include their own internal processors such as floating point processors and graphics accelerators. When information is transferred from one such component to another in prior art systems, the information which is synchronized to the clock of the sending component must be synchronized to the clock of the receiving component so that it can be correctly interpreted and used by the second component. To accomplish this, data is typically stored in word length increments in some form of memory at the source component and transferred a word at a time at the clock rate of the source component. At the interface between the source and the destination components, each word of information is synchronized with the clock of the destination component by an operation that typically requires two clock cycles. Once the information has been synchronized to the clock of the destination component, it is available for use by the destination component. Synchronization must take place each time information is transferred from a component which operates on one clock to a component which operates on another. Consequently, where the information is transferred between asynchronous components by a bus which operates at a different clock frequency than either the source or the destination component, two individual synchronization operations must take place.
As computers have become more capable, it has become desirable to transfer more information faster between components of the system. Moreover, it is just as desirable that the individual components operate at their own optimum internal clock rates so that each may carry out its functions most rapidly. The synchronization of information to the clock of the destination component and the storage of the information during transfer between components consumes a substantial portion of the time required for the operation of a computer. It, therefore, becomes desirable to be able to provide some means for synchronizing the transfer of information between a large number of asynchronously operating components. The typical prior art computer has provided ad hoc synchronizing arrangements at each interface between two asynchronous devices. No simple arrangement for accomplishing synchronization between more than two components has yet been devised.
It is, therefore, an object of the present invention to accelerate the operation of computer systems.
It is another more specific object of the present invention to accelerate the transfer of information across computer interfaces.
It is yet another object of the present invention to accelerate the transfer of information across a computer interface by reducing the time required for the synchronization and storage of data.
It is still another object of the present invention to provide an arrangement for accelerating the transfer of information across a plurality of computer interfaces while reducing the time required for individual synchronization operations.
These and other objects of the present invention are realized in a computer system which comprises a first component having a first clock, means for storing information, means for transferring information from the first component to the means for storing information utilizing the clock of the first component, a second component having a second clock, and means for utilizing the clock of the second component to transfer information from the storage of the first component in a condition in which it is synchronized for use by the second component and may be immediately utilized by the second component without the need for storage by the second component.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
Some portions of the detailed descriptions which follow may be presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to apparatus for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
Referring now to
Quite often in the design of a computer system, certain of the components will for one reason or another operate at different clock rates and will have different internal clock generators for providing the clock pulses used within the components. Typically, for example, a central processing unit 12 and a graphics accelerator 16 using an internal processor will each have its own clock. It is always necessary when transferring signals across an interface between two system components which operate at different clock frequencies that the incoming signals which are synchronized to the clock of the source component be synchronized to the clock of the destination component so that the information may be properly interpreted by the destination component.
Typically each word of information which is transferred between components is synchronized as it is transferred. This is a time consuming operation. This is usually accomplished by placing the word to be transferred in a register and simultaneously synchronizing a single bit of the word through a handshake line. The single bit is transferred on the handshake line while the remaining bits of the word are transferred on the data bus. Each handshake line (see
It will be recognized that this form of synchronization is quite time consuming since it requires an average of two clock cycles and must by done for each word transferred between system components. However, this is the typical synchronization method used in prior art arrangements for accomplishing the transfer of data between asynchronous components.
It has now been found possible to eliminate a substantial amount of the time required to accomplish synchronization when transferring information between two asynchronous system components. The manner in which this is accomplished requires that information be transferred between system components in groups of words rather than as single words. In a preferred embodiment of the invention, information is transferred from the source component using the source clock and accumulated in a buffer holding up to sixty-four bytes of data before any information is transferred to the destination component. Other sizes of buffers would, of course, be possible. When a selected amount of information has accumulated and the transfer to the buffer is complete, a signal is sent to the destination component in synchronization with the clock of the source component. This signal is synchronized to the clock of the destination component in the typical fashion described above and requires the typical time to synchronize and transfer. However, the signal indicates to the destination component that the information has all been gathered in the buffer and that no operation is presently taking place with regard to that information. Since the receipt of the synchronization signal by the destination component indicates that the clock of the source component is not active with regard to the information in the buffer, it allows the clock of the destination component to be switched to the clock input terminals of the buffer which previously received the clock of the source component while storing the data.
The information is then transferred from the buffer of the source component for use by the destination component without any synchronization being necessary to the transfer. The information is simply clocked out by the clock of the destination component and is automatically synchronized to the destination component. Thus, the only synchronization necessary in the entire transfer is the synchronization of the signal which indicates to the destination component that the data is ready in the buffer for transmission. No word by word synchronization of any sort is required. This substantially reduces the time required to transfer data between two components running on different clocks.
Not only does the transfer of information in this manner substantially reduce the synchronization time required, it also reduces the amount of system hardware and the number of steps necessary to move information. More particularly, if the information is stored using the clock of the source system component but moved out of the buffer in response to the clock of the destination system component, the buffer may be treated as a buffer of the destination component when the information is moved out. Because of this, the destination component need not store the information in a second internal buffer before it can be used. The information is immediately usable and may be used as it is clocked out of the buffer by the destination component. This has the effect of making the buffer first a part of the source component and then a part of the destination component and reducing the buffering circuitry by half. Thus, in addition to the time saved by using batch synchronization rather than per word synchronization, the time that would have been necessary to place the information in a second buffer and read it out for use is also saved.
Moreover, while prior art systems have required that ad hoc synchronization be accomplished at each individual interface, the present arrangement is especially adapted to allow the synchronization of a large number of asynchronous components. By storing information to be transferred in packets at a buffer of a source component and broadcasting a signal that the information is ready on a broadcast bus to a plurality of destination components, any of those destination components may synchronize to the broadcast signal and accept the information. This transfer of information is made easy and very rapid because any destination component need only furnish its clock to the source buffer and the information in the packet is automatically synchronized to the clock of the accepting destination. Thus, a very simple system is able to synchronize a plurality of asynchronous components.
In order to accomplish this result, a buffer 26 is provided. In
When the buffer 26 has been filled with the information to be transferred, the component 23 generates a signal from a register 28 indicating that there is information ready to be transferred to the component 24. This signal is placed at the D input terminal of a first synchronizing flip-flop 30 which is clocked as described above by the clock of the destination component 24. The output of the D flip-flop 30 is transferred to a second D flip-flop 32 which is also clocked by the clock of the destination component 24. The output of the second D flip-flop 32 is synchronized to the clock of the component 24 and thus may be read by the destination component 24 as indicating that there is information in the buffer 26 waiting to be transferred to the component 24. The signal also indicates that no information is being clocked into the buffer 26 by the component 23 and that the synchronization circuitry is not in use.
This being the case, a valid signal is transferred from the component 24 to operate the multiplexor 27 so that the clock of the component 24 is transferred by the multiplexor 27 to clock the information stored in the buffer 26 to the component 24 for use. At the same time, the D flip-flops 30 and 32 are furnished a clearing signal at a reset terminal by the component 24 so that they may be utilized for the next synchronization required for the transfer of information.
It will be realized by those skilled in the art that the information furnished from the buffer 26 is automatically synchronized to the clock of the component 24 without the necessity of synchronizing any individual word of the information through two flip-flop stages, let alone all of the words gathered in the buffer 26. This saves a substantial amount of time in the transfer of information. Moreover, the information clocked out of the buffer 26 is ready for use immediately by the component 24. Consequently, the buffer 26 which was initially a logical part of the component 23 has become, in effect, a buffer of the component 24, furnishing information to the elements of the component 24. This both saves the necessity of storing the information somewhere in the component 24 before it can be used and saves the time for so storing the information and retrieving it.
To transfer information from the second component 24 to the first component 23 requires that similar circuitry be utilized to provide buffering for the second component 24, to signal that information is ready to be transferred, and to switch the clock of the first component 23 to drive the transfer of information from the buffer of the second component 24. This might utilize some or all of the same circuitry as did the transfer from the component 23.
Associated with the buffer 46 is a launch or broadcast bus 47. Each of the components 41-44 is connected to the launch bus so that when it has completed the transfer of information to storage in the buffer 46, it may place an address on the launch bus 47 indicating that the transfer to the buffer 46 is complete and giving the address of the destination device. Each of the components 41-44 using a circuit 48 synchronizes the signal (at least one bit of the signal) placed on the launch bus 47 with its clock (the clock of the addressed component). Each of the components 41-44 receives and decodes the address. When the addressed component is ready to receive the information, the addressed component returns a gate signal and its clock to a multiplexor 49 of the buffer 46. The multiplexor 49 transfers the clock from the addressed component to a counter 51 which controls the transfer of the information to the addressed component 41-44. In this manner, the information is written to the destination component under control of the destination clock and is immediately available for use by the destination component as in the arrangement shown in FIG. 3.
The multiplexor 49 illustrated in
Thus, a plurality of asynchronous components may all be arranged with a simple and rapid synchronization system which allows any one of the components to receive the information from any other source component. The packetizing of information and the use of a broadcast bus to send signals from a source to which a plurality of destinations may synchronize, greatly enhances the speed of a computer system and makes possible the transfer of very large amounts of information.
Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3109162 *||15 Jan 1959||29 Oct 1963||Ibm||Data boundary cross-over and/or advance data access system|
|US4145755 *||15 Oct 1976||20 Mar 1979||Tokyo Shibaura Electric Co., Ltd.||Information transferring apparatus|
|US4276611 *||16 Apr 1979||30 Jun 1981||U.S. Philips Corporation||Device for the control of data flows|
|US4402040 *||24 Sep 1980||30 Aug 1983||Raytheon Company||Distributed bus arbitration method and apparatus|
|US4413258 *||14 Dec 1981||1 Nov 1983||Burroughs Corporation||Interconnection for local area contention networks|
|US4423480 *||6 Mar 1981||27 Dec 1983||International Business Machines Corporation||Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations|
|US4525849 *||23 Mar 1983||25 Jun 1985||Siemens Aktiengesellschaft||Data transmission facility between two asynchronously controlled data processing systems with a buffer memory|
|US4527233 *||26 Jul 1982||2 Jul 1985||Ambrosius Iii William H||Addressable buffer circuit with address incrementer independently clocked by host computer and external storage device controller|
|US4542457 *||11 Jan 1983||17 Sep 1985||Burroughs Corporation||Burst mode data block transfer system|
|US4620278 *||29 Aug 1983||28 Oct 1986||Sperry Corporation||Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus|
|US4621342 *||1 Feb 1984||4 Nov 1986||Cselt Centro Studi E Laboratori Telecomunicazioni S.P.A.||Arbitration circuitry for deciding access requests from a multiplicity of components|
|US4638534 *||19 Sep 1985||27 Jan 1987||Honda Giken Kogyo Kabushiki Kaisha||Pivot structure for seat belt buckle|
|US4683534||17 Jun 1985||28 Jul 1987||Motorola, Inc.||Method and apparatus for interfacing buses of different sizes|
|US4766536 *||17 Feb 1987||23 Aug 1988||Rational||Computer bus apparatus with distributed arbitration|
|US4766538 *||10 Dec 1985||23 Aug 1988||Kabushiki Kaisha Toshiba||Microprocessor having variable data width|
|US4837682 *||7 Apr 1987||6 Jun 1989||Glen Culler & Associates||Bus arbitration system and method|
|US4860193 *||22 May 1986||22 Aug 1989||International Business Machines Corporation||System for efficiently transferring data between a high speed channel and a low speed I/O device|
|US4860244 *||7 Nov 1983||22 Aug 1989||Digital Equipment Corporation||Buffer system for input/output portion of digital data processing system|
|US4864496 *||4 Sep 1987||5 Sep 1989||Digital Equipment Corporation||Bus adapter module for interconnecting busses in a multibus computer system|
|US4878166 *||15 Dec 1987||31 Oct 1989||Advanced Micro Devices, Inc.||Direct memory access apparatus and methods for transferring data between buses having different performance characteristics|
|US4920486 *||23 Nov 1987||24 Apr 1990||Digital Equipment Corporation||Distributed arbitration apparatus and method for shared bus|
|US4924380 *||20 Jun 1988||8 May 1990||Modular Computer Systems, Inc. (Florida Corporation)||Dual rotating priority arbitration method for a multiprocessor memory bus|
|US4937733 *||1 May 1987||26 Jun 1990||Digital Equipment Corporation||Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system|
|US4939644 *||9 Jan 1987||3 Jul 1990||Data General Corporation||Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system|
|US4953081 *||21 Dec 1988||28 Aug 1990||International Business Machines Corporation||Least recently used arbiter with programmable high priority mode and performance monitor|
|US4956771 *||24 May 1988||11 Sep 1990||Prime Computer, Inc.||Method for inter-processor data transfer|
|US4965723 *||23 Oct 1987||23 Oct 1990||Digital Equipment Corporation||Bus data path control scheme|
|US5010325||19 Dec 1988||23 Apr 1991||Planar Systems, Inc.||Driving network for TFEL panel employing a video frame buffer|
|US5088024 *||31 Jan 1989||11 Feb 1992||Wisconsin Alumni Research Foundation||Round-robin protocol method for arbitrating access to a shared bus arbitration providing preference to lower priority units after bus access by a higher priority unit|
|US5097437 *||17 Jul 1988||17 Mar 1992||Larson Ronald J||Controller with clocking device controlling first and second state machine controller which generate different control signals for different set of devices|
|US5111424 *||23 Feb 1990||5 May 1992||Digital Equipment Corporation||Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer|
|US5113369 *||6 Sep 1989||12 May 1992||Kabushiki Kaisha Toshiba||32-bit personal computer using a bus width converter and a latch for interfacing with 8-bit and 16-bit microprocessors|
|US5151994 *||22 Oct 1991||29 Sep 1992||Hewlett Packard Company||Distributed fair arbitration system using separate grant and request lines for providing access to data communication bus|
|US5167019 *||23 Jun 1989||24 Nov 1992||Digital Equipment Corporation||Apparatus and method for interconnecting a plurality of devices to a single node in a node-limited serial data bus computer network|
|US5179557 *||2 Jul 1990||12 Jan 1993||Kabushiki Kaisha Toshiba||Data packet communication system in which data packet transmittal is prioritized with queues having respective assigned priorities and frequency weighted counting of queue wait time|
|US5191653 *||28 Dec 1990||2 Mar 1993||Apple Computer, Inc.||Io adapter for system and io buses having different protocols and speeds|
|US5193149 *||8 Oct 1991||9 Mar 1993||Digital Equipment Corporation||Dual-path computer interconnect system with four-ported packet memory control|
|US5193197 *||30 Aug 1990||9 Mar 1993||Digital Equipment Corporation||Apparatus and method for distributed dynamic priority arbitration for access to a shared resource|
|US5204676 *||16 Dec 1991||20 Apr 1993||U.S. Philips Corporation||Circuit arrangement for frequency conversion of a digital signal|
|US5210829 *||12 Dec 1990||11 May 1993||Digital Equipment Corporation||Adjustable threshold for buffer management|
|US5218676 *||8 Jan 1990||8 Jun 1993||The University Of Rochester||Dynamic routing system for a multinode communications network|
|US5220653 *||26 Oct 1990||15 Jun 1993||International Business Machines Corporation||Scheduling input/output operations in multitasking systems|
|US5222223 *||3 Feb 1989||22 Jun 1993||Digital Equipment Corporation||Method and apparatus for ordering and queueing multiple memory requests|
|US5265215 *||17 Apr 1992||23 Nov 1993||International Business Machines Corporation||Multiprocessor system and interrupt arbiter thereof|
|US5291468 *||16 Sep 1991||1 Mar 1994||International Business Machines Corporation||Method and apparatus for synchronizing the readout of a sequential media device with a separate clocked device|
|US5452436 *||3 Jan 1995||19 Sep 1995||Hitachi, Ltd.||System for connecting plurality of electronic units to data and clock buses wherein transmitting and receiving data in synchronization with transmitting and receiving clock signals|
|EP0038189A1 *||10 Apr 1981||21 Oct 1981||Sperry Corporation||Priority scheduling apparatus|
|EP0121030A1||29 Mar 1983||10 Oct 1984||International Business Machines Corporation||Arbitration device for the allocation of a common resource to a selected unit of a data processing system|
|EP0127007A2||3 May 1984||5 Dec 1984||International Business Machines Corporation||Data processing interface apparatus|
|EP0141742A2 *||31 Oct 1984||15 May 1985||Digital Equipment Corporation||Buffer system for input/output portion of digital data processing system|
|EP0240749A2||7 Mar 1987||14 Oct 1987||Symbolics, Inc.||Disk controller bus interface|
|GB2256563A *||Title not available|
|JPH01246664A *||Title not available|
|1||*||Alok N. Choudhary, et al. "A Modified Priority Based Probe Algorithm for Distributed Deadlock Detection and Resolution", pp. 10-18, IEEE vol. 15, No. 1, Jan. 1989.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20070214337 *||1 Mar 2007||13 Sep 2007||Hiroshi Takeda||Data transfer control method, and peripheral circuit, data processor and data processing system for the method|
|U.S. Classification||710/51, 710/112, 710/55, 710/33, 710/29, 710/3, 375/372, 710/38|
|International Classification||G06F13/42, G06F13/00|
|5 Aug 2008||CC||Certificate of correction|
|26 Aug 2010||FPAY||Fee payment|
Year of fee payment: 12