|Publication number||USRE38821 E1|
|Application number||US 09/903,808|
|Publication date||11 Oct 2005|
|Filing date||12 Jul 2001|
|Priority date||31 Jan 1996|
|Also published as||US5923660, USRE39514|
|Publication number||09903808, 903808, US RE38821 E1, US RE38821E1, US-E1-RE38821, USRE38821 E1, USRE38821E1|
|Inventors||David Shemla, Avigdor Willenz|
|Original Assignee||Marvell Semiconductor Israel Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (47), Non-Patent Citations (5), Referenced by (7), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,923,660. The reissue applications are U.S. application Nos. 09/903,808 (the present application) and 10/872,147, filed Jun. 21, 2004, which is a continuation reissue of the present application.
The present invention relates to network switches generally and to switching Ethernet controllers in particular.
A network switch creates a network among a plurality of end nodes, such as workstations, and other network switches connected thereto. Each end node is connected to one port of the network. The ports also serve to connect network switches together.
Each end node sends packets of data to the network switch which the switch then routes either to another of the end nodes connected thereto or to a network switch to which the destination end node is connected. In the latter case, the receiving network switch routes the packet to the destination end node.
Each network switch has to temporarily store the packets of data which it receives from the units (end node or network switch) connected to it while the switch determines how, when and through which port to retransmit the packets. Each packet can be transmitted to only one destination address (a “unicast” packet) or to more than one unit (a “multicast” or “broadcast” packet). For multicast and broadcast packets, the switch typically stores the packet only once and transmits multiple copies of the packet to some (multicast) or all (broadcast) of its ports. Once the packet has been transmitted to all of its destinations, it can be removed from the memory or written over.
Switching Ethernet controllers are network switches that implement the Ethernet switching protocol. According to the protocol, the Ethernet network (cabling and Ethernet ports) operates at 10 Megabits per second. However, most switches do not operate at that speed, since they require longer than the 10 Mbps to process the incoming packets. Thus, their throughput is less than 10 Mbps. Switches which do operate at the desired speed are known as providing “full-wire” throughput.
It is an object of the present invention to provide an improved switching Ethernet controller (SEC) which provides full-wire throughput.
The SEC of the present invention achieves the high-speed operation by utilizing a plurality of elements whose operations are faster than those of the prior art.
For example, in accordance with a preferred embodiment of the present invention, the communication between SECs attempts to utilize the bus as little as possible so that the bus will be available as soon as an SEC wants to utilize it. In accordance with the present invention, each SEC includes a write-only bus communication unit which transfers the packets out of the SEC by utilizing the bus only for write operations. Thus, packets enter each SEC by having been written therein from other SECs and not by reading them in, since read operations utilize the bus for significant amounts of time compared to write operations. Having the bus available generally whenever a SEC needs it helps to provide the full-wire throughput.
In addition, the address table controller operates with a hash table storing addresses of the ports within the Ethernet network. The controller hashes the address of a packet to an initial hash table location value and then accesses that table location. If the address stored at the table location matches that of the input address, the port information is retrieved. However, if the address stored at the table location is other than that of the input address, rather than reading a pointer to the next location where values corresponding to the same hashed address can be found (as in the prior art), the present invention changes the hash table location values by a fixed jump amount and reads the address stored at the next table address. Due to the fixed jump amount, the hash table controller of the present invention always knows what the next possible table location is.
A further speed increase is found in the accessing of the temporarily stored packets. In the present invention, the packets are stored in a storage buffer including a multiplicity of contiguous buffers. Associated with the buffers is an empty list including a multiplicity of single bit buffers. A packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer through a simple function of the address or number of its associated single bit buffer. The simple function is typically a multiplication operation.
The present invention also incorporates a network of SECs interconnected with PCI busses.
Finally, there is provided, in accordance with a preferred embodiment of the present invention, an Ethernet network including a) at least two groups of network switches, b) at least two PCI switch busses, wherein each group of network switches is connected to one of the PCI busses, c) at least two PCI-to-PCI bridges, wherein each PCI-to-PCI bridge is connected to one of the PCI switch busses and d) at least one interconnection PCI bus to which the PCI-to-PCI bridges are connected.
The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:
Reference is now made to
The frame control unit 32 typically includes input and output multiple first-in, first-out (FIFO) buffers 40 and 42, respectively, a direct memory access (DMA) unit 44 and a descriptor control 46. The FIFO buffers 40 and 42 each have one FIFO buffer per port defined by the Ethernet interface unit 30. The descriptor control 46 controls 9 circular (or ring) transmit queues which are stored in the DRAM 20. Each queue lists the packets to be transmitted through one of the eight ports or through the PCI bus 14. The descriptor control 46 maintains read and write pointers for each queue so as to know which packets are still waiting to be transmitted.
For incoming packets, input FIFO buffer 40 receives and buffers packets from the ports. The DMA unit 44 transfers the currently available packet provided by the input FIFO buffer 40 to the DRAM 20 in accordance with the instructions from the switching unit 34. After the packet has been properly received, the switching unit 34 indicates to the descriptor control 46 through which port to transfer the packet. The descriptor control 46 places information about the packet into the relevant transmit queue and, when the packet rises to the top of the transmit queue, the descriptor control 46 indicates to the DMA 44 to transfer the packet from the DRAM 20 to the buffer in output FIFO 42 for the appropriate port.
The switching unit 34 typically includes an empty list block 50, a hash table address control unit 52, an arbiter 54 and a DRAM interface 56. The empty list block 50 manages the organization of the DRAM 20, noting which buffers of the DRAM 20 are available for storing newly arrived packets and which buffers contain packets to be transferred out. As will be described in more detail hereinbelow, the empty list block 50 associates an empty list of single bit buffers with the buffers of the DRAM 20. In addition, the empty list block 50 associates the state of the bit of a single bit buffer with the empty or full state of an associated DRAM buffer and generates the address of a DRAM buffer through a simple function of the address or number of its associated single bit buffer. The simple function is typically a multiplication operation. Thus, when a buffer request is received, the empty list block 50 relatively quickly can determine the address of the next available buffer.
When the empty list block 50 receives buffer assignment requests from the DMA 44 or from the inter SEC control unit 36, the empty list block 50 assigns the currently available buffer based on the state of the single bits of the empty list. Similarly, on output, when the empty list block 50 receives notification from the descriptor control 46 of the buffers which have successfully been either placed into the output FIFO 42 or transferred to another SEC (via the inter SEC control unit 36), the empty list block 50 then updates the state of the associated single bit buffer.
The hash table address control unit 52 receives the source and destination address information of the packet header from the Ethernet interface unit 30. As will be described in more detail hereinbelow, control unit 52 operates in conjunction with a hash table (physically found in DRAM 20) of the possible addresses of the entire network. The control unit 52 hashes the address of a packet to an initial hash table location value and then accesses that table location. If the address stored at the table location matches that of the input address, the port information is retrieved. However, if the address stored at the table location is other than that of the input address, the present invention changes the hash table location values by a fixed jump amount and reads the address stored at the next table address. Due to the fixed jump amount, the hash table controller of the present invention always knows what the next possible table location is for the current hash value and thus, can generally quickly move through the hash table to match the input address and to produce the associated port number.
Arbiter 54 controls the access to the DRAM 20 and DRAM interface 56 accesses the DRAM 20 for each piece of data (a packet or an address in the hash table) being stored or removed. Arbiter 54 receives DRAM access requests from the hash table control unit 52, the DMA unit 44, the descriptor control unit 46 and the inter SEC control unit 36.
The hash table control unit 52 provides the port associated with the destination address of the incoming packet to the descriptor control 46. Similarly, the empty list block 50 provides the descriptor control 46 with the buffer number in which the incoming packet is stored. When both values are received and the packet has been properly received (that is, without any corrupted data), the descriptor control 46 places the received buffer information in the transmit queue for the received buffer number and, at the appropriate moment, initiates the transfer of the packet from the DRAM 20 into the queue of output FIFO 42 for the appropriate port. A slightly different operation occurs for the PCI transmit queue, as will be described hereinbelow.
The inter SEC control unit 36 typically includes a PCI DMA 60, a write-only transfer manager 62 and three interrupt registers, buffer request register 64, start of packet register 66 and end of packet register 68. The transfer manager 62 supervises the transfer protocol which, in accordance with a preferred embodiment of the present invention, is performed with only write operations. As discussed hereinabove, write operations utilize the bus 14 for relatively short periods of time only.
The descriptor control 46 activates the write only transfer manager 62 whenever there is buffer information in the PCI transmit queue for a packet which has not been transmitted. The descriptor control 46 provides the transfer manager 62 with the buffer address of the packet to be transferred and the port number of the destination SEC 10 to which the destination end node is attached.
To begin the transfer, the transfer manager 62 first prepares a “buffer request” message and writes the message into the buffer request register 64 of the destination SEC 10. Typically the buffer request includes at least the address of the buffer storing the packet to be transferred and the port number of the destination SEC 10 to which the destination end node is attached.
The presence of a message in register 64 causes the transfer manager 62 of the destination SEC 10 to request that the empty list block 50 allocate a buffer in the DRAM 20 for the packet to be transferred. The empty list block 50 reviews its empty list (without reading anything from the DRAM 20) and allocates the next available buffer (by changing the state of the bit associated with the buffer) to the packet to be transferred. The empty list block 50 provides the address of the allocated buffer to the transfer manager 62 which prepares a “start of packet” message with the address of the allocated buffer. The transfer manager 62 of the destination SEC 10 then writes the “start of packet” message to the start of packet register 66 of the source SEC 10. Typically, the “start of packet” message includes at least the address of the allocated buffer (in the destination SEC 10), the address of the buffer (in the source SEC 10) storing the packet to be transferred and the port number of the destination end node.
The presence of a message in the start of packet register 66 causes the transfer manager 62, of the source SEC 10, to activate the PCI DMA 60 to write the contents of the buffer storing the packet to be transferred in the allocated buffer in the destination SEC 10. The PCI DMA 60 of the source SEC 10 actually writes the packet to the PCI DMA 60 of the destination SEC 10 which, in turn, writes the transferred packet to the allocated buffer of its DRAM 20 after receiving permission from its arbiter 54. The transfer manager 62 also prepares an “end of packet” message and then writes the message into the end of packet register 68 once the packet to be transferred has been successfully transferred. Finally, the transfer manager 62 indicates to the empty list block 50 to clear the bit of the empty list which is associated with the transferred packet. The “end of packet” message includes at least the destination port number.
The transfer manager 62 of the destination SEC 10 responds to the “end of packet” message by providing its descriptor control 46 with the port and buffer numbers of the transferred packet. The descriptor control 46 then adds the buffer information to the transmit queue for the indicated port. The packet is then transferred to the port as described hereinabove.
The following describe the empty list block 50, the hash table control unit 52 and the write-only transfer protocol in more detail.
Reference is now made to
In accordance with the present invention, the buffer 112 comprises a multiplicity of contiguous buffers 122, each of M bits and large enough to store, for example, at least one packet of 1518 bytes. For example, M might be 1.5K or 1536 bytes. Alternatively, each buffer 122 might hold many packets.
Furthermore, in accordance with a preferred embodiment of the present invention, the empty list 110 is a buffer of single (0 or 1) bits 124, each associated with one of the buffers 122.
Buffers 124 store the value of 1 when their associated buffer 122 stores a not-yet retransmitted packet and a 0 when their associated buffer 122 is free to be written into. The buffers 122 and bits 124 are associated as follows: the address of the beginning of a buffer 122 is M times the address (or number) of the single bit buffer 124 associated therewith. In other words, for M=1.5K, the buffer 122 labeled 3 begins at address 4.5K and the buffer 122 labeled 0 begins at address 0. Alternatively, the first buffer 122 can begin at an offset K and thus, the address of the beginning of a buffer i is M times the address of the single bit buffer 124 associated therewith plus the offset K.
The empty list block 50 operates as follows: when a port 120 provides a packet, the DMA 44 requests the number of the next available buffer 122 from the empty list controller 114. Empty list controller 114 reviews the empty list 110 for the next available single bit buffer 124 whose bit has a 0 value. Empty list controller 114 then changes the bit value to 1, multiplies the address of next available buffer 124 by M (and adds an offset K if there is one) and provides the resultant address, which is the start location of the corresponding buffer 122, to DMA 44.
It will be appreciated that the empty list block 50 provides a very simple mechanism by which to determine and store the address of the next available buffer 122. The mechanism only requires one multiplication operation to determine the address and the address value is stored as a single bit (the value of buffer 124), rather than as a multiple bit address.
DMA 44 then enters the data from the incoming packet into the selected buffer 122. Once DMA 44 has finished entering the data, it indicates such to the hash table address control unit 52 which in the meantime, has received the destination and source end node addresses from the Ethernet unit 30. Unit 52 determines through which port to retransmit the packet. Empty list controller 114 provides unit 52 with the number of the buffer 122 in which the packet is stored.
When a packet is to be retransmitted, the empty list controller 114 provides the DMA 44 with the buffer address for the packet and the hash table address control 52 provides the DMA 44 with the port number. DMA 44 reads the data from the buffer 122 and provides the packet to the FIFO buffer for the relevant port 120.
For unicast packets, once the DMA 44 has finished transmitting the data of the selected buffer 122, DMA 44 indicates such to empty list controller 114 and includes in the indication the beginning address of the selected buffer 122. Empty list controller 114 then determines the buffer number of the selected buffer 122 and changes the bit value of the associated single bit buffer 124 to 0, thereby indicating that the selected buffer 122 is now available.
Buffers 122 are larger by at least N bits than the maximum amount of data to be stored therein. N is the number of ports connected to the switch plus the number of switches connected to the current switch. For example, N might be 46. The extra bits, labeled 132, are utilized, for multicast packets, to indicate the multiple ports through which the packet has to be transmitted.
When the multicast packet enters the switch, DMA 44 sets all of the bits 132 (since multicast packets are to be sent to everyone). After the DMA 44 has transmitted a packet, whose port number it receives from the address control 52, the DMA 44 indicates such to the empty list controller 114. If the packet is a multicast packet, the address control unit 52 indicates to the empty list controller 114 to read the N bits 132 to determine if any of them are set. If they are, empty list controller 114 indicates to DMA 44 to reset the bit associated with the port 120 through which the packet was sent. When the DMA 44 indicates that it has finished resetting the bit, the empty list controller 114 does not change the associated single bit buffer 124.
If the empty list controller 114 reads that only one bit is still set (i.e. the previous transmission was the last time the packet had to be transmitted), when the DMA 44 indicates that it has finished resetting the bit, the empty list controller 114 changes the bit value of the associated single bit buffer 124 to 0, thereby indicating that the associated buffer 122 is now available.
In the empty list 110, bits typically change as data is received and transmitted. However, it is possible for data not to be transmitted if there are some errors in the network, such as a port being broken or a switch being removed from the network. In any of these cases, the bits in the empty list 110 associated with those ports must be cleared or else the associated buffers 122 will never be rewritten.
Therefore, the present invention includes bit clearing mechanism 121 which reviews the activity of the bits in the single bit buffers 124 and clears any set bits (i.e. of value 1) which have not changed during a predetermined period T. The period T is typically set to be small enough to avoid wasting storage space for too long but large enough to avoid clearing a buffer before its turn for transmission has occurred.
Bit clearing mechanism 121 comprises a multiplexer 140 and a state reviewer 142. The multiplexer 140 connects, at one time, to a group of single bit buffers 124 and switches between groups of buffers every period T. State reviewer 142 reviews the state of the group of single bit buffers 124 to determine if all of the single bit buffers 124 changed from 1 to 0 at least once during the period T. If, at the end of period T, one or more bits in buffers 124 have remained in the set state (i.e. with value 1), the state reviewer 142 clears them to 0. Multiplexer 140 then connects to the next group of single bit buffers 124.
The operations of the bit clearing mechanism 121 are detailed in FIG. 4. Specifically, at each clock tick ti, the state reviewer 142 checks (step 150) each bit. If the bit has changed to 0, the bit is marked (step 152) as “changed”. Otherwise, nothing occurs. The process is repeated until the period T has ended (step 154).
At the end of the period T, the state reviewer 142 clears (step 156) any unchanged bits and the multiplexer 140 changes (step 158) the group. The process is repeated for the next time period T.
Reference is now made to
Hash table control unit 52 comprises a hash table 212 and a hash table location generator 214. Hash table 212 is shown with only 18 locations; it will be appreciated that this is for the purposes of clarity only. Typically, hash table 212 will have 32K locations therein and, in accordance with the present invention, stores only the MAC address and the port associated therewith.
Location generator 214 receives the MAC address, whether of the source end node or of the destination end node, and transforms that address, via a hash function, to a table location. The hash function can be any suitable hash function; one suitable function is provided hereinbelow with respect to FIG. 7.
In accordance with the present invention, if the generated table location stores an address which is not the same as the input MAC address, the location generator 214 generates a second location which is X locations further down in the hash table 212. The hash table does not store any pointers to the next location. In accordance with the present invention, X is a prime number such that, if it is necessary to move through the entire hash table 212, each location will be visited only once during the review.
For example, and as shown in
It will be appreciated that the hash table control unit 52 does not need to have pointers in table 212 pointing to the “next” location in the table. As a result, unit 52 knows, a priori, which locations in the table are next and can, accordingly, generate a group of locations upon receiving the MAC address. If desired, the data in the group of locations can be read at once and readily compared to the input MAC address.
The hash function generator 230 converts the MAC address MA, of 48 bits, to the table location TL0, of 15 bits. The DRAM interface 56 generates the group of next table locations TL0, TL1 and TL2, where TL1=TL0+X and TL2=TL0+2X, etc. It will be appreciated that
DRAM interface 56 accesses the table 212 to read the addresses, A0, A1 and A2, and their associated data d0, d1 and d2, stored in table locations TL0, TL1 and TL2, respectively. The data di include the necessary information about the address, such as the switch identification number and any other desired information. The read operation can be performed at once or successively.
The output of each table location is latched by latch 234. Comparator 236 then compares the address information Ai with that of MAC address MA. If the two addresses match (i.e. a “hit”), then comparator 236 indicates to latch 234 to output the associated data di stored therein. Otherwise, comparator 236 indicates to DRAM interface 56 to read the address Ai and associated data di stored in the next table location.
If many table locations are to be read at once, the location generator 214 can include a multiplicity of latches 234, one for each location to be read at once.
If one of the table locations is empty, as indicated by a valid bit of the data di, all locations after it will also be empty. Thus, the input MAC address has no corresponding stored address and therefore, the input MAC address is typically input into the empty table location. The valid bit in the associated data di is then set to ‘not empty’.
Hash function generator 230 comprises two XOR units 240A and 240B, a concatenator 242 and a swap unit 244. The XOR unit 240A performs an exclusive OR between bytes C and D and XOR unit 240B performs an exclusive OR between the output of XOR unit 240A and byte B. Concatenator 242 concatenates the output of XOR unit 240B with byte A, thereby producing variable T of 15 bits. Swap unit 244 swaps the bits of variable T to produce the output table location TL. Thus, the value of TL<14> receives the value of T<0>, the value of TL<13> receives that of T<1>, etc. It will be appreciated that any hash function can be utilized. However, the desired hash functions are those which provide a uniform distribution of table locations for the expected MAC addresses. It is noted that the above hash function is easily implemented in hardware since XOR units and concatenators are simple to implement.
Reference is now made to
In accordance with the write-only protocol of the present invention, packets of data are not transferred until a buffer location 319 is allocated for them in the DRAM 20 of the destination network switch 12B. Furthermore, since the transfer operation is a DMA transfer, a packet is directly written into the location allocated therefor.
In accordance with a preferred embodiment of the present invention, when a packet of data is to be transferred, the source network switch 12A initially writes (step 350,
In the DMA transfer embodiment of the present invention, the source network switch 12A provides, on address line 342, the address of the “buffer request” register, the address of destination network switch 12B and its “return” address. Source network switch 12A provides, on data line 340, the size (or byte count) of the packet to be transferred and the buffer location 319A in which it is stored. The data of the data line is then written directly into the buffer request register.
In response to the buffer request message, the destination network switch 12B determines (step 352) the buffer location 319B in which the packet can be stored. It then writes (step 354) a “start of packet” message to the start of packet register 66a of the source network switch 12A which includes at least the location of the allocated buffer and the port numbers of the source and destination network switches. It can also include the byte count.
For example, in the DMA transfer embodiment of the present invention described hereinabove, the destination network switch 12B provides, on address line 342, the address of the “start of packet” register and the address of source network switch 12A. Destination network switch 12B provides, on data line 340, at least the following: the byte count of the packet to be transferred, the address 319B of the allocated buffer, the port number of the destination network switch 12B, and, for identification, the buffer location 319A in which the data is stored in the source network switch 12A and the port number of the source network switch 12A. As before, the data of the data line is then directly written into the start of packet register.
In response to receipt of the start of packet message in the start of packet register, the source network switch 12A writes (step 356) the packet of data to the allocated buffer location, followed by an “end of packet” message. Once the source network switch 12A has finished writing the end of packet message, it is free to send the next packet, beginning at step 350.
In the above described embodiment, the writing of the packet of data involves providing the address of the destination network switch 12B and the buffer location 319B on the address line 342 and the packet to be transferred on the data line 340. The transferred packet is then directly written into the allocated buffer location 319B. The end of packet message is written in a similar manner to the other messages, but to end of packet register 68b. The address information includes the address of the end of packet register and the address of the destination network switch 12B. The data includes the port number of the destination network switch 12B, the buffer location 319B and the byte count.
When the packet arrives at the destination network switch 12B it directly writes (step 360) the packet into the allocated buffer location 319B, as per the address on the address line 342, until it receives the end of packet message for that allocated buffer location. The destination network switch 12B is now free to perform other operations until it receives a next buffer allocation request.
It is also noted that, in the present invention, the source network switch 12A is free to operate on other packets once it has finished writing its packet, and its associated end of packet message, to the bus. The source network switch 12A does not need to ensure that the destination network switch 12B has successfully received the packet since, in the present invention, the address for the data (in the destination network switch) is known and is fully allocated prior to sending the packet; the packet would not be sent if there was no buffer location available for it. In the present invention, the time it takes for the destination network switch 12B to process the packet is not relevant to the operation of the source network switch 12A.
It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined by the claims which follow:
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4464713||17 Aug 1981||7 Aug 1984||International Business Machines Corporation||Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store|
|US4663706||14 Oct 1983||5 May 1987||Tandem Computers Incorporated||Multiprocessor multisystem communications network|
|US4680700 *||19 Dec 1986||14 Jul 1987||International Business Machines Corporation||Virtual memory address translation mechanism with combined hash address table and inverted page table|
|US4996663||2 Feb 1988||26 Feb 1991||Bell Communications Research, Inc.||Methods and apparatus for decontaminating hash tables|
|US5005121 *||20 Mar 1989||2 Apr 1991||Hitachi, Ltd.||Integrated CPU and DMA with shared executing unit|
|US5032987||11 May 1990||16 Jul 1991||Digital Equipment Corporation||System with a plurality of hash tables each using different adaptive hashing functions|
|US5101348||23 Jun 1988||31 Mar 1992||International Business Machines Corporation||Method of reducing the amount of information included in topology database update messages in a data communications network|
|US5222064||29 Jan 1991||22 Jun 1993||Mitsubishi Denki Kabushiki Kaisha||Bridge apparatus|
|US5226039 *||18 May 1990||6 Jul 1993||Kendall Square Research Corporation||Packet routing switch|
|US5274631 *||11 Mar 1991||28 Dec 1993||Kalpana, Inc.||Computer network switching system|
|US5287499||16 May 1991||15 Feb 1994||Bell Communications Research, Inc.||Methods and apparatus for information storage and retrieval utilizing a method of hashing and different collision avoidance schemes depending upon clustering in the hash table|
|US5307464 *||3 Dec 1990||26 Apr 1994||Hitachi, Ltd.||Microprocessor and method for setting up its peripheral functions|
|US5351299 *||4 Jun 1993||27 Sep 1994||Matsushita Electric Industrial Co., Ltd.||Apparatus and method for data encryption with block selection keys and data encryption keys|
|US5412805||3 Aug 1992||2 May 1995||International Business Machines Corporation||Apparatus and method for efficiently allocating memory to reconstruct a data structure|
|US5440552||19 Jan 1994||8 Aug 1995||Nec Corporation||ATM cell assembling/disassembling system|
|US5479628 *||12 Oct 1993||26 Dec 1995||Wang Laboratories, Inc.||Virtual address translation hardware assist circuit and method|
|US5521913||12 Sep 1994||28 May 1996||Amber Wave Systems, Inc.||Distributed processing ethernet switch with adaptive cut-through switching|
|US5563950 *||30 May 1995||8 Oct 1996||International Business Machines Corporation||System and methods for data encryption using public key cryptography|
|US5581757||20 Apr 1995||3 Dec 1996||Rolm Systems||Partially replicated database for a network of store-and-forward message systems|
|US5590320 *||14 Sep 1994||31 Dec 1996||Smart Storage, Inc.||Computer file directory system|
|US5623644 *||25 Aug 1994||22 Apr 1997||Intel Corporation||Point-to-point phase-tolerant communication|
|US5632021||25 Oct 1995||20 May 1997||Cisco Systems Inc.||Computer system with cascaded peripheral component interconnect (PCI) buses|
|US5633858||29 Feb 1996||27 May 1997||Accton Technology Corporation||Method and apparatus used in hashing algorithm for reducing conflict probability|
|US5634138||7 Jun 1995||27 May 1997||Emulex Corporation||Burst broadcasting on a peripheral component interconnect bus|
|US5649141||30 Jun 1995||15 Jul 1997||Nec Corporation||Multiprocessor system for locally managing address translation table|
|US5664224 *||18 Dec 1995||2 Sep 1997||Escom Ag||Apparatus for selectively loading data blocks from CD-ROM disks to buffer segments using DMA operations|
|US5671357||6 Sep 1996||23 Sep 1997||Motorola, Inc.||Method and system for minimizing redundant topology updates using a black-out timer|
|US5715395||12 Sep 1994||3 Feb 1998||International Business Machines Corporation||Method and apparatus for reducing network resource location traffic in a network|
|US5724529||22 Nov 1995||3 Mar 1998||Cirrus Logic, Inc.||Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system|
|US5734824||3 Dec 1996||31 Mar 1998||Bay Networks, Inc.||Apparatus and method for discovering a topology for local area networks connected via transparent bridges|
|US5740175 *||3 Oct 1995||14 Apr 1998||National Semiconductor Corporation||Forwarding database cache for integrated switch controller|
|US5740468||1 Dec 1993||14 Apr 1998||Fujitsu Limited||Data transferring buffer|
|US5754791||25 Mar 1996||19 May 1998||I-Cube, Inc.||Hierarchical address translation system for a network switch|
|US5761431||12 Apr 1996||2 Jun 1998||Peak Audio, Inc.||Order persistent timer for controlling events at multiple processing stations|
|US5764996||27 Nov 1995||9 Jun 1998||Digital Equipment Corporation||Method and apparatus for optimizing PCI interrupt binding and associated latency in extended/bridged PCI busses|
|US5781549||23 Feb 1996||14 Jul 1998||Allied Telesyn International Corp.||Method and apparatus for switching data packets in a data network|
|US5784373||20 Feb 1996||21 Jul 1998||Matsushita Electric Works, Ltd.||Switching device for LAN|
|US5852607 *||26 Feb 1997||22 Dec 1998||Cisco Technology, Inc.||Addressing mechanism for multiple look-up tables|
|US5914938 *||19 Nov 1996||22 Jun 1999||Bay Networks, Inc.||MAC address table search unit|
|US5930261 *||28 Jan 1997||27 Jul 1999||Galileo Technologies Ltd||Bus protocol|
|US5946679 *||31 Jul 1997||31 Aug 1999||Torrent Networking Technologies, Corp.||System and method for locating a route in a route table using hashing and compressed radix tree searching|
|US5948069 *||19 Jul 1996||7 Sep 1999||Hitachi, Ltd.||Networking system and parallel networking method|
|US5999981 *||28 Jan 1997||7 Dec 1999||Galileo Technologies Ltd.||Switching ethernet controller providing packet routing|
|US6084877 *||18 Dec 1997||4 Jul 2000||Advanced Micro Devices, Inc.||Network switch port configured for generating an index key for a network switch routing table using a programmable hash function|
|US6223270 *||19 Apr 1999||24 Apr 2001||Silicon Graphics, Inc.||Method for efficient translation of memory addresses in computer systems|
|US6240065 *||30 Jul 1998||29 May 2001||Galileo Technologies Ltd.||Bit clearing mechanism for an empty list|
|US6292483 *||18 Dec 1997||18 Sep 2001||Advanced Micro Devices, Inc.||Apparatus and method for generating an index key for a network switch routing table using a programmable hash function|
|1||*||Black's Law Dictionary. http://weblinks.westlaw.com/Search/defa . . . =ptoblcaks%2D1001&RS=WEBL1%2E0&VR=1%2E0. West 2002. pp. 1-3.|
|2||Dr. Dobb's Journal, "Essential Books on Algorithms and Data Structures", CD-Rom Library, Section 9.31 and 9.34, 1995.|
|3||*||G. Hicks. User FTP Documentation. RFC412. Nov. 27, 1972. pp. 1-7.|
|4||*||K. Abe, Y. Lacroix, L. Bonnell, and Z. Jakubczyk. Modal Interference in a Short Fiber Section: Fiber Length, Splice Loss, Cutoff, and Wavelength Dependences. Journal of Lightwave Technology, vol. 10, No. 4, Apr. 1992. pp. 401-406.|
|5||Ralston and Reilly, Encyclopedia of Computer Science, (third edition), pp. 1185-11911, 1995.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7174395 *||3 Dec 2001||6 Feb 2007||Sony Corporation||Communication interface method and device utilizing direct memory access data transfer|
|US7948999 *||4 May 2007||24 May 2011||International Business Machines Corporation||Signaling completion of a message transfer from an origin compute node to a target compute node|
|US8730984 *||2 May 2011||20 May 2014||Intel Corporation||Queuing based on packet classification|
|US20030014547 *||3 Dec 2001||16 Jan 2003||Koichi Sugiyama||Data transfer method, data transfer device, communication interface method, and communication interface device|
|US20080273543 *||4 May 2007||6 Nov 2008||Blocksome Michael A||Signaling Completion of a Message Transfer from an Origin Compute Node to a Target Compute Node|
|US20100141466 *||5 Apr 2002||10 Jun 2010||Mary Thanhhuong Thi Nguyen||System and method for automatic detection of fiber and copper in data switch systems|
|US20110208871 *||2 May 2011||25 Aug 2011||Intel Corporation||Queuing based on packet classification|
|U.S. Classification||370/402, 370/412, 370/401, 711/216, 370/389|
|International Classification||H04L12/935, H04L12/931, H04L12/937, H04L12/28|
|Cooperative Classification||H04L49/3018, H04L49/351, H04L49/201, H04L49/254, H04L49/3009|
|1 May 2003||AS||Assignment|
Owner name: MARVELL SEMICONDUCTOR ISRAEL LTD., ISRAEL
Free format text: CHANGE OF NAME;ASSIGNOR:GALILEO TECHNOLOGY LTD.;REEL/FRAME:014018/0655
Effective date: 20021215
|19 Jan 2007||FPAY||Fee payment|
Year of fee payment: 8
|19 Jan 2007||SULP||Surcharge for late payment|
Year of fee payment: 7
|9 Jul 2008||AS||Assignment|
Owner name: MARVELL ISRAEL (M.I.S.L) LTD., ISRAEL
Free format text: CHANGE OF NAME;ASSIGNOR:MARVELL SEMICONDUCTOR ISRAEL LTD.;REEL/FRAME:021212/0730
Effective date: 20080128