USRE37048E1 - Field programmable digital signal processing array integrated circuit - Google Patents
Field programmable digital signal processing array integrated circuit Download PDFInfo
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- USRE37048E1 USRE37048E1 US08/946,928 US94692897A USRE37048E US RE37048 E1 USRE37048 E1 US RE37048E1 US 94692897 A US94692897 A US 94692897A US RE37048 E USRE37048 E US RE37048E
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/946,928 USRE37048E1 (en) | 1993-08-20 | 1997-10-08 | Field programmable digital signal processing array integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/109,727 US5457644A (en) | 1993-08-20 | 1993-08-20 | Field programmable digital signal processing array integrated circuit |
US08/946,928 USRE37048E1 (en) | 1993-08-20 | 1997-10-08 | Field programmable digital signal processing array integrated circuit |
Related Parent Applications (1)
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US08/109,727 Reissue US5457644A (en) | 1993-08-20 | 1993-08-20 | Field programmable digital signal processing array integrated circuit |
Publications (1)
Publication Number | Publication Date |
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USRE37048E1 true USRE37048E1 (en) | 2001-02-06 |
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Family Applications (2)
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US08/109,727 Ceased US5457644A (en) | 1993-08-20 | 1993-08-20 | Field programmable digital signal processing array integrated circuit |
US08/946,928 Expired - Lifetime USRE37048E1 (en) | 1993-08-20 | 1997-10-08 | Field programmable digital signal processing array integrated circuit |
Family Applications Before (1)
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US08/109,727 Ceased US5457644A (en) | 1993-08-20 | 1993-08-20 | Field programmable digital signal processing array integrated circuit |
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US (2) | US5457644A (en) |
EP (1) | EP0639816A3 (en) |
JP (1) | JPH0786921A (en) |
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US20030025839A1 (en) * | 2001-07-31 | 2003-02-06 | Shuhua Xiang | Address generation for video processing |
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US20050206784A1 (en) * | 2001-07-31 | 2005-09-22 | Sha Li | Video input processor in multi-format video compression system |
US20050207663A1 (en) * | 2001-07-31 | 2005-09-22 | Weimin Zeng | Searching method and system for best matching motion vector |
US20050213661A1 (en) * | 2001-07-31 | 2005-09-29 | Shuhua Xiang | Cell array and method of multiresolution motion estimation and compensation |
US20050216608A1 (en) * | 2001-07-31 | 2005-09-29 | Xu Wang | Multiple channel data bus control for video processing |
US20050223410A1 (en) * | 2001-07-31 | 2005-10-06 | Sha Li | Video processing control and scheduling |
US20050228970A1 (en) * | 2001-07-31 | 2005-10-13 | Shuhua Xiang | Processing unit with cross-coupled alus/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
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US20120117357A1 (en) * | 2010-11-08 | 2012-05-10 | Electronics And Telecommunications Research Institute | Energy tile processor |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
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US7024653B1 (en) * | 2000-10-30 | 2006-04-04 | Cypress Semiconductor Corporation | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) |
US6970509B2 (en) | 2001-07-31 | 2005-11-29 | Wis Technologies, Inc. | Cell array and method of multiresolution motion estimation and compensation |
US7184101B2 (en) | 2001-07-31 | 2007-02-27 | Micronas Usa, Inc. | Address generation for video processing |
US6996702B2 (en) * | 2001-07-31 | 2006-02-07 | Wis Technologies, Inc. | Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
US20050206784A1 (en) * | 2001-07-31 | 2005-09-22 | Sha Li | Video input processor in multi-format video compression system |
US20050207663A1 (en) * | 2001-07-31 | 2005-09-22 | Weimin Zeng | Searching method and system for best matching motion vector |
US20050213661A1 (en) * | 2001-07-31 | 2005-09-29 | Shuhua Xiang | Cell array and method of multiresolution motion estimation and compensation |
US20050216608A1 (en) * | 2001-07-31 | 2005-09-29 | Xu Wang | Multiple channel data bus control for video processing |
US20050223410A1 (en) * | 2001-07-31 | 2005-10-06 | Sha Li | Video processing control and scheduling |
US6981073B2 (en) | 2001-07-31 | 2005-12-27 | Wis Technologies, Inc. | Multiple channel data bus control for video processing |
US20030025839A1 (en) * | 2001-07-31 | 2003-02-06 | Shuhua Xiang | Address generation for video processing |
US7219173B2 (en) | 2001-07-31 | 2007-05-15 | Micronas Usa, Inc. | System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time |
US7142251B2 (en) | 2001-07-31 | 2006-11-28 | Micronas Usa, Inc. | Video input processor in multi-format video compression system |
US20050228970A1 (en) * | 2001-07-31 | 2005-10-13 | Shuhua Xiang | Processing unit with cross-coupled alus/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
US7035332B2 (en) | 2001-07-31 | 2006-04-25 | Wis Technologies, Inc. | DCT/IDCT with minimum multiplication |
US7085320B2 (en) | 2001-07-31 | 2006-08-01 | Wis Technologies, Inc. | Multiple format video compression |
US20040036500A1 (en) * | 2002-08-08 | 2004-02-26 | Bratt Adrian Harvey | Semiconductor devices |
US20040242261A1 (en) * | 2003-05-29 | 2004-12-02 | General Dynamics Decision Systems, Inc. | Software-defined radio |
US20050094677A1 (en) * | 2003-10-30 | 2005-05-05 | Lsi Logic Corporation | Optimized interleaver and/or deinterleaver design |
US7502390B2 (en) * | 2003-10-30 | 2009-03-10 | Lsi Corporation | Optimized interleaver and/or deinterleaver design |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US20120117357A1 (en) * | 2010-11-08 | 2012-05-10 | Electronics And Telecommunications Research Institute | Energy tile processor |
Also Published As
Publication number | Publication date |
---|---|
JPH0786921A (en) | 1995-03-31 |
US5457644A (en) | 1995-10-10 |
EP0639816A2 (en) | 1995-02-22 |
EP0639816A3 (en) | 1995-11-29 |
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