US RE28923 E Abstract A system for correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error in .Iadd.each code word of .Iaddend.a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data arrangement is provided. The message data Z
_{1}, Z_{2}, . . . Z_{k} is encoded by adding two check bytes C_{1} and C_{2} thereto which are generated from the message data which is arranged in blocks of k bytes, where each byte has f bits of data, .[.arranged in a cross track direction.]. where f = b × m and m and b are integers >1 and k is an integer 2<k<2^{b}. The check bytes are generated in accordance with the equations:C and
C . ⊕T
^{k}.sup.λ Z_{k} where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is an integer given by the expression:
t(2 in which t is any positive integer prime to 2
^{b} -1. The encoded message is decoded after usage (indicated by the ' symbol) by first and second shift registers which generate first and second syndromes from the encoded data in accordance with the equations:S S Z
_{2} '⊕ . . . ⊕T^{k}.sup.λ Z_{k} 'Error pointers are provided for indicating the .[.tracks.]. .Iadd.bytes .Iaddend.in error and the .[.bytes.]. .Iadd.bits .Iaddend.in error in the indicated .[.tracks.]. .Iadd.bytes .Iaddend.are corrected in accordance with the error patterns generated by processing the syndromes.
Claims(12) 1. A system for correcting two tracks in error in a multi-track data arrangement, comprising:
means for providing message data Z _{1}, Z_{2}, Z_{3},...Z_{k} arranged in blocks having k bytes arranged in a cross track direction, each byte having f bits of data where f = b × m where b and m are integers >1 and k is an integer 2<k< 2^{b} ;means connected to said means for providing message data for generating two check bytes from said message data in accordance with the equations: C and C where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is any integer given by the expression t(.[.2 ^{b} .]. .Iadd.2^{f}.Iaddend. -1)/(2^{b} -1) in which t is any positive integer prime to 2^{b} -1;means connected to said means for providing message data and to said means for generating two check bytes for appending said two check bytes to said message data to form an encoded message; means connected to said means for appending said two check bytes to said message data for utilizing said encoded message; means connected to said utilization means for decoding said encoded message denoted by Z _{1} ', Z_{2} ',...Z_{k} ', C_{1} ', C_{2} '; said decoding means including first and second shift registers for generating first and second syndromes S_{1} and S_{2} from said encoded message in accordance with the equations:S and S means for providing error track pointer signals as inputs to said decoder which identify the tracks in error; error .[.track.]. parameters signal generating means connected to said means for providing error .[.track.]. pointer signals for providing fixed signals in accordance with the tracks indicated to be in error; means connected to said error track parameters signal generating means for generating control signals for the operation of said decoder; and error correcting means connected to said first and second shift registers, to said means for providing .[.identifying.]. .Iadd.error pointer .Iaddend.signals, to said means for providing control signals, and to said utilization means for providing error correction of the erroneous bytes in any two indicated tracks in error. 2. A system according to claim 1, wherein said means for generating said two check bytes includes a data distributor and first and second feedback shift registers connected to said data distributor, said first shift register providing modulo 2 addition of the information bytes successively applied thereto from said data distributor and said second shift register providing the product of the contents thereof and the incoming byte from said data distributor and the modulo 2 addition thereof with the product of the contents thereof and the next input byte.
3. A system according to claim 2, wherein said second feedback shift register has f data stages and a modulo 2 summing circuit at the input to each stage, the feedback connections of each of said stages of said feedback shift register are determined in accordance with the digital "1" contents of the corresponding column of the matrix T
_{f}, the positions of the 1's is in the column determining feedback connections to the modulo 2 summing circuits at the inputs of the shift register stages having corresponding numerical positions in said feedback shift register.4. A system according to claim 1, wherein said error .[.track.]. parameters signal generating means receives error .[.track.]. pointer signals P
_{1}, P_{2},...P_{k}, P_{k} _{+2} from said means for providing error .[.track.]. pointer signals and generates parameters x and y as binary numbers, new pointers I_{1}, I_{2},...I_{k} identifying the first erroneous data track, and the signals N_{0}, N_{1} and N_{3} indicating respectively, 0, 1 and more than 2 tracks in error.5. A system according to claim 4, wherein said error .[.track.]. parameters signal generating means includes a plurality of logical AND and NOT circuits having as inputs thereto the track in error pointer signals P
_{1}, P_{2},...P_{k} from said means for providing pointer signals arranged in groups of increasing order by a pointer value of 1 starting with P_{1}, P_{1} P_{2} P_{1} P_{2} P_{3},...P_{1} P_{2} P_{3}...P_{k}, all the pointer signals except the additional pointer signal in each group being connected through one of said NOT circuits so that an output I_{i} is obtained from the AND circuit in which the additional pointer signal has a "1" input thereby identifying the first data track in error.6. A system according to claim 5, wherein said error .[.track.]. parameters signal generating means further includes a first plurality of OR circuits, and said I
_{i} signals identifying the first track in error are grouped as inputs to said first plurality of OR circuits, the grouping is predetermined in accordance with a table wherein the output y parameter is obtained as a predetermined b-bit binary number.7. A system according to claim 4, wherein said error track parameters signal generating means, further includes a second plurality of AND circuits and a second and third plurality of OR circuits said second plurality of AND circuits having error track pointer signals as inputs thereto arranged in groups of pairs, said pairs of inputs thereto arranged in groups of pairs, said pairs of said first group being all possible adjacent pairs, said pairs of said second group being all possible pairs separated by one error track pointer signal input, said pairs of said third group being all possible pairs separated by two error track pointer signal inputs, said pairs of said k
^{th} group being all possible pairs separated by k-1 error track pointer signal inputs, the outputs of each of said groups of said second plurality of AND circuits are connected to respective ones of said second plurality of OR circuits whose outputs correspond to the j-i=1 to the j-i=k-1 value; each of the j-i value outputs being connected as inputs to said third plurality of OR circuits, the connections being determined in accordance with a predetermined table giving said x parameter as a b-bit binary number.8. A system in accordance with claim 4, wherein said error track parameters signal generating means further includes a combination of a plurality of NOT circuits connected to an AND circuit, a `one and only one` circuit, and a threshold circuit, each of said circuits having the error track parameters signals from said error track parameters signal generating means as inputs thereto and having said signals N
_{0}, N_{1} and N_{3} as outputs therefrom, respectively, representing 0, 1 and more than two tracks in error.9. A system in accordance with claim 4, wherein said means for generating control signals includes counting means which are energized to count down simultaneously with the shift signal for said shift registers SR1 and SR2;
means for setting said counting means to the binary value of x generated by said error track parameters signal generating means and counting down to 0 in synchronism with the shifting of SR1 and SR2 to introduce the parameter y into the error pattern e _{j} computation which is computed from the syndromes S_{1} and S_{2} according to:e 10. A system according to claim 9, wherein inhibiting means are provided connected to the output of shift register SR2 for inhibiting the e
_{j} output when j = k+2 and pointer P_{k} _{+2} is on indicating the k+2 track is in error.11. A system according to claim 10, wherein said error correcting means includes means for adding (modulo 2) error pattern e
_{j}, erroneous read bytes Z_{1} ', Z_{2} ',...Z_{k} ' and syndrome S_{1} to obtain the corrected bytes Z_{1}, Z_{2},...Z_{k}.12. A system according to claim 4, wherein said decoding means further includes an uncorrectable error indicating circuit connected to said error track parameters signal generating means which provides said N
_{0}, N_{1}, and N_{3} signals, and to said shift registers SR1 and SR2 which provide syndrome S_{1} and error pattern e_{j} signals, respectively; said N_{3} signal indicating that more than two tracks are in error, and said N_{1} signal indicating that only one track is in error and that e_{j} is not 0 in all bit positions, and said N_{0} signal indicating that no track is in error when e_{j} or S_{1} is not 0 in all bit positions. .Iadd.13. A system for correcting two bytes in error in each code word in a multi-code word data arrangement comprising:means for providing message data Z _{1}, Z_{2}, Z_{3},...Z_{k} arranged in blocks having k bytes, each byte having f bits of data where f = b × m and where b and m are integers >1 and k is an integer 2<k<2^{b} ;means connected to said means for providing message data for generating two check bytes from said message data in accordance with the equations: C and C where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is any integer given by the expression t(2 ^{f} -1)/(2^{b} -1) in which t is any positive integer prime to 2^{b} -1;means connected to said means for providing message data and to said means for generating two check bytes for appending said two check bytes to said message data to form an encoded message; means connected to said means for appending said two check bytes to said message data for utilizing said encoded message; means connected to said utilization means for decoding said encoded message denoted by Z _{1} ', Z.sub. 2 ',...Z_{k} ', C_{1} ', C_{2} '; said decoding means including first and second shift registers for generating first and second syndromes S_{1} and S_{2} from said encoded message in accordance with the equations:S and S means for providing error signals as inputs to said decoder which identify the bytes in error: error parameters signal generating means connected to said means for providing error pointer signals for providing fixed signals in accordance with the bytes indicated to be in error; means connected to said error parameters signal generating means for generating control signals for the operation of said decoder; and error correcting means connected to said first and second shift registers, to said means for providing error pointer signals, to said means for providing control signals, and to said utilization means for providing error correction of the erroneous bits in any two indicated bytes in error. .Iaddend. Description This invention relates to error detection and correction and, more particularly, to an improved error correcting code and system for detecting and correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data arrangement. In data communication systems as well as computers, the information can be coded by adding redundant bits to the data message in such a way that the message can be decoded with a practical amount of apparatus to obtain the original information corrected in the event an error has been introduced. Parallel data arrangements, that is, arrangements where the information is contained in parallel bytes arranged in a block of data, are used in computers and are well known especially in multi-channel recording apparatus. In copending application, Ser. No. 10,847, filed on Feb. 12, 1970, now U.S. Pat. No. 3,629,824, encoding and decoding apparatus are disclosed in which the redundant or check bits are associated with the data in a cross byte or cross track direction. This co-pending application sets forth a code capable of correcting one or more errors within a single, multiple bit byte of data. The data is divided into blocks which consists of k bytes of data (each of b bits), plus two check bytes, each of b bits. The decoder is effective in recovering the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. In U.S. Pat. No. 3,319,223, filed Mar. 31, 1964, an error correcting code is disclosed in which the check characters generated from the information are added serially to the message block. The coding and decoding is implemented by means of shift register circuits. Another co-pending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 utilizes the above-identified code but extends the capabilities thereof by combining therewith pointer signals which extend the error correcting capability of the arrangement to two bytes in error regardless of the number of bits in error in each byte. It is an object of the present invention to provide an improved error control system in parallel data systems such as computer tape recording systems and similar multi-channel recording apparatus. It is another object of the present invention to provide an error detection and correction system based on a new code which can be mechanized to provide two .[.channel.]. .Iadd.byte .Iaddend.correction .Iadd.in each code word .Iaddend.as well as detection of a large percentage of other errors without increasing the redundancy. It is a further object of the present invention to provide an error detection and correction system in which larger size characters or bytes can be utilized without substantially increasing the encoding and decoding time and hardware. It is a further object of the present invention to provide an error detection and correction code capable of providing correction for two tracks in error in a multi-channel system when pointers for the tracks in error are provided. It is another object of the present invention to provide an error detection and correction system in which all the necessary error correction functions can be realized by means of the same pair of shift registers. The system for correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data arrangement consists of an encoding means for generating two check bytes C
C and
C where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is any integer given by the expression t(2
S and
S Error pointers are provided which indicate the .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.and means are provided which locate the bits in error in the .[.tracks.]. .Iadd.bytes .Iaddend.in error which can then be corrected in accordance with the errors indicated by the syndromes. The foregoing and other objects, features and advantages of the invention, will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings. FIG. 1 is a schematic diagram showing the data arrangement in a multi-track data system. FIG. 2 shows a block diagram for carrying out the encoding of the present invention. FIG. 3 is a schematic diagram showing the decoder arrangement .[.for.]. of the present invention. FIG. 4 is a schematic diagram .[.showing the organization.]. of the first shift register of the pair of shift registers used for encoding and decoding in the error correction system of the invention. FIG. 5 is a further schematic diagram showing the second shift register of the pair of shift registers. FIG. 6 shows the error track parameter generator used in the decoder which includes the FIGS. 6a, 6b, 6c and 6d in its overall arrangement. FIG. 6a is a schematic diagram showing the logic network connections for generating the i pointers. FIG. 6b is a schematic logic diagram showing the generation of the Y parameter. FIG. 6c is a schematic logic diagram showing the generation of the X parameter. FIG. 6d is a schematic logic diagram for generating the control signals N FIG. 7 is a schematic diagram showing the error corrector circuit of the decoder. FIG. 8 is a schematic logic diagram showing the arrangement for the detection of a large percentage of uncorrectable errors. It will be appreciated by those skilled in the art that this invention can be applied to Information Handling Systems of various capacities. The invention will, therefore, be first described in algebraic terms which are applicable to any size system and subsequently in terms of a specific system. Data is processed by the system in blocks consisting of k bytes, each byte having f bits of data where f = b × m. Here and throughout, b and m designate integers >1 and k is an integer 2<k<2
C
C wherein: ⊕ denotes the modulo 2 vector sum; T is the companion matrix of a binary primitive polynomial g(x) of degree f which will be developed further as equation (3). For every f, there exists at least one primitive polynomial of degree f. For a list of primitive polynomials, see W. W. Petersen, Error Correcting Codes, M.I.T. Press, 1961. T λ is any integer given by the expression: t(2.sup. f - 1)/(2 In order to more clearly explain the invention, a specific value f = 8 has been chosen. The polynomial g(x) of degree 8 can be explicitly written as:
g(x)=g where:
g
i = 1,2,...7 The companion matrix T of the polynomial g(x) is defined as: ##EQU2## As was mentioned previously in the Background of the Invention, co-pending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 discloses a multi-track error correction system having k data tracks and two check byte tracks. Two b-digit check bytes are generated from k b-digit information bytes where 2<k<2 There are a number of situations where an increase in the byte size participating in the code word computation is desirable. For example, in computer tape recording systems, dividing binary data tracks into 8-bit bytes is preferred because of the 8-bit byte organization of the main processor. Thus, an 8-bit byte error correction arrangement would be preferred to the 4-bit byte arrangement shown in the co-pending application. The code generated in this invention is actually a shortened code which possesses an added capability of detecting a certain percentage of errors which cannot be corrected. The percentage R can be estimated as: The full length is defined as 2 Although the code generated in this invention is actually a shortened form of a longer code, the encoding and decoding apparatus required is equivalent to that required for the shortened code rather than the longer code. Apparatus is also described for encoding and decoding this special code by means of which two tracks in error can be corrected when track pointers are provided. The actual code generated as a result of this invention can best be described through an example using 8-bit bytes. This arrangement will also be contrasted with the 4-bit byte arrangement of the prior art so that the advantages thereof can better be appreciated. The binary form of the parity check matrix for the 4-bit byte code in its full length is given by: ##EQU3## where O
T where:
λ = t(2 for any t prime to (2
T are all distinct T
λ = 68, T thus, it can be seen that the fifth column in equation (8) is equivalent to the 85th column in equation (6). It can be seen from the above, that the code constructed using the subfield elements T
C
c after the message has been encoded and utilized at the recorder, the read message bytes are transmitted or conveyed to the decoder. The message is distributed by a read message distributor which sends the encoded message in parallel to a pair of shift registers SR1 and SR2. The decoder computes two expressions known as the syndrome S
S
S The received message byte Z The "pointer" signals are derived from the system in which the error correction is taking place. Of course, there are various means of generating "pointer" signals such as is set forth in corresponding U.S. Pat. application, Ser. No. 40,836, filed May 26, 1970, entitled, "Enhanced Error Detection and Correction For Data Systems." In this application, the quality of the record/read back operations on a real times basis is used as pointers to possible error conditions. The syndromes generated from the encoded data bytes and check bytes contain the error patterns. These error pattern bytes e
y = - i modulo 2 For each value j-i, the values of parameter x and for each value of i, the parameter y are fixed. These parameters can be computed algebraically. For example, in the preferred embodiment where T.sup.λ = T
TABLE 1.--PARAMETER x______________________________________ j-i=
TABLE 2.--PARAMETER y______________________________________ i= 1 2 3 4 5 6 y= 14 13 12 11 10 9______________________________________ - Using the above computed values of x and y, the error pattern e In summary, the decoding process consists of: 1. Computing the syndromes S 2. Computing the error pattern e 3. Correcting the erroneous bytes with the error pattern e 4. Detection of the uncorrectable errors according to the following: 4a. When more than two tracks are indicated as being in error, the code cannot provide reliable error correction. 4b. When two tracks are indicated as being in error, the error pattern bytes e 4c. When exactly one track is indicated as being in error (the case where i is equal to j), then the error pattern byte e 4d. When no track is indicated as being in error, then the syndromes S Utilizing the previous example of 8-bit bytes, it can be seen from FIG. 2, that the data Z Referring to FIG. 4, each input bit Z(0)...Z(7) of the 8-bit byte is applied to a separate modulo 2 summing circuit 16 at the input to each of the eight separate shift register storage elements 18. The output 20 of each binary storage element 18 is fed back via a feedback connection 22 to the modulo 2 adding circuit 16 at the input thereto along the with new input. In FIG. 5, each of the 8-bits Z(0)...Z(7) of an 8-bit byte are shown as inputs to the modulo 2 adder circuits 20 - 27 at the input to each storage element of the shift register. The outputs 30 - 37 of each of the binary storage elements (0)...(7) are connected to certain ones of the modulo 2 adder circuits 20 - 27 in accordance with the columns of the matrix T The information is entered into the shift registers SR1 and SR2 in reverse order, that is, Z The contents of shift register SR1 will be Z Referring to FIG. 3, the decoder 42 receives the encoded read or utilized message bytes Z The decoder 42 first computes the syndromes S The count 0 signal from the counter B The count 0 signal generated by counter B The count 0 signal from the counter B FIG. 6 shows schematically the error track parameters generator 46 which generates the parameters x and y as binary numbers from the input pointer signals P Referring to FIG. 6a, there is shown, the logic network connections for generating the I pointers I FIG. 6b has as inputs the I pointers generated in FIG. 6a. This circuit generates the y parameters as a b-bit binary number y
Table 3.-- Parameter y as a binary member______________________________________ y as binary numberi Indicated by y y Therefore, the signals y FIG. 6c shows a logic circuit diagram which generates the x parameters as a b-bit binary number x
Table 4.-- Parameter x as a binary number______________________________________ x as a binary numberj-i Function x x Note that P FIG. 6d shows the circuit arrangement for generating the control signals N Referring to FIG. 7, there is shown the error corrector circuit 68 which produces the corrected data bytes Z If j = k + 2, i.e., the pointer P Referring to FIG. 8, there is shown the uncorrectable error indicator logic circuit 80 for detection of a large percentage of uncorrectable errors. This circuit generates an error indicator signal E when one of the following happens: 1. N 2. N 3. N While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention. Patent Citations
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