|Publication number||USRE28923 E|
|Application number||US 05/586,766|
|Publication date||3 Aug 1976|
|Filing date||13 Jun 1975|
|Priority date||27 Dec 1971|
|Publication number||05586766, 586766, US RE28923 E, US RE28923E, US-E-RE28923, USRE28923 E, USRE28923E|
|Inventors||Arvind Motibhai Patel|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (6), Classifications (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
C1 =Z1 ⊕Z2 ⊕Z3 . . . ⊕Zk
C2 =T.sup.λZ1 ⊕T2 .sup.λ Z2 ⊕ . .
t(2f -1)/(2b -1)
S1 =C1 '⊕Z1 '⊕Z2 '⊕ . . . ⊕Zk '
S2 =C2 '⊕T.sup.λZ1 '⊕T2.sup.λ
C1 = Z1 ⊕Z2 ⊕Z3...⊕Zk
C2 = T.sup.λZ1 ⊕T2.sup.λ Z2 ⊕...⊕Tk.sup.λ Zk
S1 = C1 '⊕Z1 '⊕Z2 '⊕...⊕Zk '
S2 = C2 '⊕T.sup.λ Z1 '⊕T2 .sup.λ Z2 '⊕...⊕Tk .sup.λ Zk '
ej = Tx.sup.λ [S1 ⊕Ty .sup.λ S2 ].
C1 = Z1 ⊕Z2 ⊕Z3...⊕Zk
C2 = T.sup.λZ1 ⊕T2.sup.λ Z2 ⊕...⊕Tk.sup.λ Zk
S1 = C1 '⊕Z1 '⊕Z2 '⊕...⊕Zk '
S2 = C2 '⊕T.sup.λZ1 '⊕T2.sup.λ Z2 '⊕...⊕Tk.sup.λ Zk '
This invention relates to error detection and correction and, more particularly, to an improved error correcting code and system for detecting and correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data arrangement.
In data communication systems as well as computers, the information can be coded by adding redundant bits to the data message in such a way that the message can be decoded with a practical amount of apparatus to obtain the original information corrected in the event an error has been introduced. Parallel data arrangements, that is, arrangements where the information is contained in parallel bytes arranged in a block of data, are used in computers and are well known especially in multi-channel recording apparatus. In copending application, Ser. No. 10,847, filed on Feb. 12, 1970, now U.S. Pat. No. 3,629,824, encoding and decoding apparatus are disclosed in which the redundant or check bits are associated with the data in a cross byte or cross track direction. This co-pending application sets forth a code capable of correcting one or more errors within a single, multiple bit byte of data. The data is divided into blocks which consists of k bytes of data (each of b bits), plus two check bytes, each of b bits. The decoder is effective in recovering the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. In U.S. Pat. No. 3,319,223, filed Mar. 31, 1964, an error correcting code is disclosed in which the check characters generated from the information are added serially to the message block. The coding and decoding is implemented by means of shift register circuits. Another co-pending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 utilizes the above-identified code but extends the capabilities thereof by combining therewith pointer signals which extend the error correcting capability of the arrangement to two bytes in error regardless of the number of bits in error in each byte.
It is an object of the present invention to provide an improved error control system in parallel data systems such as computer tape recording systems and similar multi-channel recording apparatus.
It is another object of the present invention to provide an error detection and correction system based on a new code which can be mechanized to provide two .[.channel.]. .Iadd.byte .Iaddend.correction .Iadd.in each code word .Iaddend.as well as detection of a large percentage of other errors without increasing the redundancy.
It is a further object of the present invention to provide an error detection and correction system in which larger size characters or bytes can be utilized without substantially increasing the encoding and decoding time and hardware.
It is a further object of the present invention to provide an error detection and correction code capable of providing correction for two tracks in error in a multi-channel system when pointers for the tracks in error are provided.
It is another object of the present invention to provide an error detection and correction system in which all the necessary error correction functions can be realized by means of the same pair of shift registers.
The system for correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data arrangement consists of an encoding means for generating two check bytes C1 and C2 for the message data Z1, Z2 ,...Zk which is arranged in blocks having k bytes where each byte has f bits of data .[.extending in a cross track direction.]. where f = b × m where b and m are integers >1 and k is an integer 2<k<2b. The check bytes are generated in accordance with the equations:
C1 = Z1 ⊕Z2 ⊕Z3...⊕Zk
C2 = T.sup.λZ1 ⊕T2 .sup.λ Z2 ⊕...⊕Tk .sup.λ Zk
where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is any integer given by the expression t(2f - 1)/(2b - 1) in which t is any positive integer prime to 2b - 1. The check bytes are appended to the incoming message data to obtain the encoded data for use in a .[.multi-track.]. .Iadd.multi-code word .Iaddend.data system. The encoded data is decoded after usage (indicated by the ' symbol) by means of first and second shift registers with generate first and second syndromes from the encoded data in accordance with the equations:
S1 = C1 '+Z1 '⊕Z2 '⊕...Zk '
S2 = C2 '⊕T.sup.λ Z1 '⊕T2.sup.λ Z2 '⊕...⊕Tk.sup.λ Zk '
Error pointers are provided which indicate the .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.and means are provided which locate the bits in error in the .[.tracks.]. .Iadd.bytes .Iaddend.in error which can then be corrected in accordance with the errors indicated by the syndromes.
The foregoing and other objects, features and advantages of the invention, will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
FIG. 1 is a schematic diagram showing the data arrangement in a multi-track data system.
FIG. 2 shows a block diagram for carrying out the encoding of the present invention.
FIG. 3 is a schematic diagram showing the decoder arrangement .[.for.]. of the present invention.
FIG. 4 is a schematic diagram .[.showing the organization.]. of the first shift register of the pair of shift registers used for encoding and decoding in the error correction system of the invention.
FIG. 5 is a further schematic diagram showing the second shift register of the pair of shift registers.
FIG. 6 shows the error track parameter generator used in the decoder which includes the FIGS. 6a, 6b, 6c and 6d in its overall arrangement.
FIG. 6a is a schematic diagram showing the logic network connections for generating the i pointers.
FIG. 6b is a schematic logic diagram showing the generation of the Y parameter.
FIG. 6c is a schematic logic diagram showing the generation of the X parameter.
FIG. 6d is a schematic logic diagram for generating the control signals N0, N1 and N3.
FIG. 7 is a schematic diagram showing the error corrector circuit of the decoder.
FIG. 8 is a schematic logic diagram showing the arrangement for the detection of a large percentage of uncorrectable errors.
It will be appreciated by those skilled in the art that this invention can be applied to Information Handling Systems of various capacities. The invention will, therefore, be first described in algebraic terms which are applicable to any size system and subsequently in terms of a specific system.
Data is processed by the system in blocks consisting of k bytes, each byte having f bits of data where f = b × m. Here and throughout, b and m designate integers >1 and k is an integer 2<k<2b. The values of f and k are to be considered invariant for a particular embodiment, but are variously chosen for embodiments of various capacities. A block of data is accordingly designated Z1, Z2,...Zk wherein Z1 represents the first byte in the block, Z2 the second byte, and so on to Zk which represents the kth and last byte. The encoder calculates from the block of incoming data two check bytes, (designated C1 and C2) each of f bits and appends the check bytes to the k data bytes to generate the sent message of k+2 bytes. The data format arrangement is shown in FIG. 1. The check bytes are added in separate tracks, parallel and adjacent to the tracks carrying the data bytes. Each byte Z1 and C1 and C2 are f bit column vectors in the mathematical equations throughout and can be explicitly written as: ##EQU1## The check bytes C1 and C2 are computed from the information bytes Z1, Z2,...Zk using the following matrix equations:
C1 = Z1 ⊕Z2 ⊕...⊕Zk ( 1)
C2 = T.sup.λ Z1 ⊕T2 .sup.λ Z2 ⊕...⊕Tk .sup.λ Zk ( 2)
⊕ denotes the modulo 2 vector sum;
T is the companion matrix of a binary primitive polynomial g(x) of degree f which will be developed further as equation (3). For every f, there exists at least one primitive polynomial of degree f. For a list of primitive polynomials, see W. W. Petersen, Error Correcting Codes, M.I.T. Press, 1961.
Ti is the ith power of the matrix T. (Computed using modulo 2 operations).
λ is any integer given by the expression:
t(2.sup. f - 1)/(2b - 1) in which t is any positive integer prime to 2.sup. b - 1. Since f = b × m, the above expression always results in a positive integer. The use of λ in this code has particular significance, which will become apparent from the discussion with respect to the preferred embodiment to follow.
In order to more clearly explain the invention, a specific value f = 8 has been chosen. The polynomial g(x) of degree 8 can be explicitly written as:
g(x)=g0 + g1 x g2 x2 +...g7 x7 + g8 x8
g0 = g8 - 1 and gi is either 0 or 1 for:
i = 1,2,...7
The companion matrix T of the polynomial g(x) is defined as: ##EQU2##
As was mentioned previously in the Background of the Invention, co-pending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 discloses a multi-track error correction system having k data tracks and two check byte tracks. Two b-digit check bytes are generated from k b-digit information bytes where 2<k<2b. It will be appreciated that in this prior art system, the byte size b can be increased. However, the encoding and decoding hardware increases considerably with the increase in size of the bytes participating in the computation. Accordingly, these prior art arrangements have attempted to keep the byte size as small as possible while still satisfying the relation 2<k<2b.
There are a number of situations where an increase in the byte size participating in the code word computation is desirable. For example, in computer tape recording systems, dividing binary data tracks into 8-bit bytes is preferred because of the 8-bit byte organization of the main processor. Thus, an 8-bit byte error correction arrangement would be preferred to the 4-bit byte arrangement shown in the co-pending application.
The code generated in this invention is actually a shortened code which possesses an added capability of detecting a certain percentage of errors which cannot be corrected. The percentage R can be estimated as:
The full length is defined as 2b +1 and the shortened length is defined as k+2, i.e., the maximum number of tracks on which the code can be used versus the actual number of tracks. For example, when k = 8, using a 4-bit byte gives a detection capability estimated as 53 percent of the other errors as opposed to an estimated 97 percent with an 8-bit byte arrangement.
Although the code generated in this invention is actually a shortened form of a longer code, the encoding and decoding apparatus required is equivalent to that required for the shortened code rather than the longer code. Apparatus is also described for encoding and decoding this special code by means of which two tracks in error can be corrected when track pointers are provided. The actual code generated as a result of this invention can best be described through an example using 8-bit bytes. This arrangement will also be contrasted with the 4-bit byte arrangement of the prior art so that the advantages thereof can better be appreciated. The binary form of the parity check matrix for the 4-bit byte code in its full length is given by: ##EQU3## where O4 and I4 are 4 × 4 "zero" and "identity" matrices and T4 is the companion matrix of a degree 4 primitive polynomial. One such polynomial is 1 + x3 + x4. Accordingly, T4 is given by: ##EQU4## Similarly, the parity check matrix for the 8-bit byte code in its full length is given by: ##EQU5## where O8 and I8 are 8 × 8 "zero" and "identity" matrices and T8 is the companion matrix of the primitive polynomial 1 + x + x3 + x5 + x8. ##EQU6## Note that T4 i are elements of the Galois Field GF(24) and T8 i are elements of the Galois Field GF(28). These elements have the properties that T4, T4 2,...,T4 15 are all distinct and T4 15 equals I4 and T8, T8 2,...,T8 255 are all distinct and T8 15 equals I8. The Galois Field GF(28) contains a subfield which is isomorphic to GF(24). The elements of this subfield are given by:
T8 .sup.λ, T8 2.sup.λ,...T8 15.sup.λ
λ = t(28 - 1)/(24 - 1)
for any t prime to (24 - 1). One such λ is 68. These subfield elements have the property:
T8 .sup.λ, T8 2 .sup.λ,...T8 15.sup.λ
are all distinct T8 15.sup.λ = I8. Furthermore, T.sub. 8 i .sup.λ and T4 i possess a one-to-one relationship in that the two sets are isomorphic in the "Sum" and "Product" operations of the corresponding Galois Field. Referring to the 8-bit byte code given by the following parity check matrix: ##EQU7## It is apparent that this code possesses the same mathematical structure as that of the 4-bit byte code given by the parity check matrix of equation (4). All the columns in the matrix of equation (8) have an equivalent column in the matrix of equation (6). For example, with:
λ = 68, T8 5 .sup.λ = T8 340 = T8 255 . T8 85 = T85
thus, it can be seen that the fifth column in equation (8) is equivalent to the 85th column in equation (6). It can be seen from the above, that the code constructed using the subfield elements Ti.sup.λ is a shortened form of the code given by equation (6). The code can be further shortened in the usual manner. For example, the 8-track arrangement can be encoded using the parity check matrix: ##EQU8## Accordingly, for λ = 68, the T8 .sup.λ is given by: ##EQU9## The preferred embodiment of this invention will be illustrated using the code defined in matrix (9) in an 8-track arrangement with 8-bit bytes. Accordingly, the two check bytes C1 and C2 are computed from the information bytes Z1, Z2, Z3, Z4, Z5, Z6 using the following equations:
C1 = I8 Z1 ⊕I8 Z2 ⊕...⊕I8 Z6 ( 11)
c2 = t8 .sup.λ z1 ⊕t8 2 .sup.λ z2 ⊕...⊕t8 6.sup.λ z6 ( 12)
after the message has been encoded and utilized at the recorder, the read message bytes are transmitted or conveyed to the decoder. The message is distributed by a read message distributor which sends the encoded message in parallel to a pair of shift registers SR1 and SR2. The decoder computes two expressions known as the syndrome S1 and S2 defined as:
S1 = C1 '⊕Z1 '⊕Z2 '⊕...⊕Zk '(13)
S2 = C2 '⊕T.sup.λ Z1 '⊕T2 .sup.λ Z2 '⊕...⊕Tk .sup.λ Zk ' (14)
The received message byte Z1 ', Z2 ',...Zk ', C1 ', C2 ' are the read message bytes corresponding to the recorded bytes Z1, Z2,...Zk, C1, C2, respectively. As was previously mentioned, there may be errors in up to two tracks causing errors in the corresponding bytes. These erroneous tracks are designated by track numbers i and j and are identified by pointer signals Pi and P.sub. j in the form of logical "1." For convenience, it is required that i ≦ j, 1 ≦ i ≦ k and 1 ≦ j ≦ k + 2. The case, where two indicated erroneous tracks are the check tracks, is ignored.
The "pointer" signals are derived from the system in which the error correction is taking place. Of course, there are various means of generating "pointer" signals such as is set forth in corresponding U.S. Pat. application, Ser. No. 40,836, filed May 26, 1970, entitled, "Enhanced Error Detection and Correction For Data Systems." In this application, the quality of the record/read back operations on a real times basis is used as pointers to possible error conditions.
The syndromes generated from the encoded data bytes and check bytes contain the error patterns. These error pattern bytes ei and ej in the bytes corresponding to the tracks i and j (when i = j, we assume ej = 0). S1 and S2 have the algebraic equivalent: ##EQU10## These expressions can be solved for ei and ej as follows: ##EQU11## wherein: ##EQU12## and:
y = - i modulo 2b - 1 (20)
For each value j-i, the values of parameter x and for each value of i, the parameter y are fixed. These parameters can be computed algebraically. For example, in the preferred embodiment where T.sup.λ = T8 68 as given in equation (10), the values of x and y are tabulated in Tables 1 and 2.
TABLE 1.--PARAMETER x______________________________________ j-i= 1 0 1 2 3 4 5 x= 0 3 6 11 12 5______________________________________
TABLE 2.--PARAMETER y______________________________________ i= 1 2 3 4 5 6 y= 14 13 12 11 10 9______________________________________ -
Using the above computed values of x and y, the error pattern ej is computed from the syndromes S1 and S2 according to equation (17). The erroneous bytes Z1 ' and Zj ' can then be corrected using the error pattern ej and the syndrome S1 to produce the corrected bytes Z1 and Zj since: ##EQU13##
In summary, the decoding process consists of:
1. Computing the syndromes S1 and S2 from the received message bytes Z1 ', Z2 ',...Zk ', C1 ', C2 ' according to equations (3) and (4).
2. Computing the error pattern ej from the syndromes S1 and S2 according to equation (17) with proper values of parameters x and y from precalculated tables.
3. Correcting the erroneous bytes with the error pattern ej and the syndrome S1 according to equations (21) and (22).
4. Detection of the uncorrectable errors according to the following:
4a. When more than two tracks are indicated as being in error, the code cannot provide reliable error correction.
4b. When two tracks are indicated as being in error, the error pattern bytes ei and ej have unique values.
4c. When exactly one track is indicated as being in error (the case where i is equal to j), then the error pattern byte ej must be 0 in all bit positions. If the computed ej is not 0 in all bit positions, then this is interpreted as detection of some other errors.
4d. When no track is indicated as being in error, then the syndromes S1 and S2 and, consequently, the error pattern bytes ei ej must be 0 in all bit positions. If not, this is interpreted as detection of errors.
Utilizing the previous example of 8-bit bytes, it can be seen from FIG. 2, that the data Z1, Z2,...Zk in forms of blocks of equal size bytes is received at the input 9 of the encoder 10. The received data is distributed by a data distributor to shift registers SR1 and SR2. The distributor 12 applies the incoming data to these shift registers in parallel. The shift registers SR1, SR2 perform the computations previously described to generate the check bytes C1 and C2. These check bytes are appended to the message data at the output 14 of the encoder 10. This encoded data is sent to the multi-track recorder or transmitter for utilization. FIGS. 4 and 5 show the shift registers SR1 and SR2, respectively. Each shift register contains 8 binary storage elements (0)...(7) with appropriate feedback connections and modulo 2 summing networks at each input stage. It is implied that with a time control signal, the shift register shifts the contents while simultaneously receiving the new input. Shift register devices of this type are widely known and given the feedback connection, it can be physically constructed from available logic hardware in many different ways.
Referring to FIG. 4, each input bit Z(0)...Z(7) of the 8-bit byte is applied to a separate modulo 2 summing circuit 16 at the input to each of the eight separate shift register storage elements 18. The output 20 of each binary storage element 18 is fed back via a feedback connection 22 to the modulo 2 adding circuit 16 at the input thereto along the with new input.
In FIG. 5, each of the 8-bits Z(0)...Z(7) of an 8-bit byte are shown as inputs to the modulo 2 adder circuits 20 - 27 at the input to each storage element of the shift register. The outputs 30 - 37 of each of the binary storage elements (0)...(7) are connected to certain ones of the modulo 2 adder circuits 20 - 27 in accordance with the columns of the matrix T8 68 which is given in equation (10). For example, the output 30 of the 0th storage element is connected back to the modulo 2 adder circuits 21 and 24 at the inputs of the first and fourth stages of the shift register. These connections are made in accordance with the 0th column of T8 68 which has 1's in the first and fourth positions. The new 8-bit vector input is entered into the register via the modulo 2 adding circuits 20 - 27 simultaneously with the feedback mentioned. If an 8-digit byte X represents the present contents of shift register SR1 and shift register SR2 and Y representing the input is entered with a shifting operation; then the next contents in shift register SR1 is Y⊕X and in shift register SR2 is Y⊕T8 68. X.
The information is entered into the shift registers SR1 and SR2 in reverse order, that is, Zk is entered first and Z1 is entered last. After the last byte Z1 has entered, the registers are shifted one more time with a 0 input.
The contents of shift register SR1 will be Z1 ⊕ Z2 ⊕ ...⊕ Zk which represents the first check byte. The contents of shift register SR2 will be T.sup.λ Z1 ⊕ T2.sup.λ Z2 ⊕...⊕ Tk.sup.λ Zk which is the second check byte. At the start time of the encoder 10, t0, the binary counter 40 is set to k + 1. The counter counts down in synchronism with the timing control signal. At count 0, the last shift of shift register SR1 and SR2 generates the respective check bytes. The count 0 signal obtained from the counter 40 closes the switches SW1 and SW2 after a unit time delay (during the next timing signal).
Referring to FIG. 3, the decoder 42 receives the encoded read or utilized message bytes Z1 ', Z2 ',...Zk ', C1 ', C2 ' and the pointers P1, P2 ,...Pk, P.sub. k+1, Pk +2 which indicate the tracks in error. The decoder 42 computes from these inputs the corrected data bytes Z1, Z2,...Z.sub. k or generates an uncorrectable error signal E. The symbol represents the corrected data.
The decoder 42 first computes the syndromes S1 and S2 in shift registers SR1 and SR2, as shown in FIGS. 4 and 5 from the read or received encoded message bytes Z1 ', Z2 ',...Zk ', C1 ', C2 ' according to equations (3) and (4). The message bytes Zk ', Zk -1 '...Z1 ' are applied to the shift registers SR1 and SR2 in that order by the read message distributor 44. Of course, the decoding is being performed to correct any errors that may have been introduced to the message as a result of the utilization thereof, either in the recorder or in the transmission with respect thereto. As each byte of the input message is received at the shift registers SR1 and SR2, the registers are simultaneously shifted by means of a time control signal. After the byte Z1 ' has entered, the byte C1 ' is entered into shift register SR1 and the byte C2 ' is entered into shift register SR2 while shifting the registers once. The contents of shift register SR1 is now C1 ' ⊕ Z1 ' ⊕ Z2 ' ⊕...⊕ Zk ' which is the syndrome S1. The contents of shift register SR2 is now C2 ' ⊕ T.sup.λ Z1 ' T2 .sup.λ Z2 ' ⊕...⊕ Tk.sup.λ Zk ' which is the syndrome S2. The syndrome generation is controlled by the timing control signal. The binary counter B1 is set to k + 1 at time t0 (starting time for the decoder) and counts down in synchronism with the timing control signals. At count 0, the last shift of shift registers SR1 and SR2 results in S1 as the contents of the shift register SR1 and S2 as the contents of shift register SR2.
The count 0 signal from the counter B1 starts counter B2 after a unit time delay, that is, with the next timing control signal. B2 is set to the binary value y at time t0. Counter B2 counts down in synchronism with the timing control signal which continuously shifts registers SR1 and SR2 also. At the count 0, in the counter B2, the switch SW1 is closed. This causes the contents of shift register SR1 which is S1 to enter shift register SR2. Accordingly, the contents of shift register SR2 is S1 ⊕Ty.sup.λ S2 and the contents of shift register SR1 remains S1.
The count 0 signal generated by counter B2 initiates B3 after a unit time delay, that is, with the next timing control signal. Counter B3 is set to the binary value x at time t0. Counter B3 counts down in synchronism with the timing control signal which continuously shifts registers SR1 and SR2. At the count 0 in the counter B3, the last shift of SR1 and SR2 produces Tx.sup.λ (S1 ⊕ Ty .sup.λ S2) as the contents of SR2 while the contents of shift registers SR1 remains S1.
The count 0 signal from the counter B3 closes the switches SW2 and SW3 after a unit time delay (with the next timing control signal). The switch SW3 is also controlled by the pointer signal Pk +2 as described later in connection with the error corrector circuit.
FIG. 6 shows schematically the error track parameters generator 46 which generates the parameters x and y as binary numbers from the input pointer signals P1, P2,...Pk, Pk +1, Pk +2. The error track parameters generator 46 also generates the new pointers I1, I2,...Ik identifying the first erroneous data track which is called the Ith track. It also generates the signals N0, N1, N3, indicating respectively, 0, 1 and more than 2 tracks in error. The error track parameters generator 46 of FIG. 6 indicates that the logic circuits 6a, 6b, 6c and 6d are included in order to obtain the above-noted outputs.
Referring to FIG. 6a, there is shown, the logic network connections for generating the I pointers I1...I6 which identifies the first erroneous data track called the Ith track. Combinations of the pointer signals P1 ...P6 are utilized as inputs to AND circuits 50. The combinations are arranged in successively increasing order of 1. For example, the grouping is P1, then P1, P2 followed by P1, P2, P3, etc. It should be observed that all of the inputs except the additional input in each of the combinations is inverted in a NOT circuit at the inputs to the respective AND circuits 50. It can be seen that as long as all the pointer inputs are 0, there will be no output from any of the AND circuits. However, the first non-zero pointer signal will be indicated by an output from its corresponding AND circuit. That is, the AND circuit 50 having that pointer as the additional pointer input.
FIG. 6b has as inputs the I pointers generated in FIG. 6a. This circuit generates the y parameters as a b-bit binary number y3, y2, y1, y0. The input combinations of the 1 pointers is determined according to Table 3. The logic connections can be determined by retabulating y as a b-bit binary number with the corresponding I pointers as shown in Table 3.
Table 3.-- Parameter y as a binary member______________________________________ y as binary numberi Indicated by y y3 y2 y1 y0______________________________________1 I1 14 1 1 1 02 I2 13 1 1 0 13 I3 12 1 1 0 04 I4 11 1 0 1 15 I5 10 1 0 1 06 I6 9 1 0 0 1______________________________________
Therefore, the signals y3, y2, y1 and y0 are generated from I1, I2,...I6. The input I pointer signals are combined into three groups of three and then a group of all six. These are inputted to OR circuits 52 which produce the y parameter outputs. It will be appreciated that y3 is always a logical one when any of the I signals is logical 1. y2 is a logical 1 when I1 or I2 or I3 is a logical 1. y0 is a logical 1 when I2 or I4 or I6 is a logical 1.
FIG. 6c shows a logic circuit diagram which generates the x parameters as a b-bit binary number x3, x2, x1, x0 from the P pointers. Before the x parameter can be generated, the (j-i) values must be generated from the track pointers P1, P2,...P6. This is accomplished by combining the P pointers into pairs of inputs to separate AND circuits 56. It can be seen that the input paired arrangement of pointers has the first group of pairs separated by the value 1, while the second group of pairs is separated by the value 2, the third group by the value 3, the fourth group by the value 4 and the last pair by the value 5. Each of these P pointer pairs is fed to respective AND circuits 56 whose outputs are inputted to appropriate OR circuits 58 to obtain the appropriate j-i value. For example, j-i = 1 is obtained from the OR circuit 58 connected to the AND circuits 56 having as inputs thereto the pairs separated by 1. Similarly, the other OR circuits 58 have connections thereto based on similar properties. For example, the second OR circuit 58 has an output value j-i = 2, while the third has a value j-i = 3 and the fourth has a value j-i = 4. Each of the j-i values are connected to the appropriate OR circuits 60. The connections for the associated functions are determined by means of Table 4 which is derived from Table 1. The procedure is similar to that in generating the connections for the previous parameter. The parameter x then is obtained as a b-bit binary number with signals x3, x2, x1, x0.
Table 4.-- Parameter x as a binary number______________________________________ x as a binary numberj-i Function x x3 x2 x1 x______________________________________0 or j=7 N1 +P7 0 0 0 0 01 P1 P2 +P2 P3 +P3 P4 +P4 P5 +P5 P6 3 0 0 1 12 P1 P3 +P2 P4 +P3 P5 +P4 P6 6 0 1 1 03 P1 P4 +P2 P5 +P3 P6 11 1 0 1 14 P1 P5 +P2 P6 12 1 1 0 05 P1 P6 5 0 1 0 1______________________________________
Note that Pk +2 does not participate in the determination of the values j-i. Also, j-i = 0 or j = k+2 does not generate logical 1 on any of the x0, x1, x2, x3 signal outputs.
FIG. 6d shows the circuit arrangement for generating the control signals N0, N1 and N3. N0 indicates that none of the track pointers P1, P2 ,...P.sub. k+2 are on. N1 indicates only 1 is on. N3 indicates that more than two track pointers are on. The N0 signal is generated as an output from an AND circuit 62 having the 8 pointer signals P1...P8 as inputs thereto. It can be seen that any one of the pointer inputs being on will cause no output from the AND circuit 62. Thus, the absence of N0 indicates that there is an energized track pointer. The N1 output is obtained from a `one and only one` circuit 64 which likewise has the pointers P1 through P8 as inputs thereto. The output N1 will only be obtained from circuit 64 when only one of the pointer inputs thereto is energized. The output N3 is obtained from a threshold network 66 which provides a logical one output when more than two of the inputs have logical 1's.
Referring to FIG. 7, there is shown the error corrector circuit 68 which produces the corrected data bytes Z1, Z2 ,...Zk by combining the read data bytes Z1 ', Z2 ' ,...Zk, the error pattern byte ej and the pointer signals I1,...Ik and P1...Pk. The combining is done in accordance with the equations (21) and (22). These two equations are interpreted as follows.
If j = k + 2, i.e., the pointer Pk +2 is on, then ej the output of SR2 should be inhibited. The inhibiting is done by AND gates (switch SW3) as shown in FIG. 3. Otherwise, ej is added (modulo 2) to the erroneous read bytes and S1 is added to the first erroneous read byte. This is accomplished by a set of 8 modulo 2 summing networks 70 and 2 sets of 8 AND gates 72,74 for each data byte Z1 ', Z2 ', Z3 ', Z4 ', Z5 ', Z6 ' as shown in FIG. 7. The first set of 8 AND gates 72 acts like a normally closed gate controlled by the corresponding track pointer signal and passes the ej byte only when that track pointer is on. The second set of 8 AND gates 74 are controlled by the corresponding I signal and pass syndrome S1 only when that I pointer is on. The set of 8 modulo 2 summing networks 70 combine the input signals Zi ', ej and S1 to produce the corrected byte Zi.
Referring to FIG. 8, there is shown the uncorrectable error indicator logic circuit 80 for detection of a large percentage of uncorrectable errors. This circuit generates an error indicator signal E when one of the following happens:
1. N3 is on indicating more than two tracks are in error. This can be seen from the N3 input to the last OR circuit 81.
2. N1 is on indicating that only one track is in error and the ej, the output of SR2, is not 0 in all bit positions. This is accomplished by having N1 and ej ≠ 0 signals as inputs to an AND circuit 82, the output of which forms one of the inputs to the OR circuit 81. The ej ≠ 0 signal is generated by an OR circuit 83 which receives all of the ej bits as its input.
3. N0 is on indicating that no track is in error when ej, the output of SR2, or S1, the output of SR1, is not 0 in all bit positions. This is accomplished by deriving an S1 ≠ 0 signal from OR circuit 85 which has all the bits of S1 as inputs thereto. The S1 ≠ 0 signal is applied as an input to AND circuit 84 along with the N0 input. The AND circuit 84 output is connected to OR circuit 81. The ej ≠ 0 signal and the N0 signal are connected as inputs to an AND circuit 86 whose output forms another input connection to OR circuit 81. Thus, any one of the inputs N0, N1 and N3, under the conditions enumerated above, produces an output signal E from OR circuit 81 indicating detection of uncorrectable errors.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification||714/755, 714/765|