|Publication number||USH2 H|
|Application number||US 06/559,630|
|Publication date||3 Dec 1985|
|Filing date||9 Dec 1983|
|Priority date||9 Dec 1983|
|Also published as||EP0164364A1, WO1985002704A1|
|Publication number||06559630, 559630, US H2 H, US H2H, US-H-H2, USH2 H, USH2H|
|Inventors||Gerald S. Soloway|
|Original Assignee||AT&T Technologies Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Non-Patent Citations (1), Referenced by (9), Classifications (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
This invention relates to video display systems and, more particularly, to an arrangement for improving the resolution of such systems.
2. Description of the Prior Art
Various information display systems have been proposed and used heretofore employing interactive computer systems wherein the user manipulates the information stored in or generated by a computer. This information may constitute text, graphics, facsimile, video and the like. In the recent past, the advent of very large scale integrated circuitry has made possible the wide use of low cost microprocessor systems. It is now considered cost effective to maintain central databases from which information can be accessed with such a system by the general public.
Two information display systems using central databases, viewdata and teletext, are presently being introduced in the telecommunications industry and have a potential for wide use. In the viewdata system, the consumer is provided a two-way interactive service capable of displaying pages of text and pictorial materials on a video display. In the teletext system, the consumer is provided with a one-way broadcast information service for displaying pages of text and graphic material on a video display.
In both the viewdata and teletext systems, it is necessary to include some type of electronics module at the consumer end with the display control information. One example of such a module is shown in U.S. Pat. No. 4,396,989, issued to J. R. Fleming et al. on Aug. 2, 1983, and is incorporated herein by reference. This type of module provides control to the consumer's display terminal (such as an ordinary television set) for assembling and displaying text and graphic information.
A common approach for displaying such text and graphic information is to use video display circuitry with a local video memory commonly referred to as a bit plane memory or full frame buffer. In that typical display terminals are configured to be refreshed on the order of 60 times per second, the local memory containing a description of the image can be maintained by external circuitry conveniently located in the electronic module. This avoids the need to rebroadcast the content of each screen full of information continuously, which, incidentally, requires very high bandwidth.
In presently existing viewdata and teletext systems utilizing a full frame buffer, the video memory is normally designed to have a given number N of bits per picture element (PEL) and hence be capable of displaying 2N colors. If a display of H horizontal PELs by V vertical PELs is desired, a video memory of N×H×V bits would be required. And if a display having a horizontal resolution of 2H is desired, twice as many bits would be required in the video memory.
The horizontal resolution of existing display devices is not easily expanded since the frequency of the horizontal scan is limited. This has led designers to constrain the number of horizontal PELs for display on a home television receiver to approximately 256, even though the display tube is capable of greater resolution. It is desirable, therefore, to be able to increase the horizontal resolution of a display device and thereby more fully utilize its resolution capability, but at the same time avoid the normal corresponding increases in horizontal frequency scan and video memory requirement.
In accordance with the present invention, an arrangement is provided which multiplies the apparent resolution of color video display systems without requiring that the size of the video memory be multiplied equivalently. This arrangement requires that one or more data bits be added to the video memory for each PEL in the display. With the additional one or more data bits, the decoding logic determines if the color information represented by the bits for the horizontal and vertical PELs is to be displayed on an existing boundary, as it would normally be without this arrangement, or be delayed by a fraction of the PEL clock cycle and plotted on an offset boundary.
This invention will be more fully comprehended from the following description and the accompanying drawing in which:
FIG. 1 shows the detail of an arbitrary line segment of PELs drawn using a standard bit plane;
FIG. 2 shows the detail of an arbitrary line segment of PELs drawn in accordance with one arrangement of the present invention;
FIG. 3 shows a schematic circuit diagram suitable for adapting an information display system for operation in accordance with the present invention; and
FIG. 4 is a timing diagram depicting waveforms of particular signals employed in this invention.
A common approach to displaying color images in a video display system is to have a description of the image maintained by a local memory. This local memory is conveniently associated with a display terminal and is usually referred to as video memory. In a bit plane or full frame buffer, the memory is organized to correspond on a one-for-one basis with the PELs in the display. For instance, if it is desirable to display an image using 256 horizontal PELs, by 200 vertical PELs in 16 colors, a memory organized as 256×200 addresses is typically used, where each address accesses 4 bits (24 =16). Synchronization and decoding logic sequentially accesses these memory locations in a read cycle of a reference clock. The 4-bit output is decoded by video drive circuitry during each read cycle into the color information signals required by the display terminal (for example, red, green and blue voltage levels).
Referring now to FIG. 1, there is shown a detail of an arbitrary line segment of PELs drawn using the conventional bit plane. In this figure, for each two vertical steps of V, a horizontal step H of the same size is taken resulting in a very jagged looking line. Thus, the resolution of the conventional bit plane limits the smoothness with which this image may be drawn.
FIG. 2 shows the detail of an arbitrary line segment of PELs drawn in accordance with the present invention with one bit added to the bit plane for each PEL. Although vertical steps of V remain the same size as before, the horizontal step size H is reduced by half, resulting in a much smoother looking image. Without this arrangement, the resolution in the horizontal direction would have to be doubled in order to achieve the same results. This is easily illustrated by reference to the earlier mentioned design example for displaying an image using 256 horizontal PELs by 200 vertical PELs in 16 colors. In that example, the memory required is 256×200×4 which is 204,800 bits. To obtain the same horizontal resolution with known arrangements, the memory size would have to double to 512×200×4 which is 409,600 bits. With the new arrangement, however, the memory is 256×200×5 or 256,000 bits, or only a 25-percent increase instead of 100 percent. The impact is even greater when more colors are used. For a display system using 256 colors and requiring 8 bits per PEL, the increment for the present arrangement is only 12.5 percent.
The additional bit is not used to describe color information, but rather is used to convey positional information as to how the bits of color information are to be interpreted. Positional information for a display is typically determined by the synchronization and decoding circuitry instead of being stored in a bit plane. In this arrangement, the additional bit is also located in the bit plane and is used by decoding logic to determine if the color information represented by the bits for the horizontal and vertical PELs is to be displayed on an existing boundary, as they would be in a conventional arrangement, or whether the color information should be delayed by a fraction of the PEL clock cycle and plotted on an offset boundary.
The circuit logic necessary to incorporate the present arrangement in an information display system is minimal and is illustrated in FIG. 3 for the case of one additional bit per PEL. Moreover, the additional logic provides the added benefit of ensuring that a given color index output is always present for a minimum of one clock cycle. This increased dwell time is often necessary to ensure that the frequency response of the visual display device (e.g., a TV receiver) is not exceeded.
With reference now to FIG. 3, a reference clock signal running at the PEL rate of N number of PELs per second is available on line 11 from the usual timing and synchronization circuits of an information display system. It is assumed that these circuits and decoding circuitry are also addressing the video memory 20 sequentially in synchronism with this clock signal, and that the output of the bit planes 21 through 24 is stable prior to the rising edge of the clock signal. This is easily achieved by delaying the clock signal on line 11 a little from the clock used to generate the memory addresses.
Positional information determining how the bits of color information should be interpreted is contained in bit plane 24 and provided over line 12 to an inverter 30, one of the two inputs of AND gate 31 and a flip-flop 40. When the positional information signal on line 12 is zero, AND gate 32 will have as inputs a logic one signal from inverter 30, the clock signal on line 11 and the Q output of D flip-flop 40. The clock signal on line 11 is also provided to the clock input of flip-flop 40 and the remaining input of AND gate 31 via inverter 33.
The positional information existing during each preceding clock cycle is reflected in the Q output of flip-flop 40. If Q is a logic one, reflecting that during the previous clock cycle the signal on line 12 was zero, then the output of AND gate 32 will go high during the rising edge of the clock signal and the appropriate color value will be loaded into register 60 via OR gate 34. The output of register 60 provides color index information to a color lock-up table 70 where the appropriate color is selected. A digital-to-analog converter 80 converts the digital output of the look-up table 70 to an analog signal used for driving the red, blue and green guns of a cathode ray tube display (not shown).
If the positional information signal on line 12 is a logical one, then the output of AND gate 31 will also go to a logic one at the middle of the clock cycle, loading the data into register 60 one-half clock cycle later than it would have if the positional information signal was a logic zero. If the positional information signal was logic one on the previous cycle, and is logic zero on the current cycle, no new color information is loaded. A truth table showing the effect of this logic on the output of register 60 is shown below where i is the current clock cycle and i-1 the previous. Pi is the positional bit output during clock cycle i, and Vi is the color value output during cycle i.
______________________________________Color IndexPi Pi + 1 Cycle i Cycle i + 1______________________________________0 0 Vi Vi Vi + 1 Vi + 10 1 Vi Vi Vi Vi + 11 0 Vi - 1 Vi Vi Vi1 1 Vi - 1 Vi Vi Vi + 1______________________________________
It should be noted that for case (Pi, Pi+1)=(1,0), Vi+1 is never provided as output since to do so, Vi would be provided as output for only one-half a clock cycle during the latter half of cycle i. Should the previously mentioned restriction on the duration of the color index output being at least one cycle not be required for a particular visual display device, then obvious simplifications to the logic and modifications to the truth table are possible.
FIG. 4 represents an illustrative timing diagram depicting waveforms of particular signals employed or generated by the circuit logic shown in FIG. 3. The clock waveform depicts the signal on line 11 from which all of the timing for the logic circuit is derived. Once each clock cycle, a memory address containing a color value (which may be several bits per PEL) and a positional bit P are accessed. As may be seen in FIG. 4, if P is a logic zero, the color value is latched in register 60 at the rising edge of the clock cycle and the color index output occurs approximately coincident with the leading edge of the clock. On the other hand if P is a logic one, the color value is latched at mid-cycle, resulting in the PEL corresponding to that cycle having shifted by 1/2 PEL. This ability to shift color information by 1/2 PEL provides the apparent increase in horizontal resolution.
Many modifications of this video display system are possible and may obviously be implemented by those skilled in the art without departing from the spirit and scope of the invention. An example of such a modification is a generalization of the above-described technique which would permit R bits of positional information to be stored for each PEL in the bit plane. These R bits would be sequentially accessed as previously, however, the R bits would be capable of describing 2R possible delays, instead of a single delay of one-half. For example, if R=2, four delays are possible. These would be 0, 1/4, 1/2, and 3/4 of a PEL. This would have the effect of increasing the apparent resolution by a factor of 4. If the mentioned design example of a display having 256×200 addresses is desired, but with 4 bits per PEL, quadrupling the resolution would require 1024×200×4 which is 819,200 bits. With the new arrangement, 256×200×6 or 307,200 bits are used. It is to be understood, therefore, that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.
|1||A Random-Access Video Frame Buffer, J. T. Kajiya, I. E. Sutherland, E. C. Cheadle, May 14-16, 1975, pp. 1-6; Publ. by IEEE Comput Soc.|
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|U.S. Classification||345/549, 345/698|
|International Classification||G09G5/391, G09G5/00, G09G5/06|
|Cooperative Classification||G09G5/391, G09G5/06|
|European Classification||G09G5/391, G09G5/06|