US9179586B2 - Method for assembling a chip in a flexible substrate - Google Patents

Method for assembling a chip in a flexible substrate Download PDF

Info

Publication number
US9179586B2
US9179586B2 US13/702,173 US201113702173A US9179586B2 US 9179586 B2 US9179586 B2 US 9179586B2 US 201113702173 A US201113702173 A US 201113702173A US 9179586 B2 US9179586 B2 US 9179586B2
Authority
US
United States
Prior art keywords
flexible substrate
area
chip
electronic chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US13/702,173
Other versions
US20130074331A1 (en
Inventor
Jean Brun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BRUN, JEAN
Publication of US20130074331A1 publication Critical patent/US20130074331A1/en
Application granted granted Critical
Publication of US9179586B2 publication Critical patent/US9179586B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a permanent auxiliary member being left in the finished device, e.g. aids for protecting the bonding area during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/809—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding with the bonding area not providing any mechanical bonding
    • H01L2224/80901—Pressing a bonding area against another bonding area by means of a further bonding area or connector
    • H01L2224/80903—Pressing a bonding area against another bonding area by means of a further bonding area or connector by means of a bump or layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H05K1/0281—Reinforcement details thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/038—Textiles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A substrate provided with an electrically conducting wire coated with an electrically insulating material is impregnated with a polymerizable material. A reception area for a chip is formed on a surface of the substrate by means of deformation. The housing area is stiffened using the polymerizable material. The chip is disposed in the reception area and an electrical connection area of the chip is connected electrically to the electrically conducting wire of the substrate.

Description

BACKGROUND OF HE INVENTION
The invention relates to a method for assembling an electronic chip on a substrate.
STATE OF THE ART
In order to conquer new markets, the electronics sector has modified conventional electronic chips so that they are able to stand up to increasingly hostile environments. However, the field of flexible supports is a sector for which numerous problems remain outstanding.
In the field of integration of electronic functions on flexible substrates such as textiles, the problems mainly originate from the flexibility of the substrate itself.
In so far as the chips cannot be produced directly on the flexible substrate, the electronic chips are produced separately and then assembled on this particular substrate.
There again, when it is sought to connect one or more electronic chips to a substrate, conventional assembly methods are ineffective as they require a certain rigidity of the substrate and/or a certain thermal resistance. It is further advantageous to connect the chip to another device, for example another chip or a passive element, which complicates fabrication.
Integration of electronic chips with a textile provided with conducting thread-like wires provides numerous solutions. The textile acts as a flexible substrate and the conducting wires enable the chip to be connected with an outside element.
Examples of production are described in the document US 2004/0074660 and in the document US 2006/0258205. In these two documents, the chip or an adapter are connected to the textile, which gives rise to problems in alignment of the different connections between the chip (adapter) and the textile. In the document US 2004/0074660, the resin is injected once connection has been established in order to perform sealing of the chip with the textile.
It has been proposed to connect a chip to a conducting wire by means of a lateral groove which runs along a side wall of the chip. This method is very difficult to implement and furthermore requires the dimension of the groove to be made to match the diameter of the wire.
In the document WO 2005/067042, several chips formed on a rigid substrate are placed in connection with a textile comprising electric wires. In this embodiment, the advantage of the conducting flexible substrate is lost as the assembly is finally rigid on account of the substrate connecting the different chips. In the document JP 04290478, a rigid substrate is formed by a textile adhering to a supporting plate. The textile comprises conducting wires which are used to supply light-emitting diodes. There again, the advantages of the flexible substrate are lost on account of the rigid supporting plate.
OBJECT OF THE INVENTION
It has been ascertained that a requirement exists to provide a method for assembling an electronic chip with a substrate that is easy to implement and that ensures good mastery of the alignment between the substrate and the chip.
This requirement tends to be met by means of the method according to the appended claims and more particularly by means of a method comprising the following steps:
    • providing a flexible substrate provided with at least one electrically conducting wire and with a polymerizable material,
    • making the polymerizable material react in a first area of the substrate so as to rigidify this first area of the substrate and to form a housing area of the chip on a surface of the substrate, the housing area representing a more rigid area of the substrate,
    • arranging the chip in the housing area and electrically connecting the electrically conducting wire with an electric connection area of the chip.
BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages and features will become more clearly apparent from the following description of particular embodiments of the invention, given for non-restrictive example purposes only and represented in the appended drawings, in which:
FIG. 1 represents two chips mounted on a substrate, in schematic manner in top view,
FIGS. 2 to 4 represent a method for assembling a chip on a substrate, in schematic manner in cross-section,
FIGS. 5 and 6 represent a second method for assembling a chip on a substrate, in schematic manner in cross-section,
FIG. 7 represents a step of an alternative embodiment of an assembly method, in schematic manner in cross-section,
FIGS. 8 and 9 represent steps of another alternative embodiment of an assembly method, in schematic manner in cross-section,
FIGS. 10 and 11 represent steps of a third alternative embodiment of an assembly method, in schematic manner in cross-section,
FIG. 12 represents another embodiment of two chips mounted on a substrate, in schematic manner in top view.
 DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
As illustrated in FIG. 1, substrate 1 on which chip 2 has to be assembled is a flexible substrate which comprises at least one electrically conducting wire 3. In certain embodiments, wire 3 is totally or partially coated by an electrically insulating material. In other embodiments, electrically conducting wire 3 is not coated by an electrically insulating material.
In a particular embodiment, substrate 1 comprises a plurality of electrically conducting wires 3. Electrically conducting wires 3 can be contained in a single plane inside the substrate, but it is also conceivable to have wires 3 arranged in several parallel planes. For example purposes, substrate 1 comprises two series of wires which represent two parallel planes inside substrate 1.
In an alternative embodiment which can combined with the previous embodiments, substrate 1 also comprises a plurality of electrically non-conducting wires. According to the embodiments used, the wires used are woven or not. The electrically conducting wires can all be oriented in the same direction. It is also conceivable for the conducting wires to be arranged in several directions and organized for example in a matrix.
For example purposes, substrate 1 is a textile comprising wires 3 woven together inside which there exists at least one electrically conducting wire. In another example, substrate 1 comprises a support film which is covered by a conducting wire 3. Substrate 1 is also a film made from electrically insulating material inside which one or more wires 3 are sunk. Mechanical securing between the wires (conducting or not) can be performed by the support film or by means of the different mechanical connections existing between the different wires.
According to the embodiments used, electrically conducting wire 3 can be sheathed in the electrically insulating material, the assembly keeping the form of a wire, or it can be in a layer of insulating material.
When conducting wire 3 is coated by an insulating material and keeps the form of a wire, the conducting wire which is electrically insulated from the other wires can be used in a woven structure as weft thread or warp thread.
The electrically conducting wire is for example covered by an electrical insulator. It is also conceivable to incorporate an electrically conducting wire covered by an insulating layer inside a substrate that is itself electrically insulating. When the electrically conducting wire is integrated without an insulator, insulation is obtained by the structure of the substrate.
A housing area 5 is then formed on the substrate so as to house chip 2. Housing area 5 for chip 2 represents a more rigid area of substrate 1. This greater rigidity enables the chip to be placed more easily in the housing area thereby preventing too great a deformation of the substrate and of the conducting wire with respect to the chip. In this manner, it is easier to align the chip with the substrate. This is particularly efficient when the chip is integrated on a flexible substrate.
A portion of the substrate can be rigidified by different techniques to form the housing area, for example by means of a polymerizable material 4 which will react to rigidify the housing area. It is also possible to use an external strengthener which rigidifies the substrate preventing too great a deformation when the chip is placed. It is also conceivable to modify the mechanical behaviour of the housing area in temporary or permanent manner by means of an optic, magnetic and/or electric stimulus.
In this manner, as illustrated, the flexible substrate comprises a rigid area which is adjacent to a flexible area or surrounded by flexible area. The two areas present different mechanical properties. This difference of behaviour can originate for example from a difference of Young's modulus between the material forming the rigid housing area and the material of the adjacent flexible substrate. The Young's modulus of the housing area is higher than the Young's modulus of the rest of the flexible substrate. The rigid area thus facilitates precise positioning of the chip with respect to the electrically conducting wire and the flexible area enables the advantages of the original substrate to be preserved.
In a privileged embodiment, housing area 5 is associated with a deformation of the substrate. This deformation facilitates placing of the chip with respect to its environment, for example with respect to one or more wires 3.
If substrate 1 is deformed in order to form housing area 5 for electronic chip 2, this housing area 5 can be sunken or salient with respect to the rest of substrate 1. According to the embodiments, sunken or salient housing area 5 corresponds to the surface of chip 2, or represents a larger surface than chip 2, which can facilitate positioning thereof or enable assembly of two chips side by side. The housing area can also correspond to a smaller surface than the chip, if the housing area is salient.
Deformation of substrate 1 can be obtained by any suitable technique. As illustrated in FIG. 2, deformation can be achieved by means of die-stamping of the substrate between two half-matrices 6.
According to the patterns formed in half-matrices 6, the opposing surfaces of substrate 1 can present salient or sunken areas with any shapes. Formation of a salient or sunken housing area 5 is achieved in conventional manner according to conventional die-stamping techniques.
According to the half-matrices used, substrate 1 presents a sunken area, two sunken areas facing one another on each side of the substrate or a sunken area facing a salient area. In the example illustrated in FIG. 3, two sunken areas are facing one another.
When substrate 1 is a flexible substrate, it is difficult for the substrate to keep a predefined shape of housing area 5. It is then advantageous to use a substrate comprising a polymerizable material 4 or any other material which can locally rigidify the substrate. The polymerizable material can be an intrinsic constituent of the substrate or it can be added onto the substrate, for example by impregnation or by deposition of a polymerizable material on the substrate. The impregnation or deposition can be generalized or only localized to the future housing area of the chip. When polymerization of the polymerizable material is performed, the mechanical properties of the latter are modified so as to make it more rigid. Transformation of the polymerizable material enables the substrate to be rigidified. The same is true for the other materials that can be used.
According to the porosity of substrate 1 and its affinity with polymerizable material 4, substrate 1 can be modified locally in its chemical composition and in its mechanical strength. If not, polymerizable material 4 can form a rigid layer on the surface of flexible substrate 1 so as to prevent subsequent deformation.
As illustrated in FIG. 3, once housing area 5 has been formed, polymerizable material 4 is treated so as to make it react. Substrate 1 is then rigidified at least at the level of housing area 5 of chip 2. Polymerization of polymerizable material 4 can be achieved by any suitable technique, for example by means of heat treatment or by means of illumination under electromagnetic or electronic radiation.
Rigidifying of housing area 5 is preferably performed as soon as possible after deformation of the latter in order to avoid a change of shape. In preferential manner, transformation of polymerizable material 4 is at least partially performed when pressing or die-stamping, is performed, in order to keep a footprint that is as close as possible to what is required in substrate 1.
As illustrated in FIG. 4, in a particular embodiment, once substrate 1 has been rigidified at the level of housing area 5, chip 2 is arranged on housing area 5. The main surface of chip 2 is placed in contact with the substrate and the latter are secured to one another. This securing of chip 2 with substrate 1 is performed by any suitable technique, or example by gluing, by embedding the chip in its housing area or by mechanical securing between the chip and a cooperating element arranged on the opposite surface of the substrate.
In another embodiment illustrated in FIGS. 5 and 6, it is also possible to perform pressing of substrate 1 directly by means of chip 2. The main surface of chip 2 is placed in contact with the main surface of substrate 1 and a pressure is applied. Substrate 1 then deforms to take exactly the same shape as chip 2. Advantageously, a counter-plate 7 is used in order to master deformation of housing area 5 better. This deformation can be definitive or provisional. The pressure applied is advantageous to ensure an efficient mechanical contact between substrate 1 and chip 2.
As for die-stamping, various forms of footprints are accessible on one or two surfaces of substrate 1. In this particular case, formation of housing area 5 and placing of chip 2 are performed simultaneously. In an alternative embodiment, substrate 1 is at least locally rigidified by a polymerizable material 4 or by another technic so as to preserve the shape of housing area 5 once the pressing step has been terminated.
In other embodiments, rigidification of the housing area is linked to the use of a counter-plate 7. It is then not necessary to use a polymerizable material. Counter-plate 7 is associated with the substrate which has the effect of defining a more rigid area, housing area 5. The chip is then arranged on the substrate at the level of housing area 5. Chip 2 and counter-plate 7 are separated by substrate 1.
Chip 2 is electrically connected to substrate 1. An electric connection area 8 arranged on the main surface of chip 2 is in electric contact with an electrically conducting wire 3 of substrate 1. Electric contact area 8 of chip 2 is for example an area that is salient from the main surface of chip 2, or on the contrary an area that is sunken with respect to this same surface. Electric contact area 8 can be achieved by micro-inserts, by bumps made from fusible metallic material or by stud-bumps, i.e. bumps of particular shape. Electric connection can also be made by a conducting glue, preferably a conducting anisotropic glue. Conducting wire 3 of substrate 1 enables power supply and/or communication of chip 2 with another element electrically connected to substrate 1, a chip or a passive element.
When placing of chip 2 is performed in its housing area 5, the pressure exerted by the chip on the substrate enables electric contact between an electrically conducting wire 3 and electric connection area 8 to be ensured.
The salient connection areas enable the insulating material coating the electrically conducting wire to be pierced thus at least partially baring the latter. In preferential manner, the electric connection areas that are salient from the main surface of the chip have a pointed shape and/or a diameter smaller than or equal to 30 micrometers which facilitates penetration of salient area 8 up to conducting wire 3.
According to another embodiment, an additional chemical, ion or mechanical etching step is performed in order to form the contact areas without baring wire 3.
A sunken connection area, i.e. inside the chip, can also connect an electrically conducting wire 3 by taking advantage of the deformation of the conducting wire caused by counter-plate 7.
In order to obtain contact between an electric connection area 8 and an electrically conducting wire 3, housing area 5 has to be located according to the electrically conducting wires and the electric connection areas of the chip.
In another embodiment illustrated in FIG. 7, access to the electrically conducting wire can be achieved by means of an additional step which consists in chemical etching and/or ion etching and/or mechanical etching of the insulating material situated facing the future electric connection area. In the illustrated embodiment, access to the conducting wire 3 is achieved by passing through the substrate and by stopping at the level of counter-plate 7. It is also possible not to use a counter-plate 7 or to also etch counter-plate 7 to obtain a pass-through contact.
Depending on the etching technique used, the conducting wire is eliminated at the same time as the rest of substrate 1 and connection area 8 then fills the void area that is created. Electric contact is obtained by means of the lateral surface of the electric wire and the connection area ensures continuity of the signal in the rest of the electric wire. In another alternative embodiment, conducting wire 3 is not or not completely eliminated during elimination of the substrate 1. The insulating layer coating the conducting wire is for the most part eliminated.
Chip 2 can comprise one or more additional electric connection areas 8 (FIG. 1). The pitch between two active electric connection areas 8 is free and is a function of the pitch existing between the wires.
Inversely, if substrate 1 comprises several electrically conducting wires 3, the distance between two parallel or substantially parallel conducting wires 3 has to be compatible with the distance existing between two electric connection areas 8.
In the case where several electric connection areas 8 are connected to a single conducting wire 3, conducting wire 3 can be cut between two chips or between two connection areas of the same chip in order to prevent any short-circuiting (FIG. 1). The wire is cut by any suitable technique, for example by means of a punch or by a laser beam.
In certain embodiments, counter-plate 7 is only used in the substrate deformation step and, in this case, it is not present in the final device. In other embodiments, it can also act as mechanical strengthener for chip 2 and/or for substrate 1, counter-plate 7 then being secured to the electronic chip. Counter-plate 7 and chip 2 are located on either side of substrate 1.
In an alternative embodiment, counter-plate 7 is formed by an additional electronic chip 2 which is mechanically connected to substrate 1 and to first chip 2. In preferential manner, the two chips 2 are electrically connected to one another. This electric connection can be achieved directly by electric connection areas 8 having complementary shapes which face one another. In this case, there is no passage via wire 3 for connection between the two chips. This electric connection can also be made by passing via one more electrically conducting wires 3. The electric connections between the two chips 2 are then advantageously located in the facing surface of the two chips 2.
Mechanical connection between electronic chip 2 and counter-plate 7 can be made by any suitable means, for example by means of a glue or of forcibly engaged structures.
In another embodiment illustrated in FIGS. 8 and 9 and which can be combined with the previous embodiments, housing area 5 of chip 2 is made by means of counter-plate 7, by pressing counter-plate onto the substrate. The substrate is deformed and the counter-plate defines a salient area on the opposite surface to the one comprising the counter-plate (FIG. 8). It is also conceivable for the counter-plate to comprise one or more salient patterns. The salient housing area can be of any shape. It can have the same pattern as that of the counter-plate. It is further conceivable for salient patterns of counter-plate 7 to pass through substrate 1 or to print raised patterns on housing area 5 which act as error preventers imposing the position and orientation of chip 2 to be subsequently assembled (FIG. 9).
As illustrated in FIGS. 9 and 10, alignment of chip 2 with respect to counter-plate 7 can be achieved with a housing area salient from substrate 1 (FIG. 9) or in the volume of the substrate (FIG. 10). The counter-plate can also be used for formation of a housing area associated with two adjacent chips. Counter-plate 7 can advantageously be used to align the two chips 2 with respect to one another and with respect to wires 3.
Once chip 2 has been aligned on wires 3 of the flexible substrate and secured to the substrate, counter-plate 7 can be removed by any suitable technique. Counter-plate 7 can also be kept.
Thus, by aligning counter-plate 7 provided with error preventers with respect to conducting wire 3, alignment of chip 2 with respect to conducting wire 3 is automatic. The error preventer can also form an electric connection area.
Pressing of the counter-plate results in deformation of the substrate either to form a salient housing area or for passage of one or more error preventers through the substrate.
To ensure electric connection between a conducting wire 3 and an electric connection area 8, it is preferable to perform alignment of chip 2 with respect to conducting wire 3. This alignment can be performed when definition of housing area performed or when placing of chip 2 in housing area 5 is performed.
In a particular embodiment illustrated in FIG. 1, two chips 2 each having several connection areas 8 are integrated on substrate 1. To obtain easy and effective communication between these two chips, electric connection areas of these two chips are connected to a single conducting wire. On the other hand, to prevent any short-circuiting between two areas 8 not having to communicate with one another but nevertheless connected to the same wire 3, the electrically conducting wire simply has to be locally etched.
In this manner, it is easy to assemble different chips on a flexible substrate and to associate the latter to form specific functions according to the wires shared between the chips and the cutting areas.
In the embodiments illustrated in FIGS. 8 to 11, conducting wire 3 and electric connection contact 8 are not represented in the cross-sectional view. They can be represented in similar manner to the previous views, but it is also possible for connection to take place in another plane that is not shown. In the latter case, the deformations present in housing area 5 act as error preventer.
In another embodiment illustrated in FIG. 12, electrically conducting wires 3 are organized in matrices, i.e. there are at least two series of differently oriented wires, preferably in perpendicular directions. One or more chips present a plurality of electric connection areas 8. Certain connections 8 are electrically associated with wires oriented in a first direction whereas other connections of the same chip are electrically associated with wires oriented in a second direction.
Depending on the associations that are sought to be made, electrically conducting wires 3 that are facing chip 2 can be connected or left free. One and the same wire 3 can be connected to several connection areas 8 of chip 2. If different signals have to transit in different areas of one and the same wire, the wire is cut to prevent creation of parasite signals. For example purposes, the electric wire is cut at the level of the chip between two consecutive connection areas 8 if the signal input to the chip via a first area 8 is re-injected after processing by a second area 8 on the same wire 3 in the direction of another chip.
In a particular embodiment, the substrate comprises a plurality of electrically conducting wires arranged in two parallel planes. The wires can be arranged in any manner in each plane. Each series of wires can be oriented in a single direction, these two directions being parallel or not. It is also conceivable to have a matrix organisation of wires 3 of each plane.
When chip 2 is electrically connected to substrate 1, connection can be made on one of the planes of wires 3 or on both planes of wires 3. In a particular embodiment, an electric connection area 8 of chip 2 performs simultaneous connection of two wires 3 present on two different planes at the level of a superposition area.
In another embodiment which can be combined with the previous embodiment, the chip comprises means for making an interconnection between two superposed wires. An interconnection can be made by means of a pressure exerted on two superposed wires in order to force electric connection of the latter. Interconnection can also be achieved by means of an electric contact originating from the chip and which directly touches the two electrically conducting wires 3.
This interconnection between two wires 3 can be electrically connected to chip 2 or not.
The method is particularly advantageous in the case of use of a substrate of textile type as the latter is particularly sensitive to deformation when placing of chip is performed. Rigidifying the housing area enables the deformations to be reduced thereby mastering alignment of the chip with respect to the conducting wire.

Claims (19)

The invention claimed is:
1. A method for assembling an electronic chip on a flexible substrate comprising the successive following steps:
providing the flexible substrate provided with at least one electrically conducting wire and with a polymerizable material;
making the polymerizable material react in a first area of the flexible substrate so as to stiffen this first area of the flexible substrate and not to react in a second area of the flexible substrate, the first area forming a housing area for the electronic chip on a surface of the flexible substrate, the housing area representing a more rigid area of the flexible substrate as compared to the second area; and
arranging the electronic chip in the housing area and electrically connecting the at least one electrically conducting wire with an electric connection area of the chip.
2. The method according to claim 1, further comprising impregnating the flexible substrate by the polymerizable material before forming the housing area.
3. The method according to claim 1, wherein the polymerizable material is an epoxy resin.
4. The method according to claim 1, further comprising a counter-plate that is an additional electronic chip electrically coupled with the electronic chip.
5. The method according to claim 1, wherein the electric connection area of the chip is salient from a main surface of the electronic chip.
6. The method according to claim 1, wherein the flexible substrate is a textile.
7. The method according to claim 1, wherein the substrate comprises a plurality of electrically conducting wires arranged in two parallel planes and in that the chip is electrically connected to one of the plurality of electrically conducting wires of each plane.
8. The method according to claim 7, wherein the electronic chip comprises a salient part configured for applying pressure on two superposed electrically conducting wires to form an interconnection between said two superposed electrically conducting wires.
9. A method for assembling an electronic chip on a flexible substrate comprising the following steps:
providing the flexible substrate provided with at least one electrically conducting wire and with a polymerizable material;
making the polymerizable material react in a first area of the flexible substrate so as to stiffen this first area of the flexible substrate and to form a housing area for the electronic chip on a surface of the flexible substrate;
arranging the electronic chip in the housing area and electrically connecting the at least one electrically conducting wire with an electric connection area of the chip and with an additional electric connection area of the electronic chip; and
cutting the at least one electrically conducting wire between the electric connection area of the electronic chip and the additional electric connection area of the electronic chip.
10. The method according to claim 9, wherein the cutting is performed by a punch or a laser beam.
11. A method for assembling an electronic chip on a flexible substrate comprising the following steps:
providing the flexible substrate provided with at least one electrically conducting wire and with a polymerizable material;
making the polymerizable material react in a first area of the flexible substrate so as to stiffen this first area of the flexible substrate and not to react in a second area of the flexible substrate, the first area forming a housing area for the electronic chip on a surface of the flexible substrate, the housing area representing a more rigid area of the flexible substrate as compared to the second area; and
pressing and securing the electronic chip against a counter-plate, the electronic chip being arranged in the housing area and electrically connecting the at least one electrically conducting wire with an electric connection area of the chip.
12. The method according to claim 11, wherein the counter-plate is an additional electronic chip electrically coupled with the electronic chip.
13. A method for assembling an electronic chip on a flexible substrate comprising the following steps:
providing the flexible substrate provided with at least one electrically conducting wire and with a polymerizable material;
deforming a portion of the flexible substrate comprising the polymerizable material;
making the polymerizable material react in a first area of the deformed portion of the flexible substrate so as to stiffen this first area of the flexible substrate and to form a housing area for the electronic chip on a surface of the flexible substrate; and
arranging the electronic chip in the housing area and electrically connecting the at least one electrically conducting wire with an electric connection area of the chip.
14. The method according to claim 13, further comprising pressing a counter-plate onto the flexible substrate for deforming the portion of the flexible substrate comprising the polymerizable material and removing the counter plate before arranging the electronic chip in the housing area.
15. The method according to claim 13, further comprising pressing a counter-plate onto the flexible substrate for deforming the portion of the flexible substrate comprising the polymerizable material and removing the counter plate after arranging the electronic chip in the housing area.
16. The method according to claim 13, further comprising pressing a counter-plate onto the flexible substrate for deforming the portion of the flexible substrate and wherein the counter-plate comprise at least one salient part configured for cooperating with a recessed part of the electronic chip.
17. The method according to claim 13, wherein the deforming is performed by die-stamping the flexible substrate between two half-matrices.
18. The method according to claim 13, further comprising pressing the electronic chip onto the flexible substrate for deforming the portion of the flexible substrate comprising the polymerizable material.
19. The method according to claim 13, further comprising pressing the electronic chip by means of a counter-plate for deforming the portion of the flexible substrate comprising the polymerizable material.
US13/702,173 2010-07-06 2011-07-05 Method for assembling a chip in a flexible substrate Expired - Fee Related US9179586B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1002846 2010-07-06
FR1002846A FR2962593B1 (en) 2010-07-06 2010-07-06 METHOD FOR ASSEMBLING A CHIP IN A FLEXIBLE SUBSTRATE
PCT/FR2011/000395 WO2012007655A1 (en) 2010-07-06 2011-07-05 Method for assembling a chip in a flexible substrate

Publications (2)

Publication Number Publication Date
US20130074331A1 US20130074331A1 (en) 2013-03-28
US9179586B2 true US9179586B2 (en) 2015-11-03

Family

ID=43587503

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/702,173 Expired - Fee Related US9179586B2 (en) 2010-07-06 2011-07-05 Method for assembling a chip in a flexible substrate

Country Status (6)

Country Link
US (1) US9179586B2 (en)
EP (1) EP2591498A1 (en)
JP (1) JP5951602B2 (en)
CN (1) CN102971841A (en)
FR (1) FR2962593B1 (en)
WO (1) WO2012007655A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150024589A1 (en) * 2012-01-31 2015-01-22 Commissariat A L'energie Atomique Aux Energies Alternatives Method for assembling a microelectronic chip element on a wire element, and installation enabling assembly to be performed
US10499502B2 (en) * 2015-01-27 2019-12-03 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Flexible device module for fabric layer assembly and method for production

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2955972B1 (en) * 2010-02-03 2012-03-09 Commissariat Energie Atomique METHOD FOR ASSEMBLING AT LEAST ONE CHIP WITH A FABRIC INCLUDING A CHIP DEVICE
GB2500380A (en) 2012-03-18 2013-09-25 Effect Photonics B V Arrangement and method of making electrical connections
EP2957154B1 (en) 2013-02-15 2018-11-07 IMEC vzw Textile integration of electronic circuits
US9801277B1 (en) * 2013-08-27 2017-10-24 Flextronics Ap, Llc Bellows interconnect
WO2016093210A1 (en) 2014-12-08 2016-06-16 株式会社フジクラ Stretchable substrate
CN105047676A (en) * 2015-09-06 2015-11-11 京东方科技集团股份有限公司 Packaging flexible substrate and packaging body
EP3483929B1 (en) * 2017-11-08 2022-04-20 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with electrically conductive and insulating layers and a component embedded therein and manufacturing method thereof
US11022580B1 (en) 2019-01-31 2021-06-01 Flex Ltd. Low impedance structure for PCB based electrodes
EP3735111A1 (en) * 2019-05-03 2020-11-04 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with deformed layer for accommodating component
US11668686B1 (en) 2019-06-17 2023-06-06 Flex Ltd. Batteryless architecture for color detection in smart labels
CN112839425A (en) * 2019-11-25 2021-05-25 浙江荷清柔性电子技术有限公司 Flexible circuit board and flexible chip packaging structure

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290478A (en) 1991-03-19 1992-10-15 Denki Kagaku Kogyo Kk Matrix circuit board, its manufacture and display board
JPH0536868U (en) 1991-10-11 1993-05-18 スタンレー電気株式会社 Circuit board
US5401922A (en) * 1993-02-22 1995-03-28 Illinois Tool Works Inc. Membrane switch
DE19755792A1 (en) 1997-12-16 1999-06-24 Titv Greiz Flat textile structure of bonded insulating textile layers contains microstructured wiring
US6326544B1 (en) * 1996-02-05 2001-12-04 Micron Technology, Inc. Polymer based circuit
US20040074660A1 (en) 1999-12-16 2004-04-22 Akio Nakamura Cross substrate, method of mounting semiconductor element, and semiconductor device
DE10307505A1 (en) 2003-02-21 2004-09-09 Infineon Technologies Ag Textile fabric structure, surface covering structure and method for determining a distance from microelectronic elements of the textile fabric structure to at least one reference position
US20040244193A1 (en) 2003-06-06 2004-12-09 Infineon Technologies Ag Method of making contact with conductive fibers
US20040259391A1 (en) 2001-12-14 2004-12-23 Infineon Technologies Ag Construction and connection technique in textile structures
WO2005067042A1 (en) 2004-01-12 2005-07-21 Infineon Technologies Ag Method for electrically connecting an electrical conductor to an electronic component, and device
US20060254811A1 (en) 2005-05-13 2006-11-16 Tunde Kirstein Circuit board and method for its production
US20060258205A1 (en) 2005-05-13 2006-11-16 Ivo Locher Textile comprising a conductor line system and method for its production
WO2008120138A1 (en) 2007-03-29 2008-10-09 Koninklijke Philips Electronics N.V. Electronic assembly for attachment to a fabric substrate, electronic textile, and method of manufacturing such an electronic textile
US7447551B2 (en) * 2004-12-30 2008-11-04 Industrial Technology Research Institute Flexible implantable electrical stimulator array
US7444733B2 (en) * 2005-08-30 2008-11-04 Industrial Technology Research Institute Alignment precision enhancement of electronic component process on flexible substrate device and method thereof the same
US20090050352A1 (en) * 2007-08-20 2009-02-26 Industrial Technology Research Institute Substrate structures for flexible electronic devices and fabrication methods thereof
WO2010058360A1 (en) 2008-11-21 2010-05-27 Koninklijke Philips Electronics N.V. Textile electronic arrangement
US20130176737A1 (en) * 2010-09-21 2013-07-11 Koninklijke Philips Electronics N.V. Electronic textile and method of manufacturing an electronic textile

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4290478B2 (en) 2003-05-20 2009-07-08 株式会社コーワ Brush pieces for cleaning brush

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290478A (en) 1991-03-19 1992-10-15 Denki Kagaku Kogyo Kk Matrix circuit board, its manufacture and display board
JPH0536868U (en) 1991-10-11 1993-05-18 スタンレー電気株式会社 Circuit board
US5401922A (en) * 1993-02-22 1995-03-28 Illinois Tool Works Inc. Membrane switch
US6326544B1 (en) * 1996-02-05 2001-12-04 Micron Technology, Inc. Polymer based circuit
DE19755792A1 (en) 1997-12-16 1999-06-24 Titv Greiz Flat textile structure of bonded insulating textile layers contains microstructured wiring
US20040074660A1 (en) 1999-12-16 2004-04-22 Akio Nakamura Cross substrate, method of mounting semiconductor element, and semiconductor device
US20040259391A1 (en) 2001-12-14 2004-12-23 Infineon Technologies Ag Construction and connection technique in textile structures
US20060035554A1 (en) 2003-02-21 2006-02-16 Infineon Technologies Ag Textile fabric structure
DE10307505A1 (en) 2003-02-21 2004-09-09 Infineon Technologies Ag Textile fabric structure, surface covering structure and method for determining a distance from microelectronic elements of the textile fabric structure to at least one reference position
US20040244193A1 (en) 2003-06-06 2004-12-09 Infineon Technologies Ag Method of making contact with conductive fibers
EP1489696A2 (en) 2003-06-06 2004-12-22 Infineon Technologies AG Method for contacting conductive fibers
WO2005067042A1 (en) 2004-01-12 2005-07-21 Infineon Technologies Ag Method for electrically connecting an electrical conductor to an electronic component, and device
US7447551B2 (en) * 2004-12-30 2008-11-04 Industrial Technology Research Institute Flexible implantable electrical stimulator array
US20060254811A1 (en) 2005-05-13 2006-11-16 Tunde Kirstein Circuit board and method for its production
US20060258205A1 (en) 2005-05-13 2006-11-16 Ivo Locher Textile comprising a conductor line system and method for its production
EP1727408A1 (en) 2005-05-13 2006-11-29 Eidgenössische Technische Hochschule Zürich Textile with conductor pattern and method for its production
JP2006332647A (en) 2005-05-13 2006-12-07 Sefar Ag Circuit board and method of manufacturing the same
US7444733B2 (en) * 2005-08-30 2008-11-04 Industrial Technology Research Institute Alignment precision enhancement of electronic component process on flexible substrate device and method thereof the same
US20090026678A1 (en) * 2005-08-30 2009-01-29 Industrial Technology Research Institute Alignment precision enhancement of electronic component process on flexible substrate device and method thereof the same
WO2008120138A1 (en) 2007-03-29 2008-10-09 Koninklijke Philips Electronics N.V. Electronic assembly for attachment to a fabric substrate, electronic textile, and method of manufacturing such an electronic textile
US20090050352A1 (en) * 2007-08-20 2009-02-26 Industrial Technology Research Institute Substrate structures for flexible electronic devices and fabrication methods thereof
WO2010058360A1 (en) 2008-11-21 2010-05-27 Koninklijke Philips Electronics N.V. Textile electronic arrangement
US20130176737A1 (en) * 2010-09-21 2013-07-11 Koninklijke Philips Electronics N.V. Electronic textile and method of manufacturing an electronic textile

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Dec. 20, 2011 International Search Report issued in International Patent Application No. PCT/FR2011/000395.
Jan. 8, 2013 Translation of International Preliminary Report on Patentability issued in International Patent Application No. PCT/FR2011/000395.
May 12, 2015 Office Action issued in Japanese Patent Application No. 2013-517432.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150024589A1 (en) * 2012-01-31 2015-01-22 Commissariat A L'energie Atomique Aux Energies Alternatives Method for assembling a microelectronic chip element on a wire element, and installation enabling assembly to be performed
US9953953B2 (en) * 2012-01-31 2018-04-24 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for assembling a microelectronic chip element on a wire element, and installation enabling assembly to be performed
US10499502B2 (en) * 2015-01-27 2019-12-03 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Flexible device module for fabric layer assembly and method for production

Also Published As

Publication number Publication date
JP5951602B2 (en) 2016-07-13
WO2012007655A1 (en) 2012-01-19
US20130074331A1 (en) 2013-03-28
EP2591498A1 (en) 2013-05-15
FR2962593A1 (en) 2012-01-13
FR2962593B1 (en) 2014-03-28
JP2013531897A (en) 2013-08-08
CN102971841A (en) 2013-03-13

Similar Documents

Publication Publication Date Title
US9179586B2 (en) Method for assembling a chip in a flexible substrate
JP5175719B2 (en) Circuit board manufacturing method and circuit board structure
CN1625926B (en) Method for embedding a component in a base
KR101750713B1 (en) Interposer with microspring contacts and methods of making and using same
WO2014091644A1 (en) Multilayer wiring substrate and production method therefor
CN101466208B (en) Wiring substrate and method of manufacturing the same
US20140030471A1 (en) Component-embedded resin substrate and method for manufacturing same
KR101514518B1 (en) A printed circuit board comprising embeded electronic component within and a method for manufacturing
WO2009150087A2 (en) System support for electronic components and method for production thereof
JP2017017307A (en) Printed circuit board and method of manufacturing printed circuit board
CN104756615B (en) Printed circuit board
KR20170067472A (en) Printed circuit board and electronic component package having the same
US9190379B2 (en) Perimeter trench sensor array package
US10050014B2 (en) Circuit substrate and method of manufacturing same
JP2011151103A (en) Electronic component interconnecting structure and connecting method
JP6813387B2 (en) Wiring board for fingerprint sensor
JP5760687B2 (en) Wiring board
CN103904074A (en) Electric circuit and the method for producing the same
CN110798991B (en) Embedded substrate, manufacturing method thereof and circuit board with embedded substrate
JP5150720B2 (en) Manufacturing method of electronic assembly and electronic assembly
CN107451523B (en) Wiring substrate for fingerprint sensor
JP6525319B2 (en) Sheet-like coil component and mounted body of sheet-like coil component and method of mounting sheet-like coil component
KR102191573B1 (en) The method for manufacturing the printed circuit board
US11461609B1 (en) Multilayer structure and method of manufacturing such
JP2013149972A (en) Suspended lattice for electrical interconnection

Legal Events

Date Code Title Description
AS Assignment

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRUN, JEAN;REEL/FRAME:029591/0488

Effective date: 20121211

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20191103