US9087036B1 - Methods and apparatuses for time annotated transaction level modeling - Google Patents
Methods and apparatuses for time annotated transaction level modeling Download PDFInfo
- Publication number
- US9087036B1 US9087036B1 US11/203,554 US20355405A US9087036B1 US 9087036 B1 US9087036 B1 US 9087036B1 US 20355405 A US20355405 A US 20355405A US 9087036 B1 US9087036 B1 US 9087036B1
- Authority
- US
- United States
- Prior art keywords
- timing
- burst
- burst transaction
- transaction
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
-
- G06F17/5031—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/14—Network analysis or design
- H04L41/145—Network analysis or design involving simulating, designing, planning or modelling of a network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
B1=B+RqDL.
avgWDI=max(DSndI,DAL)
avgRRqI=max(RqSndI,RqAL)
avgRDI=max(RpSndI,RpAL)
avgWRpI=max(RpSndI,RpAL)
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/203,554 US9087036B1 (en) | 2004-08-12 | 2005-08-11 | Methods and apparatuses for time annotated transaction level modeling |
US12/706,656 US8504992B2 (en) | 2003-10-31 | 2010-02-16 | Method and apparatus for establishing a quality of service model |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US60151904P | 2004-08-12 | 2004-08-12 | |
US11/203,554 US9087036B1 (en) | 2004-08-12 | 2005-08-11 | Methods and apparatuses for time annotated transaction level modeling |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/144,883 Continuation-In-Part US8407433B2 (en) | 2003-10-31 | 2008-06-24 | Interconnect implementing internal controls |
Publications (1)
Publication Number | Publication Date |
---|---|
US9087036B1 true US9087036B1 (en) | 2015-07-21 |
Family
ID=53540146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/203,554 Active 2028-03-05 US9087036B1 (en) | 2003-10-31 | 2005-08-11 | Methods and apparatuses for time annotated transaction level modeling |
Country Status (1)
Country | Link |
---|---|
US (1) | US9087036B1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100318946A1 (en) * | 2005-10-07 | 2010-12-16 | Sonics, Inc. | Various methods and apparatuses for estimating characteristics of an electronic systems design |
US20160171138A1 (en) * | 2014-12-12 | 2016-06-16 | Freescale Semiconductor, Inc. | Method and computer system for simulating operation of a programmable integrated circuit |
US10521532B1 (en) * | 2018-09-07 | 2019-12-31 | Arm Limited | Segmented memory instances |
CN112052074A (en) * | 2020-09-29 | 2020-12-08 | 上海兆芯集成电路有限公司 | Processor modeling system and processor modeling method |
US11797409B1 (en) | 2022-09-02 | 2023-10-24 | HCL America Inc. | Method and system for managing transactions burstiness and generating signature thereof in a test environment |
CN112052074B (en) * | 2020-09-29 | 2024-05-03 | 上海兆芯集成电路股份有限公司 | Processor modeling system and processor modeling method |
Citations (145)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4189767A (en) | 1978-06-05 | 1980-02-19 | Bell Telephone Laboratories, Incorporated | Accessing arrangement for interleaved modular memories |
US4375097A (en) | 1978-06-02 | 1983-02-22 | Texas Instruments Incorporated | Transparent intelligent network for data and voice |
US4393470A (en) | 1979-11-19 | 1983-07-12 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) | Method and device for the counting and management of asynchronous events emitted by peripheral devices in a data processing system |
US4476498A (en) | 1982-02-05 | 1984-10-09 | Rca Corporation | Deviation detector for FM video recording system |
US4688188A (en) | 1984-01-24 | 1987-08-18 | International Computers Limited | Data storage apparatus for storing groups of data with read and write request detection |
US5107257A (en) | 1989-05-17 | 1992-04-21 | Nec Corporation | Bus relay apparatus for multi-data communication processing system |
JPH0512011Y2 (en) | 1985-04-09 | 1993-03-26 | ||
US5218456A (en) | 1991-07-22 | 1993-06-08 | Xerox Corporation | Disk bandwidth allocations to prioritize disk requests |
US5265257A (en) | 1990-06-22 | 1993-11-23 | Digital Equipment Corporation | Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines |
US5274769A (en) | 1988-08-29 | 1993-12-28 | Fujitsu Limited | System for transferring data between blocks |
US5287464A (en) | 1990-10-24 | 1994-02-15 | Zilog, Inc. | Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers |
US5363484A (en) | 1990-11-13 | 1994-11-08 | International Business Machines Corporation | Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets |
US5379379A (en) | 1988-06-30 | 1995-01-03 | Wang Laboratories, Inc. | Memory control unit with selective execution of queued read and write requests |
US5440752A (en) | 1991-07-08 | 1995-08-08 | Seiko Epson Corporation | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU |
US5469473A (en) | 1994-04-15 | 1995-11-21 | Texas Instruments Incorporated | Transceiver circuit with transition detection |
US5469433A (en) | 1994-04-29 | 1995-11-21 | Bell Communications Research, Inc. | System for the parallel assembly of data transmissions in a broadband network |
US5530901A (en) | 1991-11-28 | 1996-06-25 | Ricoh Company, Ltd. | Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively |
US5546546A (en) | 1994-05-20 | 1996-08-13 | Intel Corporation | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
US5557754A (en) | 1992-06-22 | 1996-09-17 | International Business Machines Corporation | Computer system and system expansion unit |
US5634006A (en) | 1992-08-17 | 1997-05-27 | International Business Machines Corporation | System and method for ensuring QOS in a token ring network utilizing an access regulator at each node for allocating frame size for plural transmitting applications based upon negotiated information and priority in the network |
US5664153A (en) | 1993-04-21 | 1997-09-02 | Intel Corporation | Page open/close scheme based on high order address bit and likelihood of page access |
US5673416A (en) | 1995-06-07 | 1997-09-30 | Seiko Epson Corporation | Memory request and control unit including a mechanism for issuing and removing requests for memory access |
US5708659A (en) | 1993-10-20 | 1998-01-13 | Lsi Logic Corporation | Method for hashing in a packet network switching system |
US5745913A (en) | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US5748629A (en) | 1995-07-19 | 1998-05-05 | Fujitsu Networks Communications, Inc. | Allocated and dynamic bandwidth management |
US5781918A (en) | 1991-08-16 | 1998-07-14 | Cypress Semiconductor Corp. | Memory system and method for selecting a different number of data channels depending on bus size |
US5809538A (en) | 1996-02-07 | 1998-09-15 | General Instrument Corporation | DRAM arbiter for video decoder |
US5872773A (en) | 1996-05-17 | 1999-02-16 | Lucent Technologies Inc. | Virtual trees routing protocol for an ATM-based mobile network |
US5917804A (en) | 1996-09-05 | 1999-06-29 | Northern Telecom Limited | Connection admission control for ATM networks handling CBR and VBR services |
JPH11191075A (en) | 1997-08-28 | 1999-07-13 | Oki Electric Ind Co Ltd | Priority encoding and decoding for memory architecture |
US5926649A (en) | 1996-10-23 | 1999-07-20 | Industrial Technology Research Institute | Media server for storage and retrieval of voluminous multimedia data |
US5948089A (en) | 1997-09-05 | 1999-09-07 | Sonics, Inc. | Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation |
JPH11250004A (en) | 1998-02-27 | 1999-09-17 | Nec Corp | Pci bus use right arbitration device |
US5982780A (en) | 1995-12-28 | 1999-11-09 | Dynarc Ab | Resource management scheme and arrangement |
US5996037A (en) | 1997-06-03 | 1999-11-30 | Lsi Logic Corporation | System and method for arbitrating multi-function access to a system bus |
US6023720A (en) | 1998-02-09 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Simultaneous processing of read and write requests using optimized storage partitions for read and write request deadlines |
WO2000029956A1 (en) | 1998-11-16 | 2000-05-25 | Infineon Technologies Ag | Methods and apparatus for prioritization of access to external devices |
US6092137A (en) | 1997-11-26 | 2000-07-18 | Industrial Technology Research Institute | Fair data bus arbitration system which assigns adjustable priority values to competing sources |
US6104690A (en) | 1996-09-27 | 2000-08-15 | Digital Optics Corporation | Integrated optical apparatus and associated methods |
US6105094A (en) | 1998-01-26 | 2000-08-15 | Adaptec, Inc. | Method and apparatus for allocating exclusive shared resource requests in a computer system |
US6119183A (en) | 1994-06-02 | 2000-09-12 | Storage Technology Corporation | Multi-port switching system and method for a computer bus |
JP2000250853A (en) | 1999-03-02 | 2000-09-14 | Nec Corp | Bus arbitration controller |
US6122690A (en) | 1997-06-05 | 2000-09-19 | Mentor Graphics Corporation | On-chip bus architecture that is both processor independent and scalable |
US6141713A (en) | 1997-06-26 | 2000-10-31 | Hyundai Electronics Industries Co., Ltd. | Bus arbitrator with a hierarchical control structure |
US6141355A (en) | 1998-11-06 | 2000-10-31 | Path 1 Network Technologies, Inc. | Time-synchronized multi-layer network switch for providing quality of service guarantees in computer networks |
US6167445A (en) | 1998-10-26 | 2000-12-26 | Cisco Technology, Inc. | Method and apparatus for defining and implementing high-level quality of service policies in computer networks |
US6182183B1 (en) | 1998-11-13 | 2001-01-30 | Sonics, Inc. | Communications system and method with multilevel connection identification |
US6199131B1 (en) | 1997-12-22 | 2001-03-06 | Compaq Computer Corporation | Computer system employing optimized delayed transaction arbitration technique |
US6198724B1 (en) | 1997-10-02 | 2001-03-06 | Vertex Networks, Inc. | ATM cell scheduling method and apparatus |
US6212611B1 (en) | 1998-11-03 | 2001-04-03 | Intel Corporation | Method and apparatus for providing a pipelined memory controller |
US6215797B1 (en) | 1998-08-19 | 2001-04-10 | Path 1 Technologies, Inc. | Methods and apparatus for providing quality of service guarantees in computer networks |
US6215789B1 (en) | 1998-06-10 | 2001-04-10 | Merlot Communications | Local area network for the transmission and control of audio, video, and computer data |
US6249144B1 (en) | 1997-10-09 | 2001-06-19 | Vantis Corporation | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources |
US6253269B1 (en) | 1998-12-22 | 2001-06-26 | 3Com Corporation | Bus arbiter system and method for managing communication buses |
US6266718B1 (en) | 1998-10-14 | 2001-07-24 | Micron Technology, Inc. | Apparatus for controlling data transfer operations between a memory and devices having respective latencies |
US20010026535A1 (en) | 2000-03-30 | 2001-10-04 | Kensaku Amou | Method and apparatus for packet scheduling in network |
WO2001075620A1 (en) | 2000-04-03 | 2001-10-11 | Advanced Micro Devices, Inc. | Bus bridge including a memory controller having an improved memory request arbitration mechanism |
WO2001093477A1 (en) | 2000-05-26 | 2001-12-06 | Sonics, Inc. | Communication system and method for different quality of service guarantees for different data flows |
US6335932B2 (en) | 1998-07-08 | 2002-01-01 | Broadcom Corporation | High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory |
US6363445B1 (en) | 1998-10-15 | 2002-03-26 | Micron Technology, Inc. | Method of bus arbitration using requesting device bandwidth and priority ranking |
US20020038397A1 (en) | 1999-12-29 | 2002-03-28 | Gurbir Singh | Quad pumped bus architecture and protocol |
US6393500B1 (en) | 1999-08-12 | 2002-05-21 | Mips Technologies, Inc. | Burst-configurable data bus |
US20020083256A1 (en) | 2000-08-31 | 2002-06-27 | Pannell Roger D. | System and method for increasing the count of outstanding split transactions |
US6430156B1 (en) | 1997-12-31 | 2002-08-06 | Hyundai Electronics Inds Co Ltd. | Traffic control method for providing predictive guaranteed service |
US20020129173A1 (en) | 2001-03-09 | 2002-09-12 | Wolf-Dietrich Weber | Communications system and method with non-blocking shared interface |
US20020129210A1 (en) | 2000-12-27 | 2002-09-12 | International Business Machines Corporation | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls |
US20020138687A1 (en) | 2001-01-16 | 2002-09-26 | Liuxi Yang | Spin-wheel SDRAM access scheduler for high performance microprocessors |
US6466825B1 (en) | 1998-09-29 | 2002-10-15 | Conexant Systems, Inc. | Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system |
US20020152297A1 (en) | 2000-05-23 | 2002-10-17 | Isabelle Lebourg | Quality of service control, particularly for telecommunication |
US20020174227A1 (en) | 2000-03-03 | 2002-11-21 | Hartsell Neal D. | Systems and methods for prioritization in information management environments |
US6487621B1 (en) | 1999-08-17 | 2002-11-26 | Compaq Information Technologies Group, L.P. | Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle |
US6499090B1 (en) | 1999-12-28 | 2002-12-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US20030004699A1 (en) | 2001-06-04 | 2003-01-02 | Choi Charles Y. | Method and apparatus for evaluating an integrated circuit model |
US6510497B1 (en) | 1998-12-09 | 2003-01-21 | Advanced Micro Devices, Inc. | Method and system for page-state sensitive memory control and access in data processing systems |
US20030023794A1 (en) | 2001-07-26 | 2003-01-30 | Venkitakrishnan Padmanabha I. | Cache coherent split transaction memory bus architecture and protocol for a multi processor chip device |
USRE37980E1 (en) | 1996-12-31 | 2003-02-04 | Compaq Computer Corporation | Bus-to-bus bridge in computer system, with fast burst memory range |
US6526462B1 (en) | 1999-11-19 | 2003-02-25 | Hammam Elabd | Programmable multi-tasking memory management system |
US6530007B2 (en) | 1998-07-13 | 2003-03-04 | Compaq Information Technologies Group, L.P. | Method and apparatus for supporting heterogeneous memory in computer systems |
US20030074520A1 (en) | 2001-10-12 | 2003-04-17 | Wolf-Dietrich Weber | Method and apparatus for scheduling requests using ordered stages of scheduling criteria |
US20030074519A1 (en) | 2001-10-12 | 2003-04-17 | Wolf-Dietrich Weber | Method and apparatus for scheduling of requests to dynamic random access memory device |
US20030079080A1 (en) | 2000-02-28 | 2003-04-24 | Sun Microsystems, Inc. | Disk scheduling system with bounded request reordering |
WO2003034242A1 (en) | 2001-10-12 | 2003-04-24 | Sonics, Inc. | Method and apparatus for scheduling a resource to meet quality-of-service restrictions |
US20030088721A1 (en) | 2001-11-05 | 2003-05-08 | Sharma Debendra Das | Method and system for controlling flow of ordered, pipelined transactions between intercommunicating electronic devices |
US6628609B2 (en) | 1998-04-30 | 2003-09-30 | Nortel Networks Limited | Method and apparatus for simple IP-layer bandwidth allocation using ingress control of egress bandwidth |
US6636482B2 (en) | 2001-03-08 | 2003-10-21 | Arris International, Inc. | Method and apparatus for controlling traffic loading of different service levels in a cable data system |
US20030208614A1 (en) | 2002-05-01 | 2003-11-06 | John Wilkes | System and method for enforcing system performance guarantees |
US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
US20040010652A1 (en) | 2001-06-26 | 2004-01-15 | Palmchip Corporation | System-on-chip (SOC) architecture with arbitrary pipeline depth |
US6683474B2 (en) | 2002-01-29 | 2004-01-27 | Sonic, Inc. | Method and apparatus for communication using a distributed multiplexed bus |
US6721325B1 (en) | 1998-04-23 | 2004-04-13 | Alcatel Canada Inc. | Fair share scheduling of multiple service classes with prioritized shaping |
US20040153928A1 (en) | 2002-12-17 | 2004-08-05 | Rohrbaugh John G. | Hierarchically-controlled automatic test pattern generation |
US6785753B2 (en) | 2001-06-01 | 2004-08-31 | Sonics, Inc. | Method and apparatus for response modes in pipelined environment |
US6816814B2 (en) | 2002-11-12 | 2004-11-09 | Sonics, Inc. | Method and apparatus for decomposing and verifying configurable hardware |
US6862265B1 (en) | 2000-04-13 | 2005-03-01 | Advanced Micro Devices, Inc. | Weighted fair queuing approximation in a network switch using weighted round robin and token bucket filter |
US6874039B2 (en) | 2000-09-08 | 2005-03-29 | Intel Corporation | Method and apparatus for distributed direct memory access for systems on chip |
US6877076B1 (en) | 2000-09-20 | 2005-04-05 | Broadcom Corporation | Memory controller with programmable configuration |
US6880133B2 (en) | 2002-05-15 | 2005-04-12 | Sonics, Inc. | Method and apparatus for optimizing distributed multiplexed bus interconnects |
US6882966B2 (en) * | 1999-12-02 | 2005-04-19 | Nec Electronics Corporation | Method, and apparatus for simulating a system using an object oriented language |
US20050086412A1 (en) | 2003-07-04 | 2005-04-21 | Cesar Douady | System and method for communicating between modules |
US20050117589A1 (en) | 2003-08-13 | 2005-06-02 | Cesar Douady | Method and device for managing priority during the transmission of a message |
US20050144585A1 (en) | 2003-12-29 | 2005-06-30 | Jyotirmoy Daw | Method and system for hardware accelerated verification of digital circuit design and its testbench |
US20050141505A1 (en) | 2003-11-13 | 2005-06-30 | Cesar Douady | System and method for transmitting a sequence of messages in an interconnection network |
US20050157717A1 (en) | 2004-01-21 | 2005-07-21 | Cesar Douady | Method and system for transmitting messages in an interconnection network |
US20050210325A1 (en) | 2004-03-02 | 2005-09-22 | Cesar Douady | Method and device for switching between agents |
US20050210164A1 (en) | 2004-03-11 | 2005-09-22 | Wolf-Dietrich Weber | Various methods and apparatuses for width and burst conversion |
WO2005045727A3 (en) | 2003-10-31 | 2005-10-06 | Sonics Inc | Scheduling memory access between a plurality of processors |
US6976106B2 (en) | 2002-11-01 | 2005-12-13 | Sonics, Inc. | Method and apparatus for speculative response arbitration to improve system latency |
US20060047890A1 (en) | 2002-11-20 | 2006-03-02 | Van De Waerdt Jan-Willem | Sdram address mapping optimized for two-dimensional access |
US7050958B1 (en) | 2000-06-02 | 2006-05-23 | Arm Limited | Method and apparatus for accelerating hardware simulation |
US7062423B1 (en) * | 2001-08-22 | 2006-06-13 | Marvell International Ltd. | Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channel |
US20060218315A1 (en) | 2005-03-25 | 2006-09-28 | Matsushita Electric Industrial Co., Ltd. | Memory access control circuit |
US7116131B1 (en) | 2004-09-15 | 2006-10-03 | Xilinx, Inc. | High performance programmable logic devices utilizing dynamic circuitry |
US20060225015A1 (en) | 2005-03-31 | 2006-10-05 | Kamil Synek | Various methods and apparatuses for flexible hierarchy grouping |
US7120765B2 (en) | 2002-10-30 | 2006-10-10 | Intel Corporation | Memory transaction ordering |
JP2006277404A (en) | 2005-03-29 | 2006-10-12 | Nec Corp | Multiprocessor system and memory access method |
US20060242525A1 (en) | 2005-03-31 | 2006-10-26 | Hollander Yoav Z | Method and apparatus for functionally verifying a physical device under test |
US7149829B2 (en) | 2003-04-18 | 2006-12-12 | Sonics, Inc. | Various methods and apparatuses for arbitration among blocks of functionality |
US7155554B2 (en) | 2004-11-02 | 2006-12-26 | Sonics, Inc. | Methods and apparatuses for generating a single request for block transactions over a communication fabric |
US20070038791A1 (en) | 2005-08-11 | 2007-02-15 | P.A. Semi, Inc. | Non-blocking address switch with shallow per agent queues |
US7194566B2 (en) | 2002-05-03 | 2007-03-20 | Sonics, Inc. | Communication system and method with configurable posting points |
US7194658B2 (en) | 2003-07-24 | 2007-03-20 | Sonics, Inc. | Various methods and apparatuses for interfacing of a protocol monitor to protocol checkers and functional checkers |
US7194561B2 (en) | 2001-10-12 | 2007-03-20 | Sonics, Inc. | Method and apparatus for scheduling requests to a resource using a configurable threshold |
US20070083830A1 (en) | 2005-10-07 | 2007-04-12 | Stephen Hamilton | Various methods and apparatuses for an executable parameterized timing model |
US20070110052A1 (en) | 2005-11-16 | 2007-05-17 | Sophana Kok | System and method for the static routing of data packet streams in an interconnect network |
US7254603B2 (en) | 2002-05-03 | 2007-08-07 | Sonics, Inc. | On-chip inter-network performance optimization using configurable performance parameters |
US7266786B2 (en) | 2002-11-05 | 2007-09-04 | Sonics, Inc. | Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems |
US7277975B2 (en) | 2004-11-02 | 2007-10-02 | Sonics, Inc. | Methods and apparatuses for decoupling a request from one or more solicited responses |
US7296105B2 (en) | 2003-10-03 | 2007-11-13 | Sonics, Inc. | Method and apparatus for configuring an interconnect to implement arbitration |
US7302691B2 (en) | 2002-05-10 | 2007-11-27 | Sonics, Incorporated | Scalable low bandwidth multicast handling in mixed core systems |
US7325221B1 (en) | 2000-08-08 | 2008-01-29 | Sonics, Incorporated | Logic system with configurable interface |
US20080028090A1 (en) | 2006-07-26 | 2008-01-31 | Sophana Kok | System for managing messages transmitted in an on-chip interconnect network |
US7356633B2 (en) | 2002-05-03 | 2008-04-08 | Sonics, Inc. | Composing on-chip interconnects with configurable interfaces |
US20080086577A1 (en) | 2006-10-04 | 2008-04-10 | Mediatek Inc. | Digital Television System, Memory Controller, and Method for Data Access |
US20080235421A1 (en) | 2007-03-22 | 2008-09-25 | Siva Shankar Jayaratnam | Technique and apparatus to optimize inter-port memory transaction sequencing on a multi-ported memory controller unit |
US20080320268A1 (en) | 2007-06-25 | 2008-12-25 | Sonics, Inc. | Interconnect implementing internal controls |
US7543093B2 (en) | 2004-08-30 | 2009-06-02 | Shanghai Magima Digital Information Co., Ltd. | Method and system for stream burst data transfer |
US7552292B2 (en) | 2004-10-29 | 2009-06-23 | Via Technologies, Inc. | Method of memory space configuration |
US7587535B2 (en) | 2006-07-31 | 2009-09-08 | Panasonic Corporation | Data transfer control device including endian conversion circuit with data realignment |
US7590815B1 (en) | 2002-08-30 | 2009-09-15 | Nvidia Corporation | Method and apparatus for partial memory power shutoff |
US20090235020A1 (en) | 2007-06-25 | 2009-09-17 | Sonics, Inc. | Various methods and apparatus for address tiling |
US7598726B1 (en) | 2005-09-12 | 2009-10-06 | Virage Logic Corporation | Methods and apparatuses for test methodology of input-output circuits |
US20100042759A1 (en) | 2007-06-25 | 2010-02-18 | Sonics, Inc. | Various methods and apparatus for address tiling and channel interleaving throughout the integrated system |
US20100211935A1 (en) | 2003-10-31 | 2010-08-19 | Sonics, Inc. | Method and apparatus for establishing a quality of service model |
US7852343B2 (en) | 2004-04-15 | 2010-12-14 | Panasonic Corporation | Burst memory access method to rectangular area |
US7899953B2 (en) | 2007-04-20 | 2011-03-01 | Nuflare Technology, Inc. | Data transfer system |
-
2005
- 2005-08-11 US US11/203,554 patent/US9087036B1/en active Active
Patent Citations (166)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4375097A (en) | 1978-06-02 | 1983-02-22 | Texas Instruments Incorporated | Transparent intelligent network for data and voice |
US4189767A (en) | 1978-06-05 | 1980-02-19 | Bell Telephone Laboratories, Incorporated | Accessing arrangement for interleaved modular memories |
US4393470A (en) | 1979-11-19 | 1983-07-12 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) | Method and device for the counting and management of asynchronous events emitted by peripheral devices in a data processing system |
US4476498A (en) | 1982-02-05 | 1984-10-09 | Rca Corporation | Deviation detector for FM video recording system |
US4688188A (en) | 1984-01-24 | 1987-08-18 | International Computers Limited | Data storage apparatus for storing groups of data with read and write request detection |
JPH0512011Y2 (en) | 1985-04-09 | 1993-03-26 | ||
US5379379A (en) | 1988-06-30 | 1995-01-03 | Wang Laboratories, Inc. | Memory control unit with selective execution of queued read and write requests |
US5274769A (en) | 1988-08-29 | 1993-12-28 | Fujitsu Limited | System for transferring data between blocks |
US5107257A (en) | 1989-05-17 | 1992-04-21 | Nec Corporation | Bus relay apparatus for multi-data communication processing system |
US5265257A (en) | 1990-06-22 | 1993-11-23 | Digital Equipment Corporation | Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines |
US5287464A (en) | 1990-10-24 | 1994-02-15 | Zilog, Inc. | Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers |
US5363484A (en) | 1990-11-13 | 1994-11-08 | International Business Machines Corporation | Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets |
US5440752A (en) | 1991-07-08 | 1995-08-08 | Seiko Epson Corporation | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU |
US5218456A (en) | 1991-07-22 | 1993-06-08 | Xerox Corporation | Disk bandwidth allocations to prioritize disk requests |
US5781918A (en) | 1991-08-16 | 1998-07-14 | Cypress Semiconductor Corp. | Memory system and method for selecting a different number of data channels depending on bus size |
US5530901A (en) | 1991-11-28 | 1996-06-25 | Ricoh Company, Ltd. | Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively |
US5557754A (en) | 1992-06-22 | 1996-09-17 | International Business Machines Corporation | Computer system and system expansion unit |
US5634006A (en) | 1992-08-17 | 1997-05-27 | International Business Machines Corporation | System and method for ensuring QOS in a token ring network utilizing an access regulator at each node for allocating frame size for plural transmitting applications based upon negotiated information and priority in the network |
US5664153A (en) | 1993-04-21 | 1997-09-02 | Intel Corporation | Page open/close scheme based on high order address bit and likelihood of page access |
US5708659A (en) | 1993-10-20 | 1998-01-13 | Lsi Logic Corporation | Method for hashing in a packet network switching system |
US5469473A (en) | 1994-04-15 | 1995-11-21 | Texas Instruments Incorporated | Transceiver circuit with transition detection |
US5469433A (en) | 1994-04-29 | 1995-11-21 | Bell Communications Research, Inc. | System for the parallel assembly of data transmissions in a broadband network |
US5546546A (en) | 1994-05-20 | 1996-08-13 | Intel Corporation | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
US6119183A (en) | 1994-06-02 | 2000-09-12 | Storage Technology Corporation | Multi-port switching system and method for a computer bus |
US5673416A (en) | 1995-06-07 | 1997-09-30 | Seiko Epson Corporation | Memory request and control unit including a mechanism for issuing and removing requests for memory access |
US5748629A (en) | 1995-07-19 | 1998-05-05 | Fujitsu Networks Communications, Inc. | Allocated and dynamic bandwidth management |
US5982780A (en) | 1995-12-28 | 1999-11-09 | Dynarc Ab | Resource management scheme and arrangement |
US5809538A (en) | 1996-02-07 | 1998-09-15 | General Instrument Corporation | DRAM arbiter for video decoder |
US5872773A (en) | 1996-05-17 | 1999-02-16 | Lucent Technologies Inc. | Virtual trees routing protocol for an ATM-based mobile network |
US5745913A (en) | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US5917804A (en) | 1996-09-05 | 1999-06-29 | Northern Telecom Limited | Connection admission control for ATM networks handling CBR and VBR services |
US6104690A (en) | 1996-09-27 | 2000-08-15 | Digital Optics Corporation | Integrated optical apparatus and associated methods |
US5926649A (en) | 1996-10-23 | 1999-07-20 | Industrial Technology Research Institute | Media server for storage and retrieval of voluminous multimedia data |
USRE37980E1 (en) | 1996-12-31 | 2003-02-04 | Compaq Computer Corporation | Bus-to-bus bridge in computer system, with fast burst memory range |
US5996037A (en) | 1997-06-03 | 1999-11-30 | Lsi Logic Corporation | System and method for arbitrating multi-function access to a system bus |
US6122690A (en) | 1997-06-05 | 2000-09-19 | Mentor Graphics Corporation | On-chip bus architecture that is both processor independent and scalable |
US6141713A (en) | 1997-06-26 | 2000-10-31 | Hyundai Electronics Industries Co., Ltd. | Bus arbitrator with a hierarchical control structure |
JPH11191075A (en) | 1997-08-28 | 1999-07-13 | Oki Electric Ind Co Ltd | Priority encoding and decoding for memory architecture |
US5948089A (en) | 1997-09-05 | 1999-09-07 | Sonics, Inc. | Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation |
US6198724B1 (en) | 1997-10-02 | 2001-03-06 | Vertex Networks, Inc. | ATM cell scheduling method and apparatus |
US6249144B1 (en) | 1997-10-09 | 2001-06-19 | Vantis Corporation | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources |
US6092137A (en) | 1997-11-26 | 2000-07-18 | Industrial Technology Research Institute | Fair data bus arbitration system which assigns adjustable priority values to competing sources |
US6199131B1 (en) | 1997-12-22 | 2001-03-06 | Compaq Computer Corporation | Computer system employing optimized delayed transaction arbitration technique |
US6430156B1 (en) | 1997-12-31 | 2002-08-06 | Hyundai Electronics Inds Co Ltd. | Traffic control method for providing predictive guaranteed service |
US6105094A (en) | 1998-01-26 | 2000-08-15 | Adaptec, Inc. | Method and apparatus for allocating exclusive shared resource requests in a computer system |
US6023720A (en) | 1998-02-09 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Simultaneous processing of read and write requests using optimized storage partitions for read and write request deadlines |
JPH11250004A (en) | 1998-02-27 | 1999-09-17 | Nec Corp | Pci bus use right arbitration device |
US6721325B1 (en) | 1998-04-23 | 2004-04-13 | Alcatel Canada Inc. | Fair share scheduling of multiple service classes with prioritized shaping |
US6628609B2 (en) | 1998-04-30 | 2003-09-30 | Nortel Networks Limited | Method and apparatus for simple IP-layer bandwidth allocation using ingress control of egress bandwidth |
US6215789B1 (en) | 1998-06-10 | 2001-04-10 | Merlot Communications | Local area network for the transmission and control of audio, video, and computer data |
US6335932B2 (en) | 1998-07-08 | 2002-01-01 | Broadcom Corporation | High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory |
US6530007B2 (en) | 1998-07-13 | 2003-03-04 | Compaq Information Technologies Group, L.P. | Method and apparatus for supporting heterogeneous memory in computer systems |
US6215797B1 (en) | 1998-08-19 | 2001-04-10 | Path 1 Technologies, Inc. | Methods and apparatus for providing quality of service guarantees in computer networks |
US6466825B1 (en) | 1998-09-29 | 2002-10-15 | Conexant Systems, Inc. | Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system |
US6266718B1 (en) | 1998-10-14 | 2001-07-24 | Micron Technology, Inc. | Apparatus for controlling data transfer operations between a memory and devices having respective latencies |
US6363445B1 (en) | 1998-10-15 | 2002-03-26 | Micron Technology, Inc. | Method of bus arbitration using requesting device bandwidth and priority ranking |
US6167445A (en) | 1998-10-26 | 2000-12-26 | Cisco Technology, Inc. | Method and apparatus for defining and implementing high-level quality of service policies in computer networks |
US6212611B1 (en) | 1998-11-03 | 2001-04-03 | Intel Corporation | Method and apparatus for providing a pipelined memory controller |
US6141355A (en) | 1998-11-06 | 2000-10-31 | Path 1 Network Technologies, Inc. | Time-synchronized multi-layer network switch for providing quality of service guarantees in computer networks |
US20070094429A1 (en) | 1998-11-13 | 2007-04-26 | Wingard Drew E | Communications system and method with multilevel connection identification |
US6182183B1 (en) | 1998-11-13 | 2001-01-30 | Sonics, Inc. | Communications system and method with multilevel connection identification |
US20040177186A1 (en) | 1998-11-13 | 2004-09-09 | Wingard Drew Eric | Communications system and method with multilevel connection identification |
US7120712B2 (en) | 1998-11-13 | 2006-10-10 | Sonics, Inc. | Communications system and method with multilevel connection identification |
US6725313B1 (en) | 1998-11-13 | 2004-04-20 | Sonics, Inc. | Communications system and method with multilevel connection identification |
WO2000029956A1 (en) | 1998-11-16 | 2000-05-25 | Infineon Technologies Ag | Methods and apparatus for prioritization of access to external devices |
US6510497B1 (en) | 1998-12-09 | 2003-01-21 | Advanced Micro Devices, Inc. | Method and system for page-state sensitive memory control and access in data processing systems |
US6253269B1 (en) | 1998-12-22 | 2001-06-26 | 3Com Corporation | Bus arbiter system and method for managing communication buses |
JP2000250853A (en) | 1999-03-02 | 2000-09-14 | Nec Corp | Bus arbitration controller |
US6393500B1 (en) | 1999-08-12 | 2002-05-21 | Mips Technologies, Inc. | Burst-configurable data bus |
US6487621B1 (en) | 1999-08-17 | 2002-11-26 | Compaq Information Technologies Group, L.P. | Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle |
US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
US6526462B1 (en) | 1999-11-19 | 2003-02-25 | Hammam Elabd | Programmable multi-tasking memory management system |
US6882966B2 (en) * | 1999-12-02 | 2005-04-19 | Nec Electronics Corporation | Method, and apparatus for simulating a system using an object oriented language |
US6499090B1 (en) | 1999-12-28 | 2002-12-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US20020038397A1 (en) | 1999-12-29 | 2002-03-28 | Gurbir Singh | Quad pumped bus architecture and protocol |
US20030079080A1 (en) | 2000-02-28 | 2003-04-24 | Sun Microsystems, Inc. | Disk scheduling system with bounded request reordering |
US20020174227A1 (en) | 2000-03-03 | 2002-11-21 | Hartsell Neal D. | Systems and methods for prioritization in information management environments |
US20010026535A1 (en) | 2000-03-30 | 2001-10-04 | Kensaku Amou | Method and apparatus for packet scheduling in network |
WO2001075620A1 (en) | 2000-04-03 | 2001-10-11 | Advanced Micro Devices, Inc. | Bus bridge including a memory controller having an improved memory request arbitration mechanism |
US6862265B1 (en) | 2000-04-13 | 2005-03-01 | Advanced Micro Devices, Inc. | Weighted fair queuing approximation in a network switch using weighted round robin and token bucket filter |
US20020152297A1 (en) | 2000-05-23 | 2002-10-17 | Isabelle Lebourg | Quality of service control, particularly for telecommunication |
US6330225B1 (en) | 2000-05-26 | 2001-12-11 | Sonics, Inc. | Communication system and method for different quality of service guarantees for different data flows |
WO2001093477A1 (en) | 2000-05-26 | 2001-12-06 | Sonics, Inc. | Communication system and method for different quality of service guarantees for different data flows |
US7050958B1 (en) | 2000-06-02 | 2006-05-23 | Arm Limited | Method and apparatus for accelerating hardware simulation |
US7325221B1 (en) | 2000-08-08 | 2008-01-29 | Sonics, Incorporated | Logic system with configurable interface |
US20020083256A1 (en) | 2000-08-31 | 2002-06-27 | Pannell Roger D. | System and method for increasing the count of outstanding split transactions |
US6874039B2 (en) | 2000-09-08 | 2005-03-29 | Intel Corporation | Method and apparatus for distributed direct memory access for systems on chip |
US6877076B1 (en) | 2000-09-20 | 2005-04-05 | Broadcom Corporation | Memory controller with programmable configuration |
US20020129210A1 (en) | 2000-12-27 | 2002-09-12 | International Business Machines Corporation | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls |
US20020138687A1 (en) | 2001-01-16 | 2002-09-26 | Liuxi Yang | Spin-wheel SDRAM access scheduler for high performance microprocessors |
US6636482B2 (en) | 2001-03-08 | 2003-10-21 | Arris International, Inc. | Method and apparatus for controlling traffic loading of different service levels in a cable data system |
US20020129173A1 (en) | 2001-03-09 | 2002-09-12 | Wolf-Dietrich Weber | Communications system and method with non-blocking shared interface |
US6785753B2 (en) | 2001-06-01 | 2004-08-31 | Sonics, Inc. | Method and apparatus for response modes in pipelined environment |
US20030004699A1 (en) | 2001-06-04 | 2003-01-02 | Choi Charles Y. | Method and apparatus for evaluating an integrated circuit model |
US20040010652A1 (en) | 2001-06-26 | 2004-01-15 | Palmchip Corporation | System-on-chip (SOC) architecture with arbitrary pipeline depth |
US20030023794A1 (en) | 2001-07-26 | 2003-01-30 | Venkitakrishnan Padmanabha I. | Cache coherent split transaction memory bus architecture and protocol for a multi processor chip device |
US7062423B1 (en) * | 2001-08-22 | 2006-06-13 | Marvell International Ltd. | Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channel |
WO2003034242A1 (en) | 2001-10-12 | 2003-04-24 | Sonics, Inc. | Method and apparatus for scheduling a resource to meet quality-of-service restrictions |
US6804757B2 (en) | 2001-10-12 | 2004-10-12 | Sonics, Inc. | Method and apparatus for scheduling requests using ordered stages of scheduling criteria |
US6804738B2 (en) | 2001-10-12 | 2004-10-12 | Sonics, Inc. | Method and apparatus for scheduling a resource to meet quality-of-service restrictions |
US20030074520A1 (en) | 2001-10-12 | 2003-04-17 | Wolf-Dietrich Weber | Method and apparatus for scheduling requests using ordered stages of scheduling criteria |
US20030074519A1 (en) | 2001-10-12 | 2003-04-17 | Wolf-Dietrich Weber | Method and apparatus for scheduling of requests to dynamic random access memory device |
US7194561B2 (en) | 2001-10-12 | 2007-03-20 | Sonics, Inc. | Method and apparatus for scheduling requests to a resource using a configurable threshold |
US7191273B2 (en) | 2001-10-12 | 2007-03-13 | Sonics, Inc. | Method and apparatus for scheduling a resource to meet quality-of-service restrictions |
US6578117B2 (en) | 2001-10-12 | 2003-06-10 | Sonics, Inc. | Method and apparatus for scheduling requests using ordered stages of scheduling criteria |
US20030088721A1 (en) | 2001-11-05 | 2003-05-08 | Sharma Debendra Das | Method and system for controlling flow of ordered, pipelined transactions between intercommunicating electronic devices |
US6683474B2 (en) | 2002-01-29 | 2004-01-27 | Sonic, Inc. | Method and apparatus for communication using a distributed multiplexed bus |
US20030208614A1 (en) | 2002-05-01 | 2003-11-06 | John Wilkes | System and method for enforcing system performance guarantees |
US7254603B2 (en) | 2002-05-03 | 2007-08-07 | Sonics, Inc. | On-chip inter-network performance optimization using configurable performance parameters |
US7194566B2 (en) | 2002-05-03 | 2007-03-20 | Sonics, Inc. | Communication system and method with configurable posting points |
US7356633B2 (en) | 2002-05-03 | 2008-04-08 | Sonics, Inc. | Composing on-chip interconnects with configurable interfaces |
US7302691B2 (en) | 2002-05-10 | 2007-11-27 | Sonics, Incorporated | Scalable low bandwidth multicast handling in mixed core systems |
US6880133B2 (en) | 2002-05-15 | 2005-04-12 | Sonics, Inc. | Method and apparatus for optimizing distributed multiplexed bus interconnects |
US7590815B1 (en) | 2002-08-30 | 2009-09-15 | Nvidia Corporation | Method and apparatus for partial memory power shutoff |
US7120765B2 (en) | 2002-10-30 | 2006-10-10 | Intel Corporation | Memory transaction ordering |
US6976106B2 (en) | 2002-11-01 | 2005-12-13 | Sonics, Inc. | Method and apparatus for speculative response arbitration to improve system latency |
US7266786B2 (en) | 2002-11-05 | 2007-09-04 | Sonics, Inc. | Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems |
US7299155B2 (en) | 2002-11-12 | 2007-11-20 | Sonics, Incorporated | Method and apparatus for decomposing and verifying configurable hardware |
US6816814B2 (en) | 2002-11-12 | 2004-11-09 | Sonics, Inc. | Method and apparatus for decomposing and verifying configurable hardware |
US20060047890A1 (en) | 2002-11-20 | 2006-03-02 | Van De Waerdt Jan-Willem | Sdram address mapping optimized for two-dimensional access |
US20040153928A1 (en) | 2002-12-17 | 2004-08-05 | Rohrbaugh John G. | Hierarchically-controlled automatic test pattern generation |
US7149829B2 (en) | 2003-04-18 | 2006-12-12 | Sonics, Inc. | Various methods and apparatuses for arbitration among blocks of functionality |
US20050086412A1 (en) | 2003-07-04 | 2005-04-21 | Cesar Douady | System and method for communicating between modules |
US7194658B2 (en) | 2003-07-24 | 2007-03-20 | Sonics, Inc. | Various methods and apparatuses for interfacing of a protocol monitor to protocol checkers and functional checkers |
US20050117589A1 (en) | 2003-08-13 | 2005-06-02 | Cesar Douady | Method and device for managing priority during the transmission of a message |
US7296105B2 (en) | 2003-10-03 | 2007-11-13 | Sonics, Inc. | Method and apparatus for configuring an interconnect to implement arbitration |
JP5144934B2 (en) | 2003-10-31 | 2013-02-13 | ソニックス・インコーポレーテッド | Method and apparatus for establishing a quality of service model |
EP1678620B1 (en) | 2003-10-31 | 2011-06-22 | Sonics, Inc. | Scheduling memory access between a plurality of processors |
US20100211935A1 (en) | 2003-10-31 | 2010-08-19 | Sonics, Inc. | Method and apparatus for establishing a quality of service model |
WO2005045727A3 (en) | 2003-10-31 | 2005-10-06 | Sonics Inc | Scheduling memory access between a plurality of processors |
US7665069B2 (en) | 2003-10-31 | 2010-02-16 | Sonics, Inc. | Method and apparatus for establishing a quality of service model |
KR101196048B1 (en) | 2003-10-31 | 2012-11-02 | 소닉스, 인코퍼레이티드 | Scheduling memory access between a plurality of processors |
US20050141505A1 (en) | 2003-11-13 | 2005-06-30 | Cesar Douady | System and method for transmitting a sequence of messages in an interconnection network |
US20050144585A1 (en) | 2003-12-29 | 2005-06-30 | Jyotirmoy Daw | Method and system for hardware accelerated verification of digital circuit design and its testbench |
US20050157717A1 (en) | 2004-01-21 | 2005-07-21 | Cesar Douady | Method and system for transmitting messages in an interconnection network |
US20050210325A1 (en) | 2004-03-02 | 2005-09-22 | Cesar Douady | Method and device for switching between agents |
US7574629B2 (en) | 2004-03-02 | 2009-08-11 | Arteris | Method and device for switching between agents |
US7543088B2 (en) | 2004-03-11 | 2009-06-02 | Sonics, Inc. | Various methods and apparatuses for width and burst conversion |
US20050210164A1 (en) | 2004-03-11 | 2005-09-22 | Wolf-Dietrich Weber | Various methods and apparatuses for width and burst conversion |
US7852343B2 (en) | 2004-04-15 | 2010-12-14 | Panasonic Corporation | Burst memory access method to rectangular area |
US7543093B2 (en) | 2004-08-30 | 2009-06-02 | Shanghai Magima Digital Information Co., Ltd. | Method and system for stream burst data transfer |
US7116131B1 (en) | 2004-09-15 | 2006-10-03 | Xilinx, Inc. | High performance programmable logic devices utilizing dynamic circuitry |
US7552292B2 (en) | 2004-10-29 | 2009-06-23 | Via Technologies, Inc. | Method of memory space configuration |
US7155554B2 (en) | 2004-11-02 | 2006-12-26 | Sonics, Inc. | Methods and apparatuses for generating a single request for block transactions over a communication fabric |
US7277975B2 (en) | 2004-11-02 | 2007-10-02 | Sonics, Inc. | Methods and apparatuses for decoupling a request from one or more solicited responses |
US20060218315A1 (en) | 2005-03-25 | 2006-09-28 | Matsushita Electric Industrial Co., Ltd. | Memory access control circuit |
JP2006277404A (en) | 2005-03-29 | 2006-10-12 | Nec Corp | Multiprocessor system and memory access method |
US20060225015A1 (en) | 2005-03-31 | 2006-10-05 | Kamil Synek | Various methods and apparatuses for flexible hierarchy grouping |
US20060242525A1 (en) | 2005-03-31 | 2006-10-26 | Hollander Yoav Z | Method and apparatus for functionally verifying a physical device under test |
US20070038791A1 (en) | 2005-08-11 | 2007-02-15 | P.A. Semi, Inc. | Non-blocking address switch with shallow per agent queues |
US7598726B1 (en) | 2005-09-12 | 2009-10-06 | Virage Logic Corporation | Methods and apparatuses for test methodology of input-output circuits |
US20070083830A1 (en) | 2005-10-07 | 2007-04-12 | Stephen Hamilton | Various methods and apparatuses for an executable parameterized timing model |
US20070110052A1 (en) | 2005-11-16 | 2007-05-17 | Sophana Kok | System and method for the static routing of data packet streams in an interconnect network |
US20080028090A1 (en) | 2006-07-26 | 2008-01-31 | Sophana Kok | System for managing messages transmitted in an on-chip interconnect network |
US7587535B2 (en) | 2006-07-31 | 2009-09-08 | Panasonic Corporation | Data transfer control device including endian conversion circuit with data realignment |
US20080086577A1 (en) | 2006-10-04 | 2008-04-10 | Mediatek Inc. | Digital Television System, Memory Controller, and Method for Data Access |
US20080235421A1 (en) | 2007-03-22 | 2008-09-25 | Siva Shankar Jayaratnam | Technique and apparatus to optimize inter-port memory transaction sequencing on a multi-ported memory controller unit |
US7899953B2 (en) | 2007-04-20 | 2011-03-01 | Nuflare Technology, Inc. | Data transfer system |
US20090235020A1 (en) | 2007-06-25 | 2009-09-17 | Sonics, Inc. | Various methods and apparatus for address tiling |
WO2009002998A1 (en) | 2007-06-25 | 2008-12-31 | Sonics, Inc. | An interconnect implementing internal controls |
US20080320254A1 (en) | 2007-06-25 | 2008-12-25 | Sonics, Inc. | Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary |
US20100042759A1 (en) | 2007-06-25 | 2010-02-18 | Sonics, Inc. | Various methods and apparatus for address tiling and channel interleaving throughout the integrated system |
US20080320255A1 (en) | 2007-06-25 | 2008-12-25 | Sonics, Inc. | Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets |
US20080320476A1 (en) | 2007-06-25 | 2008-12-25 | Sonics, Inc. | Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering |
US20080320268A1 (en) | 2007-06-25 | 2008-12-25 | Sonics, Inc. | Interconnect implementing internal controls |
US8108648B2 (en) | 2007-06-25 | 2012-01-31 | Sonics, Inc. | Various methods and apparatus for address tiling |
Non-Patent Citations (84)
Title |
---|
"1st NASCUG Meeting", Meeting Presentations, http:\\www.nascug.org/nascug2004-spring.html North American SystemC Users Group, Jun. 7, 2004, pp. 2. |
"IEEE 100: The Authoritative Dictionary of IEEE Standards Terms", 2000, IEEE, 7th Edition, IEEE Standard 100-2000, pp. 570 and 693. |
"Intel Dual-Channel DDR Memory Architecture" White Paper Informational Brochure, Infineon Technologies North America Corporation and Kingston Technolgy Company, Inc., 14 pages, Sep. 2003. |
"Open Core Protocol (OCP)", Wikipedia, the free encyclopedia, http://en.wikipedia.org/wiki/Open-Core-Protocol, Feb. 9, 2009, 2 pages. |
"Open Core Protocol Specification," OCP International Partnership, Release 1.0, 2001, 2 pgs. |
"Open Core Protocol Transaction Level 2", results of search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"Open Core Protocol Transaction Level 2", search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"Open Core Protocol", results of search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"Open Core Protocol", search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"SystemC", results of search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"SystemC", search query on Trademark Electronic Search System (TESS), United States Trademark and Patent Office, Feb. 7, 2009, 2 pages. |
"SystemC", Wikipedia, the free encyclopedia, http://en.wikipedia.org/wiki/SystemC, Feb. 9, 2009, 6 pages. |
2nd NASCUG Meeting Agenda, Meeting Presentations, GSPx 2004, Santa Clara, CA U.S.A., Sep. 29, 2004, http://www.nascug.org/nascug2004-fall.agenda.html, North American SystemC Users Group, pp. 2. |
Adan et al., "Queueing Models and some Fundamental Relations", Chapter 3, XP-002329104, Feb. 14, 2001, pp. 23-27 (double-sided copy). |
Advisory Action for U.S. Appl. No. 12/706,656, mailed Nov. 15, 2012, 4 pages. U.S. Patent and Trademark Office, Alexandria, Virginia, USA. |
Ahn, Jung Ho, et al., "The Design Space of Data-Parallel Memory Systems", IEEE, 12 pages, Nov. 2006. |
Alan Kamas, "The SystemC OCP Models, An Overview of the SystemC Models for the Open Core Protocol", NASCUG Sep. 29, 2004, Copyright Alan Kamas 2004, www. karnas.com, pp. 30. |
Alan Kamas. "Dot.org-Open Core Protocol: The SystemC Models" article, published in Apr./May 2004 issue of Chip Design Magazine, http://www.chipdesignmag.com/print.php?articleId=28?issueId=4, pp. 2. |
Alexanian, H., Bolden, G., Amir, Z., "Simplifying the Behavior of System C Descriptions for Hardware/Software Covalidation," copyright 2005 [retrieved Apr. 26, 2008] Retreived from the Internet. <URL: www.ocpip.org/pressroom/schedule/speaking/papers-presentations/Summit-OCP-IP-pavillion-pres.pps>. |
Bakr Younis et al., "Operating System for Switched Analog Mixed-Signal Circuits", The Ohio State University Department of Electrical and Computer Engineering Design Automation Research Lab (DARL), Jun. 7, 2004, pp. 12. |
Benini et al., "Networks on Chips: A New SoC Paradigm", In IEEE 2002, Computer, vol. 35, No. 1, pp. 70-78, 9 pages. |
Black, Co-Founder, "Eklectic Ally Electronic Systems Solutions", SystemC 2.1 Preview-DAC2004, www.EklecticAlly.com, info@EklecticAlly.com, Version 1.0, Copyright 2003, pp. 12. |
Brian McMurtrey et al., "SystemC Enabling Embedded System Design at Sandia", Sandia National Laboratories, Apr. 14, 2004, pp. 11. |
Casini, Phil, "Measuring the Value of Third Party Interconnects," Sonics, Inc., White Paper, 2005, 11 pages, www.sonicsinc.com. |
Chou, Joe, "System-Level Design Using OCP Based Transaction-Level Models," presentation, Denali MemCom Taiwan 2005, OCP International Partnership, 23 pages. |
Cottrell, Donald, Chapter 78: "Design Automation Technology Roadmap", The VLSI Handbook, Copyright 2000, 41 Pages. |
Dally et al., "Route Packets, Not Wires: On-Chip Interconnection Networks." In Design Automation Conference, pp. 684-689, Jun. 2001, 6 pages. |
Dally, William J., "Virtual-channel Flow Control", In Proceedings of the 17th Int. Symp. on Computer Architecture, ACM SIGARCH, May 1990, vol. 18, No. 2, pp. 60-68, 9 pages. |
De Meer, H.; Richter, J.-P.; Puliafito, A.; Tomarchio, O., "Tunnel agents for enhanced Internet QoS," Concurrency, IEEE, vol. 6, No. 2, pp. 30-39, Apr.-Jun. 1998, URL: http//ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=678787&isnumber=14923. |
Final Office Action for U.S. Appl. No. 12/706,656, mailed Jul. 25, 2012, 37 pages. U.S. Patent and Trademark Office, Alexandria, Virginia, USA. |
Final Preliminary Rejection (Office Action) for Korean Patent Application No. 10-20067010659 mailed Oct. 18, 2011, 6 pages. Korean Intellectual Property Office. |
G Maruccia et al., "OCCN On-Chip-Communication-Network" From On-Chip bus to Network-on-Chip, a unique modeling framework, Advanced System Technology STMicroelectronics, Jun. 7, 2004, pp. 12. |
Goossens et al., "Networks on Silicon: Combining Best-Effort and Guaranteed Services", In Proceeding of 2002 Design, 3 pages. |
Gupta, Sumit and Gupta, Rajesh K., Chapter 64: "ASIC Design", The VLSI Handbook, Copyright 2000, 29 pages. |
Hardware Verification Group, "SystemC Verification Problematic", System-on-Chip Verification , 2004, pp. 26. |
Hardware Verification Group, "SystemC Verification Problematic", System-on-Chip Verification <http://hvg.ece.concordia.ca/Research/SoC/>, 2004, pp. 26. |
Haverinen, "White Paper for SystemC based SoC Communication Modeling for the OCP Protocol", 2002, ICPIP, V1.0-Oct. 14, 2002. pp. 39. * |
Ho et al., "The Future of Wires". In Proceedings of the IEEE, vol. 89, No. 4, pp. 490-504, Apr. 2001, 15 pages. |
Hurst, Stanley L., Chapter 5: "Computer Aided Design", VLSI Custom Microelectronics: Digital, Analog, and Mixed-Signal, Copyright 1999, 95 pages. |
International Preliminary Report on Patentability for International Patent Application No. PCT/US2008/068107, mailed Feb. 1, 2010, 7 pages. The International Bureau of WIPO, Geneva, Switzerland. |
Jantsch, Axel, et al., "Networks on Chip", Kluwer Academic Publishers, 2003. Cover, Title Page, Contents, (4 pp.) Chapters 1-5, (pp. 3-106,) Chapters 7-8, (pp. 131-172) & Chapter 10, (pp. 193-213), 170 pages. |
Kurose, "Open Issues and Challenges in Providing Quality of Service Guarantees in High-Speed Networks", ACM Computer Communication Review, vol. 23, No. 1, pp. 6-15, Jan. 1993, 10 pages. |
Lahiri, K., et al., "LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs". In Proceedings of Design Automation Conference 2003, Las Vegas, Jun. 2001, pp. 15-20, 6 pages. |
Lamport, Leslie, "How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs", XP-009029909, IEEE Transactions on Computers, vol. C-28, No. 9, Sep. 1979, pp. 690-691 (double-sided copy). |
Melvin, S. and Patt, Y. 2002. Handling of packet dependencies: a critical issue for highly parallel network processors. In Proceedings of the 2002 international Conference on Compilers, Architecture, and Synthesis for Embedded Systems (Grenoble, France, Oct. 8-11, 2002). Cases '02. ACM, New York, NY, 202-209. |
Non-Final Office Action for U.S. Appl. No. 12/144,883, mailed Jun. 28, 2012, 9 pages. U.S. Patent and Trademark Office, Alexandria, Virginia, USA. |
Non-Final Office Action for U.S. Appl. No. 12/706,656, mailed Feb. 15, 2012, 26 pages. U.S. Patent and Trademark Office, Alexandria, Virginia, USA. |
Notice of Allowance for U.S. Appl. No. 12/144,883, mailed Nov. 21, 2012, 10 pages. U.S. Patent and Trademark Office, Alexandria, Virginia, USA. |
Notice to File a Response (Office Action) for Korean Patent Application No. 10-20067010659 mailed Feb. 16, 2011, 3 pages. Korean Intellectual Property Office. |
OCP (Open Core Protocol) Specification, Release 2.0, OCP International Partnership, OCP-IP Association, 210 pages, 2003. |
Office Action for European Patent Application No. 04 796 678.3-2416 dated Dec. 14, 2007, 4 pages. European Patent Office, Munich, Germany. |
Office Action for European Patent Application No. 04 796 678.3-2416 dated Mar. 27, 2009, 4 pages. European Patent Office, Munich, Germany. |
Office Action for Japanese Patent Application No. 2006-538262 mailed Dec. 6, 2010, 3 pages. Japan Patent Office. |
Office Action for Japanese Patent Application No. 2006-538262 mailed Jan. 31, 2012, 16 pages. Japan Patent Office. |
Paul Klein et al., "Passive TLM", Intel Corporation, Paul.J.Klein@intel.com, Zafer.Kadi@intel.com, Jun. 7, 2004, pp. 16. |
Reisslein et al., "A Framework for Guaranteeing Statistical QoS", In IEEE/ACM Transactions on Networking, vol. 10, No. 1, Feb. 2002, pp. 27-42, 16 pages. |
Richard Ruigrok, "Hardware-Software Co-Simulation with System C", Qualcomm Incorporated, Jun. 7, 2004, pp. 17. |
Rijpkema et al., "Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip", In Proceedings of Design Automation and Test Conference in Europe, Mar. 2003, 6 pages. |
Rixner, et al., "A Bandwidth-Efficient Architecture for Media Processing", Micro-31, (1998), pp. 1-11. |
Rixner, Scott, et al., "MemoryAccess Scheduling", to appear in ISCA27 (2000), Computer Systems Laboratory, Stanford University, Stanford, CA 94305 pp. 1-11. |
Search Report and Written Opinion for International Patent Application No. PCT/US2008/068107, mailed Oct. 8, 2008 International Searching Authority/US, Alexandria, Virginia USA. |
Sofiene Tahar, "Assertion and Model Checking of SystemC", Hardware Verification Group, Department of Electrical and Computer Engineering, Concordia University Montreal, Quebec, Canada, First Annual North American SystemC Users Group (NASCUG) Meeting, Jun. 7, 2004, pp. 28. |
Stiliadis et al., "Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms", In Proceedings of IEEE Infocom 96, Apr. 1996, pp. 111-119, 9 pages. |
Stuart Swan, Senior Architect, "System C-Towards a SystemC Transaction Level Modeling Standard", Cadence Design Systems, Inc., Jun. 2004 pp. 12. |
Summons to Oral Proceedings for European Patent Application No. 04 796 678.3-2416 dated Aug. 4, 2010, 7 pages. European Patent Office, Munich, Germany. |
Supplementary (Extended) Search Report for European Patent Application No. 08780967 dated Dec. 21, 2010, 4 pages. European Patent Office at The Hague, Netherlands. |
U.S. Appl. No. 11/203,554, filed Aug. 11, 2005, Chou et al. |
U.S. Appl. No. 13/276,041, filed Oct. 18, 2011, Wingard et al. |
United States Patent & Trademark Office, memo from Love, John J., Deputy Commissioner for Patent Examination Policy, entitled, "Clarification of Interim Guidelines for Examination of Patent Applications for Subject Matter Eligibility", Apr. 12, 2007, 2 pgs. |
Weber, Wolf-Dietrich, et al., "A Quality-of-Search Mechanism for Interconnection Networks in System-on-Chips", Section 1530-1591/05, IEEE, 6 pages, 2005. |
Weber, Wolf-Dietrich, et al., "Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol", In Proceedings of the IP 2000 System-on-Chip Conference Mar. 2000, pp. 1-5. |
Weber, Wolf-Dietrich,"Efficient Shared DRAM Subsystems for SOCs", Sonics, Inc. Systems on the ICs, 6 pages, 2001. |
Wielage et al., "Networks on Silicon: Blessing or Nightmare?" Keynote speech Proceedings of the Euromicro Symposium on Digital System Design, Dortmund, Germany, Sep. 2002, 5 pages. |
Wilson Snyder, "Verilator and SystemPerl", Sun Microsystems, VeriPool, wsnyder@wsnyder.org, http://www.veripool.com, Jun. 2004, pp. 14. |
Wingard, Drew, "A Non-Blocking Intelligent Interconnect for AMBA-Connected SoCs", Sonics, Inc., CoWare Arm Developer's Conference, 39 pages, Oct. 6, 2005. |
Wingard, Drew, "MicroNetworks-Based Integration for SOCs." In Design Automation Conference, 2001, pp. 673-677, 5 pages. |
Wingard, Drew, "Socket-Based Design Using Decoupled Interconnects", Interconnect-Centric Design for Advanced SOC and NOC, 30 pages, 2002. |
Wingard, Drew, "Tiles: The Heterogeneous Processing Abstraction for MPSoc Presentation", Sonics, Smart Interconnect IP, 35 pages, Jul. 7, 2004. |
Wingard, Drew, "Tiles-An Architectural Abstraction for Platform-Based Design," Perspective article 2, EDAVision, Jun. 2002, 3 pages, www.edavision.com. |
Wingard, Drew, et al., "Integration Architecture for System-on-a-Chip Design", In Proc. of the 1998 Custom Integrated Circuits Conference, May 1998, pp. 85-88, 4 pages. |
Wingard, Drew, PhD., "Integrating Semiconductor IP Using mu Networks," ASIC Design, Jul. 2000 electronic engineering, 3 pages. |
Wingard, Drew, PhD., "Integrating Semiconductor IP Using μ Networks," ASIC Design, Jul. 2000 electronic engineering, 3 pages. |
Wingard, Drew, Sonics SOC Integration Architecture Presentation, Systems-ON-ICS, 25 pages, Jan. 28, 1999. |
Zhang, Hui, "Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks" Proceedings of the IEEE, vol. 83, No. 10, pp. 1374-1396. Oct. 1995, DOI: 10.1109/5.469298. |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100318946A1 (en) * | 2005-10-07 | 2010-12-16 | Sonics, Inc. | Various methods and apparatuses for estimating characteristics of an electronic systems design |
US20160171138A1 (en) * | 2014-12-12 | 2016-06-16 | Freescale Semiconductor, Inc. | Method and computer system for simulating operation of a programmable integrated circuit |
US10521532B1 (en) * | 2018-09-07 | 2019-12-31 | Arm Limited | Segmented memory instances |
TWI818068B (en) * | 2018-09-07 | 2023-10-11 | 英商Arm股份有限公司 | Methods and device for segmented memory instances |
CN112052074A (en) * | 2020-09-29 | 2020-12-08 | 上海兆芯集成电路有限公司 | Processor modeling system and processor modeling method |
CN112052074B (en) * | 2020-09-29 | 2024-05-03 | 上海兆芯集成电路股份有限公司 | Processor modeling system and processor modeling method |
US11797409B1 (en) | 2022-09-02 | 2023-10-24 | HCL America Inc. | Method and system for managing transactions burstiness and generating signature thereof in a test environment |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7778815B2 (en) | Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction | |
US9311437B2 (en) | Modeling a bus for a system design incorporating one or more programmable processors | |
US10303628B2 (en) | Reordering responses in a high performance on-chip network | |
US8930593B2 (en) | Method for setting parameters and determining latency in a chained device system | |
US9600618B2 (en) | Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit | |
CN107346351A (en) | For designing FPGA method and system based on the hardware requirement defined in source code | |
US8504992B2 (en) | Method and apparatus for establishing a quality of service model | |
JP2021514084A (en) | Optimized asynchronous training of neural networks with distributed parameter servers with lively updates | |
JP2021530813A (en) | Integrated address space for multiple hardware accelerators with dedicated low latency links | |
JP2016033823A (en) | Use of completer knowledge related to memory region ordering requirements for modifying transaction attributes | |
US9087036B1 (en) | Methods and apparatuses for time annotated transaction level modeling | |
Underwood et al. | Simulating red storm: Challenges and successes in building a system simulation | |
CN114330229B (en) | Method, device, equipment and medium for delay modeling of memory | |
US10409935B2 (en) | Modeling a bus for a system design incorporating one or more programmable processors | |
Pasricha et al. | FABSYN: Floorplan-aware bus architecture synthesis | |
JP2022510803A (en) | Memory request chain on the bus | |
JP2022511581A (en) | Distributed AI training topology based on flexible cable connections | |
Pasricha et al. | Fast exploration of bus-based communication architectures at the CCATB abstraction | |
US10162913B2 (en) | Simulation device and simulation method therefor | |
US7987437B2 (en) | Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization | |
CN117312215B (en) | Server system, job execution method, device, equipment and medium | |
US20190205494A1 (en) | System and method for designing a chip floorplan using machine learning | |
US10073795B1 (en) | Data compression engine for I/O processing subsystem | |
Shin et al. | System-on-Chip Communication Modeling Style Guide | |
Danowitz | Exploring abstract interfaces in system-on-chip integration |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SONICS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOU, CHIEN-CHUN;KAMAS, ALAN;REEL/FRAME:017071/0206 Effective date: 20050812 |
|
AS | Assignment |
Owner name: PARTNERS FOR GROWTH, L.P., CALIFORNIA Free format text: SECURITY AGREEMENT;ASSIGNOR:SONICS, INC.;REEL/FRAME:016886/0376 Effective date: 20050526 |
|
AS | Assignment |
Owner name: SONICS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:PARTNERS FOR GROWTH, L.P.;REEL/FRAME:035790/0758 Effective date: 20120410 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: FACEBOOK TECHNOLOGIES, LLC, CALIFORNIA Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:SONICS, INC.;FACEBOOK TECHNOLOGIES, LLC;REEL/FRAME:049442/0332 Effective date: 20181227 |
|
AS | Assignment |
Owner name: META PLATFORMS TECHNOLOGIES, LLC, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:FACEBOOK TECHNOLOGIES, LLC;REEL/FRAME:060130/0404 Effective date: 20220318 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |