Publication number | US8874995 B2 |

Publication type | Grant |

Application number | US 13/364,390 |

Publication date | 28 Oct 2014 |

Filing date | 2 Feb 2012 |

Priority date | 2 Feb 2012 |

Also published as | CA2861410A1, CN104160452A, CN104160452B, EP2810280A1, EP2810280A4, US8869006, US20130205168, US20130205181, WO2013114230A1 |

Publication number | 13364390, 364390, US 8874995 B2, US 8874995B2, US-B2-8874995, US8874995 B2, US8874995B2 |

Inventors | Mario Blaum, James L. Hafner, Steven R. Hetzler |

Original Assignee | International Business Machines Corporation |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (37), Non-Patent Citations (17), Classifications (11), Legal Events (1) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 8874995 B2

Abstract

Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.

Claims(22)

1. A system for storing data in a storage array, the system comprising:

a storage array comprising a plurality of storage devices; and

an array controller configured for:

receiving write data;

arranging the write data in an array that includes m rows and n columns of entries, each entry comprising at least one sector;

assigning mr+s locations in the array to parity entries, such that there are at least r parity entries for each row, and further such that the parity entries correspond to a partial-maximum distance separable (PMDS) code, such code allowing recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s and r are integers greater than zero; and

writing the write data and the associated parity entries to the set of storage devices,

wherein s is less than m.

2. The system of claim 1 , wherein the data and parity entries are in a field or ring with b elements, the field or ring generated by a polynomial f(x) of degree b, and wherein the product of m and n is smaller than the exponent of f(x).

3. The system of claim 1 , wherein r=1.

4. The system of claim 1 , wherein m−1 rows contain exactly r parity entries each and one row contains r+s parity entries.

5. The system of claim 4 , wherein the r parity entries in each of the m−1 rows containing exactly r parity entries are obtained using an [n,n−r] maximum distance separable (MDS) code, and the remaining r+s parity entries are obtained by solving a system of r+s equations with r+s unknowns based on the write data, the previously obtained parity entries and a parity-check matrix corresponding to a PMDS code.

6. The system of claim 1 , wherein the parity entries are computed by solving a linear system of mr+s equations with mr+s unknowns, the linear system based on the write data and on a parity-check matrix corresponding to a PMDS code.

7. The system of claim 6 , wherein the parity-check matrix is an (m+s)×(mn) matrix, such that:

a jth row, where j is at most m, includes (j−1)m 0s followed by m 1s and followed by 0s,

an (m+1)-th row includes a 1, followed by α, followed by α^{2}, and so on, up to the last symbol of the row, which is α_{mn−1}, where α is a root of f(x), and

an (m+i)-th row, where i is a number between 2 and s, includes the entries of the (m+1)-th row taken to the power 2^{i−1}.

8. The system of claim 6 , wherein the parity-check matrix is an (m+s)×(mn) matrix, such that:

a jth row, where j is at most m, includes (j−1)m 0s followed by m 1s and followed by 0s,

an (m+1)-th row includes a 1, followed by α, followed by α^{2}, and so on, up to the last symbol of the row, which is α_{mn−1}, where α is a root of f(x),

an (m+i)-th row, where i is a number between 2 and s, includes the entries of the (m+1)-th row taken to the power i.

9. A method for storing data on a set of n storage devices, the method comprising:

receiving write data;

arranging the write data in an array that includes m rows and n columns of entries, each entry comprising at least one sector;

assigning mr+s locations in the array to parity entries, such that there are at least r parity entries for each row, and further such that the parity entries correspond to a partial-maximum distance separable (PMDS) code, such code allowing recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s and r are integers greater than zero; and

writing the write data and the associated parity entries to the set of storage devices,

wherein s is less than m.

10. The method of claim 9 ,

wherein the parity entries are computed by solving a linear system of mr+s equations with mr+s unknowns, the linear system based on the write data and on a parity-check matrix corresponding to a PMDS code.

11. The method of claim 10 , wherein the parity-check matrix is an (m+s)×(mn) matrix, such that:

a jth row, where j is at most m, includes (j−1)m 0s followed by m 1s and followed by 0s,

an (m+1)-th row includes a 1, followed by α, followed by α^{2}, and so on, up to the last symbol of the row, which is α^{mn−1}, where α is a root of f(x), and

an (m+i)-th row, where i is a number between 2 and s, includes the entries of the (m+1)-th row taken to the power 2^{i−1}.

12. The method of claim 10 , wherein the parity-check matrix is an (m+s)×(mn) matrix, such that:

a jth row, where j is at most m, includes (j−1)m 0s followed by m 1s and followed by 0s,

an (m+1)-th row includes a 1, followed by α, followed by α^{2}, and so on, up to the last symbol of the row, which is α^{mn−1}, where α is a root of f(x),

an (m+i)-th row, where i is a number between 2 and s, includes the entries of the (m+1)-th row taken to the power i.

13. The method of claim 9 , wherein the write data and parity entries are in a field or ring with b elements, the field or ring generated by a polynomial f(x) of degree b, and wherein the product of m and n is smaller than the exponent of f(x).

14. The method of claim 13 , wherein f(x) is the polynomial M_{p}(x)=1+x+x^{2}+. . . +x^{p−1 }and p is a prime number.

15. The method of claim 9 wherein r=1.

16. The method of claim 9 , wherein m−1 rows contain exactly r parity entries each and one row contains r+s parity entries.

17. The method of claim 16 , wherein the r parity entries in each of the m−1 rows containing exactly r parity entries are obtained using an [n,n−r] maximum distance separable (MDS) code, and the remaining r+s parity entries are obtained by solving a system of r+s equations with r+s unknowns based on the write data, the previously obtained parity entries and a parity-check matrix corresponding to a PMDS code.

18. A computer program product for storing data in a storage array, the computer program product comprising:

a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising:

computer readable program code configured for:

receiving write data;

arranging the write data in an array that includes m rows and n columns of entries, each entry comprising at least one sector;

assigning mr+s locations in the array to parity entries, such that there are at least r parity entries for each row, and further such that the parity entries correspond to a partial-maximum distance separable (PMDS) code, such code allowing recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s and r are integers greater than zero; and

writing the write data and the associated parity entries to the set of storage devices,

wherein s is less than m.

19. The computer program product of claim 18 , wherein the data and parity entries are in a field or ring with b elements, the field or ring generated by a polynomial f(x) of degree b and wherein the product of m and n is smaller than the exponent of f(x).

20. The computer program product of claim 18 , wherein r=1.

21. The computer program product of claim 18 , wherein m−1 rows contain exactly r parity entries each and one row contains r+s parity entries.

22. The computer program product of claim 21 , wherein the r parity entries in each of the m−1 rows containing exactly r parity entries are obtained using an [n,n−r] maximum distance separable (MDS) code, and the remaining r+s parity entries are obtained by solving a system of r+s equations with r+s unknowns based on the write data, the previously obtained parity entries and a parity-check matrix corresponding to the PMDS code.

Description

The present invention relates generally to storage systems, and more specifically, to partial-maximum distance separable (PMDS) erasure correcting codes for storage arrays.

Computer systems utilize data redundancy schemes such as parity computation to protect against loss of data on a storage device. In redundant arrays of independent disks (RAID) systems, data values and related parity values are striped across disk drives. RAID systems are typically used to protect information stored in hard disk drives (HDDs) arrays from catastrophic disk failures. Two popular RAID schemes are RAID 5 which protects against a single catastrophic disk failure and RAID 6 which protects against a double catastrophic disk failure.

Flash devices are a type of solid state non-volatile storage devices that can be electrically erased and reprogrammed in large blocks. Like HDDs, flash devices divide the medium into sectors that are typically 512 bytes. Flash devices further collect sectors into pages with typically eight sectors per page, so that each page contains four thousand or 4 kilobytes (KB). Each sector is protected by an error correcting code (ECC) that corrects a number of errors (typically, single-bit errors, although other possibilities, like byte errors, are also feasible). A popular choice is a Bose-Chaudhuri-Hocquenghem (BCH) code, like an eight bit correcting or fifteen bit correcting BCH code, although many variations are possible. As in HDDs, pages in flash devices may suffer hard errors (HEs). This occurs, for example, when the error correcting capability of the BCH code in a sector of the page is exceeded. As compared to HDDs, exceeding the capability of the BCH code is more likely in flash devices, both as a page nears the end of its write endurance lifetime, or as a page nears the end of its data retention lifetime. Thus, the number of HEs in flash devices may be expected to grow over time, leaving latent HEs on a device.

An array made up of flash devices may encounter a mix of catastrophic device failures combined with possibly more prevalent HEs. For example, use of RAID 5 for protecting information stored in flash devices may result in a device failure when there are latent HEs. Therefore, for a given data stripe (e.g., a data array that is read and/or written as a unit) if a device in a RAID 5 system experiences a catastrophic device failure, and some other device suffers a HE, a RAID 5 system will be unable to retrieve the information in the data stripe. RAID 6 may allow for the data to be retrieved, but RAID 6 requires dedicating an entire second device for parity, which is expensive when the predominant failures are HEs.

Embodiments include a system for storing data in a storage array. Write data is received and arranged in an array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

An embodiment of the present invention is a new family of erasure correcting codes having a two-dimensional structure. These erasure correcting codes are referred to herein as partial-maximum distance separable (PMDS) codes. Embodiments of the PMDS codes described herein can tolerate (i.e., recover from) a catastrophic failure and at least two additional hard errors (HEs), even when the additional HEs are located in the same row in a data array that is processed as a unit (e.g., a read data stripe, a write data stripe).

As used herein, the term “catastrophic failure” refers to the failure of an entire solid state drive (SSD), such as a flash device. As used herein, the term “erasure correction” refers to correcting an error whose location is known. An erasure correction is different than an “error correction” which, as used herein, refers to correcting an error whose location is not known. Correcting erasures requires about half of the amount of redundancy that is required to correct errors. As used herein, the term “hard error” or “HE” refers to an erasure (i.e., an error with a known location).

While error correcting codes (ECCs), such as the Bose-Chaudhuri-Hocquenghem (BCH) code, help reduce a raw bit error rate in a flash device to a lower level after correction, the final level may still be higher than a target raw bit error rate for the storage system. For example, a fifteen bit correcting BCH code may bring down a raw bit error rate of 0.001 to a raw bit error rate of 2.7 e^{−9 }after decoding a 512 byte (B) sector. However, this raw bit error rate, which represents the probability of a HE in a flash device, is substantially higher than that of a typical hard disk drive (HDD), which may range from 8 e^{−14 }to 8 e^{−16}. Higher error rates are likely to occur near the end of write endurance as well as near the end of the data retention life in a flash device.

When the error correcting capability of an ECC is exceeded, this event will be detected with a very high probability. For example, if a fifteen bit correction BCH code has been implemented and more than fifteen errors have occurred, it is very likely that the BCH code itself will detect such an event. In any case, a cyclical redundancy code (CRC) is generally added in order to assure that the probability of miscorrection is of the order of 1 e^{−26 }or so. A BCH code failing to detect a miscorrection is symptomatically equivalent to an HDD dropped write or off-track write.

Any multiple erasure correcting code known in the art may be utilized by an embodiment. One example of a multiple erasure code utilized by an embodiment is a Reed-Solomon (RS) code. RS codes are well known in the art and can be used to correct a plurality of erasures. RS codes are based on symbols, with the size of the symbols depending on the application. For a tutorial on RS codes that is relevant to RAID architectures, see J. S. Plank “A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like Systems”, *Software, Practice & Experience, *995-1012, September 1997.

Another family of efficient codes for correction of a plurality of erasures is given by the Blaum-Roth 93 (BR93) codes, as described in M. Blaum et al., New Array Codes for Multiple Phased Burst Correction“, IEEE Transactions on Information Theory, vol. 39, pp. 66-77 1993. BR93 codes are array codes that tend to be less complex than RS codes by avoiding Galois field operations and doing only exclusive-or (XOR) operations instead.

Both the RS and BR93 codes are maximum distance separable (MDS) codes, meaning that they make optimal use of the redundancy in order to correct erasures. RS and BR93 codes are examples of two types of multiple erasure correcting codes that may be utilized by embodiments described herein. Embodiments are not limited to these two codes as other families of codes may also be implemented such as a generalized EVENODD code or a generalized row diagonal code (RDC).

Contrary to arrays of hard disk drives (HDDs), arrays of SSDs present a mixed failure mode. On one hand, there are catastrophic SSDs failures, as in the case of HDDs. On the other hand, there are hard errors (HEs), which in general are silent in that their existence is not known until an attempt is made to access a sector containing a HE. This situation complicates the task of recovery in a RAID (redundant arrays of independent disks) type of architecture. For example, assume that a catastrophic SSD failure occurs in a RAID 5 architecture. Recovery is started by reconstructing each sector of the failed device by “exclusive-oring” (XORing) the corresponding sectors in each of the surviving devices. However, if there is a row that has also suffered a HE, such a row has two sectors that have failed. RAID 5 cannot recover from such an event and data loss will occur.

A possible solution to the situation above is to use a RAID 6 type of architecture, in which two SSDs are used for parity. The RAID 6 architecture allows for the recovery of two erased sectors in a row. However, such a solution may be wasteful, since it requires an additional whole device to protect against HEs. Embodiments of the PMDS code described herein provide a solution that is intermediate between RAID 5 and RAID 6 by allowing the handling of HEs without the need of dedicating a whole second SSD to parity.

In order to handle this mixed environment of HEs with catastrophic failures, the way that information is written in SSDs is taken into account. The way that information is written in SSDs is quite different than the way that information is written in HDDs. In an SSD, a new write includes first erasing a number of consecutive sectors and then rewriting all of them. Therefore, the short write operation in arrays of SSDs (e.g., one sector at a time) is not an issue here: each time a new write is performed, a data stripe of, say, M sectors in each SSD is erased and then rewritten. In this case, the parity is recomputed as part of the new write. As described herein, it is assumed that a storage array is made up of “m×n” stripes (where “n” is the number of SSDs), repeated one after the other. Each m×n stripe is an independent unit and parity for each stripe will be computed in accordance with embodiments described herein. In addition, each new write includes writing a number of m×n stripes (this number may be one, depending on the application, the particular SSD used, and other factors). Embodiments of the family of PMDS codes described here allow for the simultaneous correction of catastrophic failures and HEs.

**100** that is protected using PMDS codes in accordance with an embodiment. As shown in **102** is in communication with an array controller **104** in a storage system **110**. The storage system **110** stores data in a storage array **108** made up of n storage devices **106** (where n is greater than one): storage device zero **106** *a*, storage device one **106** *b*, storage device two **106** *c*, through storage device n-1 106*d*. In an embodiment, parity bits are stored in the storage devices **106** along with host data (e.g., represented as data bits). In an embodiment, the storage devices **106** in the storage array **108** are implemented by SSDs such as flash devices. In an embodiment, the array is made up of five flash devices, each device having a 32 Gigabyte (GB) storage capacity. As shown in **104** is part of the storage system **110**; in another embodiment, the array controller **104** is part of the host computer **102**.

**110** of **110** may include numerous other elements such as receivers, transmitters, and clocks as known by those of ordinary skill in the art, which are not illustrated for purposes of clarity. As shown in **104** includes an encoder **202** and a decoder **204**. The encoder **202** is utilized during a write process for receiving one or more write data bits (e.g., from the host computer **102**) and generating a write stripe, which includes both data entries and parity entries. Each entry includes “b” bits and may correspond to one or more pages, one or more sectors, and/or one or more symbols. In an embodiment, the write stripe is written in the storage array **108** and spans a plurality of rows in the storage array **108**. The decoder **204** is utilized during a read process for reading one or more data entries from the storage array **108**. When one or more HEs in an entry are detected, the decoder reads the whole stripe where the HE(s) has been detected from the storage array **108**. The decoder **204** and the encoder **202** both have access to shared data (e.g., data to identify the type of encoding that was applied by the encoder **202** to the write entries to generate the write stripe). The read stripe contains parity bits that are removed by the decoder **204** to generate the read data. The decoder **204** includes a reconstructor **206** that is used when a read failure of at least one data entry has occurred. A read failure occurs, for example, when the error correcting capability of the internal ECC of an entry has been exceeded. Typically, the locations of the entries in error are known and thus, the error locations (e.g., the erased entry location(s)) and the read stripe are sent to the reconstructor **206**, which attempts to retrieve the erased entries.

**106** (the data array is also referred to herein as a “stripe”). The data array is encoded as a unit by the encoder **202** using a PMDS code. As used herein, the term “encoding stripe” refers to a group of entries that together make up a write stripe and that are encoded with the PMDS code as a unit. As used herein, the term “decoding stripe” refers to a group of entries that together make up a read stripe and that are decoded with the PMDS as a unit.

The data array depicted in _{00}” is an entry at row 0, column 0 in the data array). In an embodiment, each column represents a portion of a storage device. In the stripe depicted in

In an embodiment, the decoder **204** receives a read stripe that has experienced HEs in one or more entries from the storage array **108** that has been encoded in the manner shown in **206** located in the decoder **204**.

In accordance with an embodiment, each row in the array is protected by r parity entries in such a way that any r erasures in the row will be recovered. In other words, each row of the data array constitutes an [n, n−r, r+1] MDS code. In addition, “s” extra global parities are added to the array. The s extra parities may be placed in many different ways in the data array, but in order to simplify the description, in this example, they are placed in the last row. Being global means that these parities affect all “mn” entries in the data array. For example, instance in the 4x5 data array shown below, r=1 and s=2 and there are two extra global parities placed in the last row. “D” indicates data entries and “P” indicates parity entries.

D | D | D | D | P | ||

D | D | D | D | P | ||

D | D | D | D | P | ||

D | D | P | P | P | ||

Referring to the above data array, assume that a catastrophic failure occurs (that is, a whole column in the data array has failed), and in addition, there are up to two HEs anywhere in the data array. The PMDS described herein will correct these failures (also referred to herein as erasures). The situation is illustrated in the below data arrays. In the data array on the left, the two additional HEs occur in different rows. In the array on the right, the two additional HEs occur in the same row. “F” indicates failure and “N” indicates no failure.

N F N F N | N N N F N | ||

N N N F N | N N N F N | ||

N N N F F | F N N F F | ||

N N N F N | N N N F N | ||

One approach to solving this problem is using an MDS code. In the 4×5 data array example, there are a total of six parity entries. So, it is feasible to implement an MDS code on 20 entries (e.g., symbols) with six parity entries. So, we can implement a [20,14,7] MDS code (like a RS code). A problem with this approach is its complexity. In one embodiment this MDS code is a [20,14,7] RS code. This example, where the number of rows in a data array, m, is four is given for the purpose of illustration only. More typical values of m in applications are sixteen or thirty-two, and this would result in 18 or 34 parity entries. Implementing such a code, although feasible, is complex. It is desirable for the code base, in normal operation, to utilize its underlying RAID structure based on rows, like single parity in the case of RAID 5. The extra parities are invoked on relatively rare occasions. Embodiments of the PMDS codes described herein comply with the constraint of having a horizontal code in order to utilize the underlying RAID structures. In the case of the example of RAID 5 plus two global parities, a PMDS code can correct up to one erasure per row, and in addition, two erasures anywhere. Thus, the PMDS code can correct any of the situations depicted in the data arrays above that indicate failures and non-failures.

An Embodiment of the PMDS Code is Defined as Follows in Definition 1

Definition 1. Let

be a m×n data array such that each row is encoded into a [n, n −r, r+1] MDS code, and in addition s parity symbols are added into the array. is an (r, s) PMDS code, if in addition to correcting up to r erasures per row, can correct any s erasures anywhere in the array.Code

as defined in Definition 1 is a two-dimensional code. It is assumed that the entries are read horizontally, in a row-wise manner, making the code an [mn, m(n−r)−s] linear code. Herein below actual constructions of codes are described based on their parity-check matrices, which are (mr+s)×mn matrices. **204** in accordance with an embodiment. At block **402**, the ECC and/or the CRC detect that a read of an entry has failed. At block **404**, a request is sent to read all of the entries in the stripe that contains the entry where the read has failed. At block **406**, the read stripe together with the location(s) of the entry(s) where the read has failed (i.e., the erased entry location(s)) are sent to the reconstructor **206**. At block **408**, it is determined if the number of erased entry locations in the read stripe is greater than the erasure correction capability of the scheme. For instance, if a code that can recover an erasure in each row plus two global parities has been implemented, and block **408** finds out that a whole column together with three extra entries have been erased, the erasure correction capability of the PMDS code is exceeded. If it is determined at block **408**, that the number of erased entry locations in the read stripe is greater than the capability of the PMDS scheme, then block **414** is performed to return an error condition to the decoder **204**. If it is determined at block **408**, that the number of erased entry locations is within the capacity of the PMDS scheme, then block **410** is performed. At block **410**, the read stripe is reconstructed using embodiments of the PMDS erasure correcting codes as described herein. At block **412**, the reconstructor **206** outputs the recovered read stripe including the recovered read entry (s) to the decoder **204**.

**202** to protect a m×n data array from r catastrophic errors and “s” additional errors. At block **502**, it is assumed that there are “n” columns (e.g., flash devices) and m” rows. In addition, it is assumed that the entries in the first n—r columns in the first m−1 rows, and the first n—r—s entries of the mth row contain data entries (or information entries). The rest of the entries are blank and will be encoded using the PMDS code as described herein below. At block **504**, the first m−1 rows are encoded using an [n, n−r] MDS code. In an embodiment, the results for each row are stored in the last n−r entries of the corresponding row. At block **506**, the last row is encoded by solving a linear system based on a parity-check matrix as described herein below. In an embodiment, the results are stored in the last n−r−s entries in the last row, row m−1, of the data array.

**204** for an m×n data array. At block **602**, it is assumed that there are “t” rows with up to r+s_{j }erasures each (where 1≦j≦t), where the sum of the s_{j}s adds to s, and up to r erasures in the remaining rows. At block **604**, the rows with at most r erasures are corrected using one or more [n, n−r] MDS codes. At block **606**, the “t” rows with up to r+s_{j }erasures each are corrected by computing syndromes and solving a linear system based on a parity-check matrix as described herein below.

Following is a description of code constructions for embodiments of the PMDS codes, as well as descriptions of general conditions for an erasure correcting code to be a PMDS code. In addition, specific embodiments of the PMDS code are described for selected applications.

Code Construction

As described above, each entry is made up of b bits. In an embodiment, it is assumed that each entry is in a ring. The ring is defined by a polynomial f(x) of degree b, i.e., the product of two elements in the ring (taken as polynomials of degree up to b−1), is the residue of dividing the product of both elements by f(x) (if f(x) is irreducible, the ring becomes the Galois field GF(2^{b})). Let a be a root of the polynomial f(x) defining the ring. The exponent of f(x), denoted e (f(x)), is the exponent of α, i.e., the minimum l, 0<l, such that α^{l}=1. If f(x) is primitive, e(f(x))=2^{b}−1.

A special case that will be important in applications is f(x)=1+x+ . . . +x^{p−1}, where p a prime number. In this case, e(f(x))=p and f(x) may not be irreducible. In fact, it is not difficult to prove that f(x) is irreducible if and only if 2 is primitive in GF(p). Thus, the polynomials of degree up to p−2 modulo 1+x+ . . . +x^{p−1 }constitute a ring and not generally a field. This ring was used to construct the Blaum-Roth (BR) codes, and as described in embodiments herein, it is either assumed that f(x) is irreducible or that f(x)=1+x+ . . . +x^{p−1}, where p a prime number. A general construction is defined as follows.

Construction 1. Consider the binary polynomials modulo f(x), where either f(x) is irreducible or f(x)=1+x+ . . . +x^{p−1}, p a prime number. Let mn≦e(f(x)), where e(f(x)) denotes the exponent of f(x). Let

where H(n, r, i, j) is the r×n matrix

Matrices H(n, r, i, j) as given by equation (2), in which each row is the square of the previous one, have been used in the art for constructing codes for which the metric is given by the rank, for constructing codes that can be encoded on columns and decoded on rows, and for constructing differential MDS codes.

Example 1, which follows, illustrates Construction 1.

Construction 1 provides PMDS codes for particular parameters and polynomial functions (i.e., f(x)) defining the ring or field. The received entries are denoted by (a_{i,j})_{0≦i≦m−1} _{ 0≦j≦n−1 }with the erased entries being equal to 0. The first step is computing the rm+s syndromes. For a

The case r=1. Following is a description of the case where r=1 and a description of how to use the syndromes for decoding and determining whether

(m, n, 1, s; f(x)) codes are PMDS. The parity-check matrix (m, n, 1, s) given by formula (1) is written as:(

It is assumed that Σ_{j=1} ^{t}s_{j}=s for integers s_{j}≧0. The code

Lemma 1. Consider a code

(m, n, 1, s; f(x)) and let sLemma 2. Consider a code

(m, n, 1, s; f(x)) and let s

The combination of Lemmas 1 and 2 results in the following theorem. Theorem 1. For s≧1, code

(m, n, 1, s; f(x)) as given by Construction 1 is PMDS if and only if: (1) code (m, n, 1, s−1; f(x)) is PMDS, and (2) for any (sTheorem 1 provides conditions to check in order to determine if a code

(m, n, 1, s; f(x)) as given by Construction 1 is PMDS, but by itself it does not provide any family of PMDS codes. Consider the ring of polynomials modulo f(x)=1+x+ . . . +xTheorem 2. Consider the code

(m, n, 1, s; f(x)) given by Construction 1 over the field of elements modulo f(x)=1+x+ . . . +xSo far descriptions have dealt with general values of s. In the following text special cases that may be important for applications are described.

Case where r=1 and s=1:

(m, n, 1,1; f(x))(m, n, 1,1; f(x)) is always PMDS, since by Theorem 1, the binomials of type 1+x

Theorem 3. Code

(m, n, 1,1; f(x)) is always PMDS.Case where r=1 and s=2:

(m, n, 1,2; f(x))This case is important in applications, in particular, for arrays of SSDs. Since

(m, n, 1,1; f(x)) is PMDS, Theorem 1 gives the following theorem for the case where s=2.Theorem 4. Code

(m, n, 1,2; f(x)) is PMDS if and only if, for any 1<i≦m−1, and for any 0≦lgcd(1+x

Since this case is important in applications, the decoding (of which the encoding is a special case) is described herein in some detail, the other cases being treated similarly.

Consider a PMDS code

(m, n, 1,2; f(x)), i.e., it satisfies the conditions of Theorem 4. Without loss of generality, assume that there are either three erasures in the same row iUsing the parity-check matrix

(m, n, 1,2) as given by equation (1), the following linear system is solved:a

α

α

The solution to this system is:

Since matrix:

is a Vandermonde matrix,

the ring of polynomials modulo

Since matrix

is a Vandermonde matrix,

As will be appreciated by those skilled in the art, the elements 1⊕α^{j} ^{ 1 } ^{−j} ^{ 0 }, 1⊕αj^{ 1 } ^{−j} ^{ 0 }and 1⊕α^{j} ^{ 2 } ^{−j} ^{ 1 }can be efficiently inverted in the ring of polynomials modulo 1+x+ . . . +x^{p−1}, p a prime, for instance, using the method described in Blaum and Roth, “Method and Means for Coding and Rebuilding the Data Contents of Unavailable DASDs or Rebuilding the Contents of a DASD in Error in the Presence of a Reduced Number of Unavailable DASDs in a DASD Array”, U.S. Pat. No. 5,321,246.

The encoding is a special case of the decoding. For instance, assume that the two global parities are placed in locations (m−1, n−3) and (m−1, n−2) in the array shown in _{i,n−1 }for 0≦i≦m −2 using single parity, the parities a_{m−1,n−3}, a_{m−1,n−2 }and a_{m−1,n−1 }are computed using the method above. In particular, the Vandermonde determinant becomes (making i_{0}=m−1, j_{0}=n−3, j_{1}=n−2 and j_{2}=n−1) α^{4(m+n)−15}(1⊕α)(1⊕α^{2}) (1⊕α)=α^{4(m+n)−15}(1⊕α^{4}). So, only 1⊕α^{4 }has to be inverted for the encoding, and many operations may be pre-calculated, making the encoding very efficient.

Another case is when there are two pairs of erasures in rows i_{0 }and i_{1}, 0≦i_{0}<i_{1}≦m−1. In this example, it is assumed that the erased entries are a_{i} _{ 0, } _{j} _{ 0 }and a_{i} _{ 0, } _{j} _{ 1 }in row i_{0}, 0≦j_{0}<j_{1}≦n−1, and a_{i} _{ 1, } _{l} _{ 0 }and a_{i} _{ 1, } _{l} _{ 1 }in row i_{1}, 0≦l_{0}<l_{1}≦n−1. Again, using the parity-check matrix

a

a

α

α

where S

By row operations, it is seen that this determinant is equal to the following determinant times a power of α:

It is noted that this determinant corresponds to a 2×2 Vandermonde matrix, and it equals 1⊕α^{j} ^{ 1 } ^{−j} ^{ 0 }⊕α^{(i} ^{ 1 } ^{1} ^{ 0 } ^{)n+l} ^{ 0 }(1⊕α^{l} ^{ 1 } ^{−l} ^{ 0 }) times α^{(i} ^{ 1 } ^{−i} ^{ 0 } ^{)n+l} ^{ 0 } ^{−j} ^{ 0 }(1⊕α^{j} ^{ 1 } ^{−j} ^{ 0 })(1⊕α^{l} ^{ 1 } ^{−l} ^{ 0 }). As described previously, this last expression is easy to invert in the case of a ring modulo f(x)=1+x+ . . . +x^{p−1}, p a prime number. Inverting 1⊕α^{j} ^{ 1 } ^{−j} ^{ 0 }⊕α(^{i} ^{ 1 } ^{−i} ^{ 0)n+l } ^{ 0 } ^{−l} ^{ 0 }(1⊕α^{l} ^{ 1 } ^{−l} ^{ 0 }), however, is not as neat as inverting binomials 1⊕α^{j}, as shown above. Since 1+x^{j} ^{ 1 } ^{−j} ^{ 0 }+x^{(i} ^{ 1 } ^{−i} ^{ 0 } ^{)n+l} ^{ 0 } ^{−j} ^{ 0 }(1+x^{l} ^{ 1 } ^{l} ^{ 0 }) and 1+x+ . . . +x^{p−1 }are relatively prime by Theorem 4, 1+x^{j} ^{ 1 } ^{−j} ^{ 0 }+x^{(i} ^{ 1 } ^{−i} ^{ 0 } ^{)n+l} ^{ 0 } ^{−l} ^{ 0 }(1+x^{l} ^{ 1 } ^{−l} ^{ 0 }) modulo f(x) is inverted using Euclid's algorithm. This takes some computational time, but it is not an operation done very often. When it is invoked performance has already been degraded due in general to a catastrophic failure.

Following is an analysis of some concrete PMDS codes

(m, n, 1,2; f(x)). Consider first finite fields GF(2

TABLE 1 | |||||||||

b | f(x) | e(f(x)) | m | m | b | f(x) | e(f(x)) | m | n |

8 | 4 3 5 | 255 | 5 | 5 | 16 | 2 2 7 2 1 5 | 13107 | 404 | 6 |

5 6 7 | 85 | 7 | 5 | 346 | 7 | ||||

4 3 3 | 51 | 10 | 5 | 303 | 8 | ||||

9 | 1 0 2 1 | 511 | 20 | 6 | 269 | 9 | |||

1 2 3 1 | 73 | 10 | 7 | 242 | 10 | ||||

10 | 3 0 2 5 | 1023 | 21 | 6 | 164 | 11 | |||

15 | 7 | 160 | 12 | ||||||

11 | 6 0 1 5 | 2047 | 29 | 6 | 59 | 16 | |||

5 3 6 1 | 2047 | 25 | 7 | 45 | 17 | ||||

22 | 8 | 53 | 18 | ||||||

13 | 10 | 24 | 20 | ||||||

12 | 1 5 6 47 | 4095 | 67 | 6 | 19 | 22 | |||

58 | 7 | 21 | 23 | ||||||

50 | 8 | 18 | 24 | ||||||

24 | 9 | 17 | 25 | ||||||

22 | 10 | 16 | 26 | ||||||

Next, consider the ring of polynomials modulo f(x)=1+x+ . . . +x^{p−1}, p a prime and mn <e(f(x))=p. Theorem 2 solves the case in which f(x) is irreducible, so in this case it is assumed that f(x) is not irreducible, i.e., the ring is not a field. This ring was considered for the BR codes because it allows for efficient correction of erasures for symbols of large size without using look-up tables like in the case of finite fields. All possible cases of Theorem 4 need to be checked for different values of m and n, mn<p.

The results are tabulated in Table 2, below, which gives the list of primes between 17 and 257 for which f(x) is reducible (hence, 2 is not primitive in GF(p)), together with some values of m and n, and a statement indicating whether the code is PMDS or not. For most such primes the codes are PMDS. The only exceptions are 31, 73 and 89. The case of 89 is particularly interesting, since for m=8 and n=11 as well as for m=n=9, the codes are not PMDS. However, for m=11 and n=8, the code is PMDS, which illustrates the fact that a code being PMDS does not depend only on the polynomial f(x) chosen, but also on m and n.

TABLE 2 | ||||

Prime | m | n | C(m, n, 1, 2; f(x)) PMDS? | |

17 | 4 | 4 | YES | |

23 | 3 | 7 | YES | |

4 | 5 | YES | ||

31 | 5 | 6 | NO | |

6 | 5 | NO | ||

41 | 5 | 8 | YES | |

6 | 6 | YES | ||

8 | 5 | YES | ||

43 | 5 | 8 | YES | |

6 | 7 | YES | ||

47 | 4 | 11 | YES | |

5 | 9 | YES | ||

71 | 7 | 10 | YES | |

8 | 8 | YES | ||

10 | 7 | YES | ||

73 | 6 | 12 | NO | |

7 | 10 | NO | ||

8 | 9 | NO | ||

9 | 8 | NO | ||

79 | 6 | 13 | YES | |

7 | 11 | YES | ||

8 | 9 | YES | ||

89 | 8 | 11 | NO | |

9 | 9 | NO | ||

11 | 8 | YES | ||

97 | 8 | 12 | YES | |

10 | 9 | YES | ||

12 | 8 | YES | ||

103 | 9 | 11 | YES | |

10 | 10 | YES | ||

11 | 9 | YES | ||

109 | 9 | 12 | YES | |

10 | 10 | YES | ||

12 | 9 | YES | ||

113 | 10 | 11 | YES | |

11 | 10 | YES | ||

12 | 9 | YES | ||

127 | 11 | 11 | YES | |

13 | 9 | YES | ||

137 | 11 | 12 | YES | |

12 | 11 | YES | ||

13 | 10 | YES | ||

15 | 9 | YES | ||

16 | 8 | YES | ||

151 | 15 | 10 | YES | |

16 | 9 | YES | ||

157 | 12 | 13 | YES | |

13 | 12 | YES | ||

14 | 11 | YES | ||

15 | 10 | YES | ||

16 | 9 | YES | ||

167 | 12 | 13 | YES | |

13 | 12 | YES | ||

15 | 11 | YES | ||

16 | 10 | YES | ||

191 | 13 | 14 | YES | |

14 | 13 | YES | ||

17 | 11 | YES | ||

193 | 16 | 12 | YES | |

199 | 14 | 14 | YES | |

16 | 12 | YES | ||

223 | 15 | 14 | YES | |

17 | 13 | YES | ||

229 | 15 | 15 | YES | |

16 | 14 | YES | ||

233 | 15 | 15 | YES | |

16 | 14 | YES | ||

239 | 15 | 15 | YES | |

16 | 14 | YES | ||

241 | 16 | 15 | YES | |

251 | 16 | 15 | YES | |

25 | 10 | YES | ||

257 | 16 | 16 | YES | |

32 | 8 | YES | ||

Case where r=1 and s=3: (m, n, 1,3; f(x))

There are two ways to obtain s=3 as a sum of odd numbers: one is 3 itself, the other is 1+1+1. Then, based on Theorem 1, Theorem 5 is:

Theorem 5. Code

(m, n, 1,3; f(x)) is PMDS if and only if code (m, n, 1,2; f(x)) is PMDS, and, for 1≦land, for any 1≦i

So, to check if code

(m, n, 1,3; f(x)) is PMDS, a first check is made to determine whether (m, n, 1,2; f(x)) is PMDS, similar to the cases tabulated in Tables 1 and 2 above. Then a check is made to see if equations (8) and (9) of Theorem 5 are satisfied.For instance, the codes in Table 1 are

(m, n, 1,2; f(x)) PMDS codes, but equation (9) in Theorem 5 is quite restrictive and most of the entries do not correspond to (m, n, 1,3; f(x)) PMDS codes. In Table 2, however, several of the codes that are (m, n, 1,2; f(x)) PMDS codes are also (m, n, 1,3; f(x)) PMDS codes. These results are shown in Table 3, below, which shows that for the primes 17, 43, 89, 127, 151, 241 and 257, and also for 89 with (m, n)=(11,8), the codes are not (m, n, 1,3; f(x)) PMDS codes, although they were (m, n, 1,2; f(x)) PMDS codes. Table 3 shows values of p such that 2 is not primitive in GF(p), and some codes (m, n, 1,3; f(x)), mn<p.

TABLE 3 | |||||||

C(m, n, 1, 3; | C(m, n, 1, 2; | ||||||

Prime | m | n | f(x)) PMDS? | Prime | m | n | f(x)) PMDS? |

17 | 4 | 4 | NO | 109 | 9 | 12 | YES |

23 | 3 | 7 | YES | 10 | 10 | YES | |

4 | 5 | YES | 12 | 9 | YES | ||

31 | 5 | 6 | NO | 113 | 10 | 11 | YES |

6 | 5 | NO | 11 | 10 | YES | ||

41 | 5 | 8 | YES | 12 | 9 | YES | |

6 | 6 | YES | 127 | 11 | 11 | NO | |

8 | 5 | YES | 13 | 9 | NO | ||

43 | 5 | 8 | NO | 137 | 11 | 12 | YES |

6 | 7 | NO | 12 | 11 | YES | ||

47 | 4 | 11 | YES | 151 | 15 | 10 | NO |

5 | 9 | YES | 16 | 9 | NO | ||

71 | 7 | 10 | YES | 157 | 15 | 10 | YES |

8 | 8 | YES | 16 | 9 | YES | ||

10 | 7 | YES | 167 | 16 | 10 | YES | |

73 | 6 | 12 | NO | 191 | 17 | 11 | YES |

7 | 10 | NO | 193 | 16 | 12 | YES | |

8 | 9 | NO | 199 | 16 | 12 | YES | |

9 | 8 | NO | 223 | 17 | 13 | YES | |

79 | 6 | 13 | YES | 229 | 16 | 14 | YES |

7 | 11 | YES | 28 | 8 | YES | ||

8 | 9 | YES | 233 | 23 | 10 | YES | |

89 | 8 | 11 | NO | 239 | 26 | 9 | YES |

9 | 9 | NO | 241 | 16 | 15 | NO | |

11 | 8 | NO | 24 | 10 | NO | ||

97 | 8 | 12 | YES | 251 | 25 | 10 | YES |

10 | 9 | YES | 257 | 16 | 16 | NO | |

12 | 8 | YES | 32 | 8 | NO | ||

103 | 9 | 11 | YES | ||||

10 | 10 | YES | |||||

11 | 9 | YES | |||||

Case where r=1 and s=4: (m,n, 1,4; f(x))

Similar to the previous analysis, s=4 is written as all possible sums of odd numbers. There are three ways of doing so: 4=1+3, 4=3+1 and 4=1+1+1+1. Then, based on Theorem 1, Theorem 6 is:

Theorem 6. Code

(m, n, 1,4; f(x)) as given by Construction 1 is PMDS if and only if code (m, n, 1,3; f(x)) is PMDS, and, for any 1≦i≦m−1, 0≦lfor any 1≦i≦m−1, 0≦l

and for any 1≦i

Consider next a restricted situation for a code

(m, n, 1,4; f(x)). Contemporary codes have been constructed that can recover from an erased column together with a row with up to two errors, or two different rows with up to one error each. From a coding point of view, a (m, n, 1,4; f(x)) code that is both 5-erasure correcting and (3,3)-erasure correcting will accomplish this (these conditions are actually stronger than those in contemporary codes since they do not require an erased column, as the erasures can be anywhere in the row).Notice that, according to Lemma 2, a code

(m, n, 1,4; f(x)) is 5-erasure correcting, if and only if for any 1≦lEquation (7) is exactly the condition for code

(m, n, 1,2) to be PMDS by Theorem 4. This results in the following lemma.Lemma 3. Code

(m, n, 1,4; f(x)) is both 5-erasure correcting and (3,3)-erasure correcting if and only if code (m, n, 1,2; f(x)) is PMDS and, for any 1≦lAs shown in Table 2, for the values of m, n and p for which

(m, n, 1,2; f(x)) is PMDS, equation (8) holds. Therefore, by Lemma 3, for such prime numbers p the codes (m, n, 1,4; f(x)) are both 5-erasure correcting and (3,3)-erasure correcting.Case where s=1:

(m, n, r, 1; f(x))Thus far, cases where r=1 have been described. If r=s=1, then as described earlier, the code is PMDS. What follows is an examination of the case where r>1. Thus, assume that row i, 0≦i≦m−1, has r+1 erasures in locations 0≦j_{0}<j_{1}< . . . <j_{r}≦n−1. The following theorem, Theorem 7 gives the conditions for the codes to be PMDS.

Theorem 7. Consider code

(m, n, r, 1; f(x)). If r is even, then (m, n, r, 1; f(x)) is PMDS if and only if (m, n, r 1,1; f(x)) is PMDS, while if r is odd, (m, n, r, 1; f(x)) is PMDS if and only if (m, n, r 1,1; f(x)) is PMDS and, for any 1≦l

As described earlier,

(m, n, 1,1; f(x)) is PMDS. Thus, by Theorem 7, also (m, n, 2,1; f(x)) is PMDS. According to equation (13), (m, n, 3,1; f(x)) and (m, n, 4,1; f(x)) are PMDS if and only if, for any 1≦lCase where r=2 and s=1:

(m, n, 2, 2; f(x))For

(m, n, 2,2; f(x)) to be PMDS, it has to be both 4-erasure-correcting and (3,3)-erasure-correcting. As described previously, (m, n, 2,2; f(x)) is 4-erasure correcting if and only if, for any 1≦lTheorem 8. Code

(m, n, 2,2; f(x)) is PMDS if and only if code (m, n, 3,1; f(x)) is PMDS and, for any 1≦i≦m−1, 0≦lthen gcd (g(x), f(x))=1.

Alternate Construction

Following is a description of an embodiment of a PMDS code construction that is an alternative to Construction 1 described previously.

Construction 2. Consider the binary polynomials modulo f(x), where either f(x) is irreducible or f(x)=1+x+ . . . +x^{p−1}, p a prime number, and let mn≦e(f(x)). Let

where H(n, r, i, j) is the r×n matrix

and __0__(n, r) is an r×n zero matrix.

Next, Construction 2 is illustrated with some examples. In the first example, m=3 and n=5. Then:

Note that

(m, n, 1,2; f(x)) andCase where s=1:

Conditions under which conditions code

is invertible. Since α^{in+j} ^{ t }≠α^{in+j} ^{ l }for 0≦t<l≦r, when f(x) is irreducible α^{in} ^{+j} ^{ t }⊕α^{in+j} ^{ l }is invertible. When f(x)=1+x+ . . . +x^{p−1}, p a prime, and f(x) is reducible, then α^{in+j} ^{ t }⊕αα^{in+j} ^{ l }is also invertible. This results in Theorem 9.

Theorem 9. Code

Comparing Theorems 7 and 9, it is concluded that codes

Case where r=1 and s=3:

The following theorem holds.

Theorem 10. Code

and for any 1≦i_{2}<i_{3}≦m−1, 0≦l_{1,0}<l_{1,1}≦n−1, 0≦l_{2,0}<l_{2,1}≦n−1 and 0≦l_{3,0}<l_{3,1}≦n−1, the following matrix is invertible:

Consider f(x)=1+x+ . . . +x^{p−1}, p a prime number. All prime numbers p such that 2 is primitive in GF(p) up to p=227 were tested (i.e., f(x) is irreducible), and the matrices given by equations (16) and (17) are invertible in all instances. This results in Lemma 4.

Lemma 4. Consider the code

For values of p such that 2 is not primitive in GF(p), some results are tabulated in Table 4 for different values of m and n. This table is very similar to Table 3.

TABLE 4 | ||||

Prime | m | n C^{(1)} |
(m, n, 1, 3; f(x)) PMDS? | |

7 | 4 | 4 | NO | |

23 | 3 | 7 | NO | |

4 | 5 | YES | ||

31 | 5 | 6 | NO | |

6 | 5 | NO | ||

41 | 5 | 8 | NO | |

6 | 6 | YES | ||

8 | 5 | YES | ||

43 | 5 | 8 | NO | |

6 | 7 | NO | ||

47 | 4 | 11 | YES | |

5 | 9 | YES | ||

71 | 7 | 10 | YES | |

8 | 8 | YES | ||

10 | 7 | YES | ||

73 | 6 | 12 | NO | |

7 | 10 | NO | ||

8 | 9 | NO | ||

9 | 8 | NO | ||

79 | 6 | 13 | YES | |

7 | 11 | YES | ||

8 | 9 | YES | ||

89 | 8 | 11 | NO | |

9 | 9 | NO | ||

11 | 8 | NO | ||

97 | 8 | 12 | YES | |

10 | 9 | YES | ||

12 | 8 | YES | ||

103 | 9 | 11 | YES | |

10 | 10 | YES | ||

11 | 9 | YES | ||

109 | 9 | 12 | YES | |

10 | 10 | YES | ||

12 | 9 | YES | ||

113 | 10 | 11 | NO | |

11 | 10 | NO | ||

12 | 9 | NO | ||

127 | 11 | 11 | NO | |

13 | 9 | NO | ||

137 | 11 | 12 | YES | |

12 | 11 | YES | ||

13 | 10 | YES | ||

15 | 9 | YES | ||

16 | 8 | YES | ||

151 | 15 | 10 | NO | |

16 | 9 | NO | ||

157 | 12 | 13 | YES | |

13 | 12 | YES | ||

16 | 9 | YES | ||

167 | 16 | 10 | YES | |

191 | 17 | 11 | YES | |

193 | 16 | 12 | YES | |

199 | 16 | 12 | YES | |

223 | 17 | 13 | YES | |

229 | 16 | 14 | YES | |

28 | 8 | YES | ||

233 | 23 | 10 | YES | |

239 | 26 | 9 | YES | |

241 | 24 | 10 | NO | |

251 | 25 | 10 | YES | |

257 | 16 | 16 | NO | |

32 | 8 | NO | ||

Actually, comparing Table 3 and Table 4, it can be seen that for values of p, m and n for which

The following description includes additional code constructions and descriptions of embodiments of PMDS codes.

Technical effects and benefits include PMDS codes that are suitable for a flash array type of architecture, in which hard errors co-exist with catastrophic device failures. Described herein are specific codes that are useful in applications, as well as necessary and sufficient conditions for PMDS codes satisfying an optimality criterion. Technical effects and benefits also include the ability to provide the same protection as a redundant array of independent disks RAID 6, but with storage efficiency approaching that of RAID 5. Thus, an embodiment may be utilized to maximize the protection against stripe failures for a given amount of redundancy.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Further, as will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method, or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present invention are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

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Classifications

U.S. Classification | 714/770, 714/6.2 |

International Classification | G11C29/00, G06F11/10 |

Cooperative Classification | H03M13/033, G06F11/108, G06F2211/1059, G06F11/1076, G06F2211/1057, G06F11/1092, C06F11/1092 |

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