US8214702B2 - Distributed joint test access group test bus controller architecture - Google Patents
Distributed joint test access group test bus controller architecture Download PDFInfo
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- US8214702B2 US8214702B2 US12/614,512 US61451209A US8214702B2 US 8214702 B2 US8214702 B2 US 8214702B2 US 61451209 A US61451209 A US 61451209A US 8214702 B2 US8214702 B2 US 8214702B2
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- 238000004891 communication Methods 0.000 description 6
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
Definitions
- JTAG Joint Test Access Group
- OSP on-board scan programming
- PROM programmable read only memory
- FPGA field programmable gate array
- a JTAG architecture used for OSP has typically included one test bus controller (TBC) and one or more test access port (TAP) chains. If an apparatus (e.g., server) had more than one circuit board to be programmed using OSP, then a TAP chain typically spanned the multiple circuit boards.
- JTAG based OSP became difficult, if even possible at all for some apparatus (e.g., enterprise servers).
- apparatus e.g., enterprise servers.
- flight time limits of long traces mandated slower clock speeds for JTAG based OSP operations.
- clock speeds were being forced to go slower, the number of programmable elements to program using OSP was increasing, as was the size of the programmable elements.
- using a single TBC required serial operation where one programmable element would be completely processed before processing of the next programmable element could be started. Programming a set of programmable devices could take an unacceptable amount of time due to the combination of slow clocks and serial operation.
- FIG. 1 illustrates one embodiment of an apparatus associated with a distributed JTAG TBC architecture.
- FIG. 2 illustrates one embodiment of an apparatus associated with a distributed JTAG TBC architecture.
- FIG. 3 illustrates one embodiment of a method for controlling OSP in a distributed JTAG TBC architecture.
- FIG. 4 illustrates one embodiment of a method for controlling OSP in a distributed JTAG TBC architecture.
- the distributed JTAG TBC architecture may reside in a complex apparatus (e.g., enterprise class server).
- the complex apparatus may have a plurality of circuit boards.
- the circuit boards may have programmable elements to be programmed using OSP.
- example apparatus and methods employ a parallel approach and higher clock speeds.
- the parallel approach and higher clock speeds are attainable by using more than one TBC and by limiting TAP chains to a single circuit board.
- a TBC is placed on a circuit board having a programmable element to be programmed using OSP.
- OSP programmable element to be programmed using OSP.
- example apparatus and methods would work with ten TBCs, one per circuit board.
- the ten TBCs are arranged one per circuit board, on the circuit board.
- a control logic could distribute control signals and data to the ten circuit boards via the ten TBCs, and then OSP could occur in parallel or at least partially in parallel on the ten circuit boards.
- the degree of parallelism achieved may depend, for example, on the distribution method employed to distribute the control signals and data.
- the degree of parallelism may also depend, for example, on the amount of time required to complete OSP for a programmable element on a circuit board.
- references to “one embodiment”, “an embodiment”, “one example”, “an example”, and so on, indicate that the embodiment(s) or example(s) so described may include a particular feature, structure, characteristic, property, element, or limitation, but that not every embodiment or example necessarily includes that particular feature, structure, characteristic, property, element or limitation. Furthermore, repeated use of the phrase “in one embodiment” does not necessarily refer to the same embodiment, though it may.
- FIG. 1 illustrates an apparatus 100 .
- Apparatus 100 forms part of a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture.
- Apparatus 100 includes a circuit board 130 .
- the circuit board 130 includes a programmable component 134 that can be programmed using JTAG on-board scan programming (OSP).
- OSP JTAG on-board scan programming
- the programmable component 134 can be a programmable read only memory (PROM), a field programmable gate array (FPGA), or other programmable device.
- the circuit board 130 includes a test bus controller (TBC) 132 .
- the TBC 132 is configured to produce a set of JTAG OSP commands from scan information provided to the circuit board 130 .
- the TBC 132 can then provide the set of JTAG OSP commands to a TAP chain on circuit board 130 to control OSP of the programmable component 134 .
- the TAP chain may include, for example, TAPs 136 - 138 .
- Apparatus 100 also includes an intra-complex management network 110 .
- the intra-complex management network 110 is configured to communicate scan information between elements that provide scan information and elements that receive and use scan information.
- the scan information includes control signals and data associated with OSP of the programmable component 134 on circuit board 130 .
- the scan information includes control signals that control how the programmable component 134 is to be dynamically programmed.
- the scan information also includes data that is programmed into the programmable component 134 using OSP.
- the scan information does not include JTAG commands, but instead includes encoded JTAG commands with an additional layer of abstraction.
- the encoded JTAG commands are configured to be translated into JTAG commands by the TBC.
- Apparatus 100 also includes an on-board administration logic 120 .
- the on-board administration logic 120 is configured to place the scan information on the intra-complex management network 110 . Placing the scan information on the intra-complex management network 110 may include, for example, controlling a bus, controlling inter-process communications, controlling a network, and controlling other communications equipment and/or processes.
- the on-board administration logic 120 can be (but is not limited to) hardware, firmware, instructions in execution on a machine, and/or combinations of each to perform a function(s) or an action(s), and/or to cause a function or action from another logic, method, apparatus, and/or system.
- Logic 120 may include a software controlled microprocessor, a discrete logic (e.g., ASIC), an analog circuit, a digital circuit, a programmed logic device, a memory device containing instructions, and so on.
- Logic 120 may include one or more gates, combinations of gates, or other circuit components. Other “logics” described herein may take forms similar to those described in connection with logic 120 .
- Circuit board 130 is configured to receive the scan information that is delivered from the on-board administration logic 120 via the intra-complex management network 110 .
- the circuit board 130 includes one or more test access port(s) (TAP)s 136 - 138 that are arranged in a TAP chain that is confined to the circuit board 130 . Being confined to a single circuit board, the TAP chain can be clocked at a rate faster than conventional JTAG systems. Therefore, in one example, apparatus 100 includes a JTAG clock that is configured to clock the TAP chain at a rate of at least 10 MHz.
- 10 MHz is but one example and that other frequencies may be employed.
- the TBC 132 is configured as a host interface for the TAP chain 136 - 138 , and at least one of the TAPs 136 - 138 is configured as a slave interface for the TAP chain 136 - 138 . Therefore, one skilled in the art will appreciate that in one example the clock rate generated by the TBC is configurable to adapt to the maximum speeds of the TAPs in the chain(s) connected to a TBC.
- FIG. 2 illustrates another embodiment of apparatus 100 .
- apparatus 100 includes two circuit boards 130 and 140 . While two circuit boards 130 and 140 are illustrated, one skilled in the art will appreciate that apparatus 100 can include more than two circuit boards.
- the on-board administration logic 120 is configured to provide scan information to the two circuit boards 130 and 140 .
- the scan information may be distributed in parallel, substantially in parallel, and in other fashions. In one example, a complete set of scan information may be provided to circuit board 130 and then a complete set of scan information may be provided to circuit board 140 . In another example, scan information may be made available to a set of circuit boards that can distinguish and accept scan information based on circuit board address. In other examples, scan information may be distributed in parts using a round-robin fashion, may be distributed in parts on an as-needed basis, or may be distributed using other distribution techniques.
- circuit board 130 may be configured to perform OSP independent of OSP performed on circuit board 140 .
- TBC 132 may receive scan information from on-board administration logic 120 , may produce JTAG commands from the scan information, and then provide the JTAG commands to TAPs 136 through 138 to program programmable OSP component 134 .
- TBC 142 may receive scan information from on-board administration logic 120 , may produce JTAG commands from the scan information, and then provide the JTAG commands to TAPs 146 through 148 to program programmable OSP component 144 .
- programmable component 134 and programmable component 144 can be programmed using OSP at the same time.
- programmable component 134 and programmable component 144 would have been subjected to OSP one after another (e.g., serially), rather than in parallel. Furthermore, due to timing constraints associated with the physical design of communication traces, communication lines, and other communication hardware, programmable component 134 and programmable component 144 would have been clocked at a slower rate than is possible on circuit board 130 and circuit board 140 . Therefore, the apparatus 100 illustrated in FIG. 2 can achieve OSP of programmable component 134 and programmable component 144 faster than conventional systems.
- Example methods may be better appreciated with reference to flow diagrams. While for purposes of simplicity of explanation, the illustrated methodologies are shown and described as a series of blocks, it is to be appreciated that the methodologies are not limited by the order of the blocks, as some blocks can occur in different orders and/or concurrently with other blocks from that shown and described. Moreover, less than all the illustrated blocks may be used to implement an example methodology. Blocks may be combined or separated into multiple components. Furthermore, additional and/or alternative methodologies can employ additional, not illustrated blocks.
- FIG. 3 illustrates a method 300 associated with controlling a distributed JTAG TBC architecture.
- Method 300 includes, at 310 , providing first OSP data to a first circuit board configured with a first TBC.
- the first circuit board is located in a computer (e.g., server).
- Method 300 also includes, at 320 , providing second OSP data to a second circuit board configured with a second TBC.
- the second circuit board is located in the same computer (e.g., server) as the first circuit board. Note that both circuit boards are configured with their own TBCs.
- method 300 describes communicating with a first circuit board and a second circuit board, one skilled in the art will appreciate that a greater number of circuit boards having programmable elements may reside in one machine (e.g., server) and that method 300 may therefore provide data to more than two circuit boards.
- Method 300 also includes, at 370 , controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.
- controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board comprises providing a control signal to the first TBC and to the second TBC.
- the control signal may be a non-JTAG command provided with scan information.
- FIG. 4 illustrates additional detail about method 300 .
- the embodiment of method 300 illustrated in FIG. 4 includes, at 330 , controlling the first TBC to produce a first set of JTAG commands to control OSP on the first circuit board.
- This embodiment of method 300 also includes, at 340 , controlling the second TBC to produce a second set of JTAG commands to control OSP on the second circuit board.
- the TBCs may accept non-JTAG scan information and produce JTAG commands.
- the embodiment of method 300 illustrated in FIG. 4 includes, at 350 , controlling the first TBC to provide the first set of JTAG commands to a first TAP chain on the first circuit board.
- the embodiment of method 300 illustrated in FIG. 4 includes, at 360 , controlling the second TBC to provide the second set of JTAG commands to a second TAP on the second circuit board.
- programmable elements on the circuit boards can be subjected to OSP in parallel and/or substantially in parallel.
- Apparatus 100 illustrates a distributed JTAG TBC architecture.
- Method 300 illustrates controlling a distributed JTAG TBC architecture.
- Apparatus 100 and method 300 therefore illustrate means for providing OSP data to a plurality of circuit boards arranged in a server, where an individual circuit board includes a TBC, a TAP, and an OSP programmable element.
- apparatus 100 and method 300 provide means for controlling the plurality of circuit boards to perform OSP, in parallel, to program programmable elements on the plurality of circuit boards.
- the means include, but are not limited to, processes in execution, communication networks, and circuits.
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US20140325299A1 (en) * | 2013-04-30 | 2014-10-30 | Hon Hai Precision Industry Co., Ltd. | Testing system and testing method for motherboard |
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