Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7888185 B2
Publication typeGrant
Application numberUS 11/506,144
Publication date15 Feb 2011
Filing date17 Aug 2006
Priority date17 Aug 2006
Also published asUS20080122113
Publication number11506144, 506144, US 7888185 B2, US 7888185B2, US-B2-7888185, US7888185 B2, US7888185B2
InventorsDavid J. Corisis, Chin Hui Chong, Choon Kuan Lee
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US 7888185 B2
Abstract
Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.
Images(12)
Previous page
Next page
Claims(22)
1. A semiconductor device assembly comprising:
a plurality of semiconductor devices stacked one over another comprising:
a first semiconductor device comprising a first major surface, an opposing second major surface, and at least one conductive element on or in at least the first major surface thereof; and
a second semiconductor device situated at least partially over the first major surface or the second major surface of the first semiconductor device, the second semiconductor device comprising a first major surface, an opposing second major surface, and at least one conductive element on or in at least the first major surface thereof; and
at least three discrete self-supporting conductive leads, each comprising a first end and a second end, the first ends of the at least three self-supporting conductive leads being structurally and electrically coupled together and extending over one of the first major surface and the second major surface of the first semiconductor device, each of the at least three self-supporting conductive leads extending around a side of the first semiconductor device, the second ends of the at least three self-supporting conductive leads extending over a major surface of a semiconductor device of the plurality of semiconductor devices, and the second ends of the at least three self-supporting conductive leads being structurally and electrically coupled to a conductive element of a semiconductor device of the plurality of semiconductor devices.
2. The semiconductor device assembly of claim 1, wherein the second end of at least one self-supporting conductive lead of the at least three self-supporting conductive leads is disposed between the first semiconductor device and the second semiconductor device.
3. The semiconductor device assembly of claim 1, wherein the second major surface of the second semiconductor device is adjacent the second major surface of the first semiconductor device, the at least one conductive element of the first semiconductor device being structurally and electrically coupled to the first end of at least one self-supporting conductive lead of the at least three self-supporting conductive leads and the at least one conductive element of the second semiconductor device being structurally and electrically coupled to the second end of the at least one self-supporting conductive lead.
4. The semiconductor device assembly of claim 1, wherein at least one self-supporting conductive lead of the at least three self-supporting conductive leads extends over the first major surface of the first semiconductor device and around a side of the first semiconductor device and a side of the second semiconductor device.
5. The semiconductor device assembly of claim 1, wherein at least one self-supporting conductive lead of the at least three self-supporting conductive leads is structurally and electrically coupled to a substrate.
6. The semiconductor device assembly of claim 1, wherein the at least three self-supporting conductive leads consist essentially of metal or a metal alloy.
7. The semiconductor device assembly of claim 1, wherein the first semiconductor device and the second semiconductor device each comprise a substantially bare semiconductor die.
8. The semiconductor device assembly of claim 1, wherein the first semiconductor device and the second semiconductor device each comprise a semiconductor device package.
9. The semiconductor device assembly of claim 1, further comprising:
at least another semiconductor device situated at least partially over the second semiconductor device, the at least another semiconductor device comprising a first major surface, an opposing second major surface, and at least one conductive element on or in at least the first major surface thereof; and
at least another self-supporting conductive lead having a first end structurally and electrically coupled to the first end of the at least three self-supporting conductive leads and a second end structurally and electrically coupled to the at least one conductive element of the at least another semiconductor device.
10. The semiconductor device assembly of claim 1, further comprising a plurality of lead stacks, each lead stack comprising a plurality of self-supporting conductive leads, each conductive lead of the plurality of self-supporting conductive leads having a first end and a second end, the first ends of the plurality of self-supporting conductive leads being structurally and electrically coupled together, the second ends of the plurality of self-supporting conductive leads being structurally and electrically coupled to a conductive element of a semiconductor device.
11. The semiconductor device assembly of claim 2, wherein the first major surface of the second semiconductor device is disposed adjacent the second major surface of the first semiconductor device, the at least one conductive element of the first semiconductor device being structurally and electrically coupled to the first end of the at least one self-supporting conductive lead and the at least one conductive element of the second semiconductor device being structurally and electrically coupled to the second end of the at least one self-supporting conductive lead.
12. The semiconductor device assembly of claim 2, wherein the first major surface of the second semiconductor device is adjacent the first major surface of the first semiconductor device, the at least one conductive element of the first semiconductor device and the at least one conductive element of the second semiconductor device each being structurally and electrically coupled to the second end of the at least one self-supporting conductive lead.
13. The semiconductor device assembly of claim 4, wherein the second major surface of the second semiconductor device is adjacent the first major surface of the first semiconductor device, the at least one conductive element of the first semiconductor device being structurally and electrically coupled to the second end of at least another self-supporting conductive lead of the at least three self-supporting conductive leads and the at least one conductive element of the second semiconductor device being structurally and electrically coupled to the second end of the at least one self-supporting conductive lead.
14. The semiconductor device assembly of claim 5, wherein the substrate comprises one of a motherboard, a daughterboard, an interposer substrate, and a carrier substrate.
15. The semiconductor device assembly of claim 9, wherein the first end of the at the least one self-supporting conductive lead of the at least three self-supporting conductive leads is disposed between the first major surface of the first semiconductor device and the first end of at least another self-supporting conductive lead of the at least three self-supporting conductive leads.
16. The semiconductor device assembly of claim 10, wherein each lead stack of the plurality of lead stacks comprises two, three, or four self-supporting conductive leads.
17. The semiconductor device assembly of claim 16, wherein the semiconductor device assembly includes a total of four semiconductor devices.
18. A semiconductor device assembly comprising:
a first semiconductor device having a first major surface, an opposing second major surface, and at least one conductive element on or in at least one of the first major surface or the second major surface thereof;
at least a second semiconductor device situated at least partially over the first major surface or the second major surface of the first semiconductor device, the second semiconductor device having a first major surface, an opposing second major surface, and at least one conductive element on or in at least one of the first major surface and the second major surface thereof;
a first conductive pathway having a first end disposed over the first major surface of the first semiconductor device and a second end disposed over the second major surface of the first semiconductor device, the first conductive pathway extending around a side of the first semiconductor device, the at least one conductive element of the first semiconductor device being electrically coupled to the first end or the second end of the first conductive pathway;
at least a second conductive pathway communicating electrically with the first conductive pathway and having a first end disposed adjacent the first end of the first conductive pathway and a second end disposed over the first major surface or the second major surface of the second semiconductor device, the second conductive pathway extending around a side of the first semiconductor device and a side of the second semiconductor device, the at least one conductive element of the second semiconductor device being electrically coupled to the first conductive pathway or the second conductive pathway, wherein the first conductive pathway and the second conductive pathway each comprise a conductive trace carried by a carrier substrate and the carrier substrate comprises a flexible dielectric material; and
a conductive via extending through the conductive trace and the carrier substrate of the first conductive pathway and the second conductive pathway.
19. The semiconductor device assembly of claim 18, wherein the first end of the first conductive pathway is disposed between the first major surface of the first semiconductor device and the first end of the at least a second conductive pathway.
20. A system comprising at least one electronic signal processor configured to communicate with at least one memory device, wherein at least one of the at least one signal processor and the at least one memory device comprises a semiconductor device assembly comprising:
a plurality of semiconductor devices stacked one over another comprising:
a first semiconductor device comprising a first major surface, an opposing second major surface, and at least one conductive element on or in at least the first major surface thereof; and
a second semiconductor device situated at least partially over the first major surface or the second major surface of the first semiconductor device, the second semiconductor device comprising a first major surface, an opposing second major surface, and at least one conductive element on or in at least the first major surface thereof; and
at least three self-supporting conductive leads, each comprising a first end and a second end, the first ends of the at least three self-supporting conductive leads being structurally and electrically coupled together and extending over one of the first major surface and the second major surface of the first semiconductor device, each of the at least three self-supporting conductive leads extending around a side of the first semiconductor device, the second ends of the at least three self-supporting conductive leads extending over a major surface of a semiconductor device of the plurality of semiconductor devices, and the second ends of the at least three self-supporting conductive leads being structurally and electrically coupled to a conductive element of a semiconductor device of the plurality of semiconductor devices.
21. The system of claim 20, further comprising at least one input device and at least one output device.
22. The system of claim 20, wherein the system comprises one of a computer system, a computer subsystem, a portable telephone, an audio player, a digital camera, a video player, and a visual display.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate generally to semiconductor device assemblies that include more than one semiconductor die. More specifically, embodiments of the present invention relate generally to semiconductor device assemblies that include electrically conductive paths that provide electrical communication between semiconductor dice in such semiconductor device assemblies and conductive structures of a substrate to which the semiconductor dice are structurally and electrically coupled. Embodiments of the present invention further relate to semiconductor device assemblies, to methods of fabricating such semiconductor device assemblies and to systems that include such semiconductor device assemblies.

2. Background of Related Art

In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices coupled thereto, various types of increased circuit density semiconductor devices have been developed. Some types of semiconductor device assemblies include semiconductor dice or semiconductor device packages that are stacked one over another. Among these various types of semiconductor devices are stacked multi-chip modules (MCMs) and package-on-package (POP) assemblies. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor dice or semiconductor device packages is readily apparent. A stack of semiconductor dice or semiconductor device packages may consume roughly as little real estate on a carrier substrate as a single, horizontally oriented semiconductor die or semiconductor device package.

Another benefit of stacked semiconductor device assemblies is flexibility in manufacturing, as they provide a variety of configurations, while enabling high-volume semiconductor device production. By way of example and not limitation, stacked semiconductor device assemblies may be manufactured that combine various numbers of like semiconductor devices, such as dynamic random-access memory (DRAM) devices, providing a memory module that may be configured to a selected storage capacity. Stacked semiconductor device assemblies may also be manufactured that combine various numbers of different semiconductor devices. For example, a semiconductor device assembly may include a DRAM device, a non-volatile Flash memory device, and an application specific integrated circuit (ASIC) device, thereby combining the functionality of each semiconductor device into a single module. This is advantageous, as one may use a relatively small variety of semiconductor devices, which may be combined in a diversity of ways, and create a large variety of stacked semiconductor device assemblies with differing functionalities.

Semiconductor device assemblies typically include electrically conductive paths that provide electrical communication between the dice and a substrate to which dice are, or may be, attached. The electrically conductive paths are conventionally formed on or within a substrate, which provides them with support and mutual electrical isolation. Various designs of semiconductor device assemblies including such conductive paths have been disclosed in the art.

U.S. Pat. No. 5,977,640, to Bertin et al., which issued Nov. 2, 1999, discloses a stacked multi-chip module, including a chip-on-chip (COC) component, where the active region of a first chip is electrically coupled to the active region of a second chip. The COC component is coupled to a substrate, the upper surface of the substrate having solderable metallurgical pads and the lower surface having solder balls. Multiple components can then be stacked and coupled, with the solder balls on the bottom surface of a component corresponding to the metallurgical pads on the top surface of another component.

U.S. Pat. No. 6,020,629, to Farnworth et al., which issued Feb. 1, 2000 and is assigned to the assignee of the present invention, discloses a stacked multi-chip module, including multiple substrates, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate. Interlevel conductors through the substrate interconnect the external contacts and contact pads. The external contact pads on a substrate are bonded to the contact pads on an adjacent substrate, such that all of the dice in the package are interconnected.

U.S. Pat. No. 6,072,233, to Corisis et al., which issued Jun. 6, 2000 and is assigned to the assignee of the present invention, discloses a package-on-package assembly in which fine ball grid array (FBGA) packages are stacked one upon another. Each FBGA package is configured such that conductive elements on the package extend beyond one or more of the major surfaces and make contact with adjacent FBGA packages in the stack.

U.S. Pat. No. 6,225,688, to Kim et al., which issued May 1, 2001, discloses a stacked multi-chip module, which includes a flexible substrate having a wiring layer with conductive paths extending to a plurality of attachment sites. A plurality of microelectronic components is assembled to the attachment sites, and the flexible substrate is folded so as to provide a stacked assembly with conductive terminals exposed at the bottom end of the stack.

U.S. Pat. No. 6,323,060, to Isaak, which issued Nov. 27, 2001, discloses a stacked multi-chip module, including multiple flex circuit integrated circuit (IC) packages. The patent teaches a flex circuit, which is comprised of a flexible base with a conductive pattern disposed thereon, that is wrapped around a frame, having an IC device mounted there within. The conductive pattern of the flex circuit is electrically coupled to the IC device, forming a stackable flex circuit IC package. Multiple flex circuit IC packages can then be stacked and electrically coupled using a conductive epoxy.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of the embodiments of the present invention can be more readily ascertained from the following description of various embodiments of the invention when read in conjunction with the accompanying drawings in which:

FIG. 1 is a side view of one example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 2 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 3 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 4 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 5 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 6 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 7 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIGS. 8-17 illustrate one example of a method for forming a semiconductor device assembly that embodies teachings of the present invention;

FIGS. 18-21 illustrate another example of a method for forming a semiconductor device assembly that embodies teachings of the present invention;

FIG. 22 illustrates yet another example of a method for forming a semiconductor device assembly that embodies teachings of the present invention; and

FIG. 23 is a schematic diagram of a system that embodies teachings of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In the description which follows, like features and elements may be identified by the same or similar reference numerals for ease of identification and enhanced understanding of the disclosure hereof. Such identification is by way of convenience for the reader only, however, and is not limiting of the present invention or an implication that features and elements of various components and embodiments identified by like reference numerals are identical or constrained to identical functions.

In one embodiment, the present invention includes a semiconductor device assembly that includes a plurality of semiconductor devices stacked one over another. At least one conductive pathway extends around a side of one semiconductor device in the assembly such that a first end thereof extends generally over a first major surface thereof and a second end extends generally over a second major surface thereof. The conductive pathway may include a self-supporting conductive lead or a conductive trace carried by a carrier substrate. Optionally, the semiconductor device assembly may include an additional conductive pathway that communicates electrically with the first conductive pathway and extends around the sides of at least two semiconductor devices of the assembly.

In another embodiment, the present invention includes a system having at least one electronic signal processor configured to communicate electrically with at least one memory device. At least one of the at least one electronic signal processor and the at least one memory device includes a semiconductor device assembly that includes a plurality of semiconductor devices stacked one over another. At least one conductive pathway extends around a side of one semiconductor device in the assembly such that a first end thereof extends generally over a first major surface thereof and a second end extends generally over a second major surface thereof. The at least one conductive pathway may include a self-supporting conductive lead or a conductive trace carried by a carrier substrate. Optionally, an additional conductive pathway may communicate electrically with the first conductive pathway and extend around the sides of at least two semiconductor devices of the assembly.

In yet another embodiment, the present invention includes a method of forming a semiconductor device assembly that includes at least two semiconductor devices. The method includes structurally and electrically coupling a conductive element of a first semiconductor device to an end of a conductive pathway and bending the conductive pathway around a side of the semiconductor device to position another end of the conductive pathway on an opposite side of the semiconductor device. A second semiconductor device then may be structurally and electrically coupled to the end of the conductive pathway positioned on the opposite side of the semiconductor device.

Several non-limiting examples of various embodiments of the present invention are described in further detail below.

Referring to FIG. 1, an embodiment of the present invention in the form of semiconductor device assembly 10 that comprises a plurality of semiconductor devices 12A-12D is depicted. As shown in FIG. 1, the semiconductor devices 12A-12D may be substantially bare semiconductor dice.

The semiconductor device assembly 10 may include a first semiconductor device 12A, a second semiconductor device 12B, a third semiconductor device 12C, and a fourth semiconductor device 12D. In additional embodiments, the semiconductor device assembly 10 may include only two, only three, or more than four semiconductor devices. In some embodiments, the semiconductor device assembly 10 may also comprise a substrate 26, such as a printed circuit board (PCB). By way of example and not limitation, the substrate 26 may be or include an interposer substrate, a motherboard or daughterboard of a computer system, or other carrier substrate.

Each of the semiconductor devices 12A-12D may include a respective first major surface 18A-18D and a respective opposing second major surface 20A-20D. The semiconductor devices 12A-12D may further include conductive elements 16A- 16D, respectively, on or in their corresponding first major surface 18A-18D. However, additional conductive elements may be disposed on or in one or more of the second major surfaces 20A-20D. By way of example and not limitation, the conductive elements 16A-16D may comprise bond pads, either at original or redistributed locations over the active surface. The conductive elements 16A-16D may communicate electrically with components (e.g., transistors, capacitors, etc.) of integrated circuits (not shown) contained within each of the respective semiconductor devices 12A-12D.

The semiconductor devices 12A-12D may be configured in a stacked configuration, one stacked over the other, as depicted in FIG. 1. For example, the first semiconductor device 12A may be situated over a substrate 26 with its first major surface 18A adjacent the substrate 26. The second semiconductor device 12B may be situated over the first semiconductor device 12A, the third semiconductor device 12C over the second semiconductor device 12B, and the fourth semiconductor device 12D over the third semiconductor device 12C. As shown in FIG. 1, in one particular non-limiting embodiment, set forth merely as an example, the first major surface 18B of the second semiconductor device 12B may be disposed adjacent the second major surface 20A of the first semiconductor device 12A, the first major surface 18C of the third semiconductor device 12C may be disposed adjacent the first major surface 18B of the second semiconductor device 12B, and the first major surface 18D of the fourth semiconductor device 12D may be disposed adjacent the second major surface 20C of the third semiconductor device 12C.

The semiconductor device assembly 10 may further include a plurality of self-supporting conductive leads. As used herein, the term “self-supporting conductive leads” is used in a non-limiting sense and includes elongated conductive paths, comprising a metal or metal alloy, that are supported by the metal or metal alloy from which they are formed and are not externally supported or carried by a substrate as are the conductive traces and vias of printed circuit boards (PCB), flexible printed wiring (FPW), or tape automated bonding (TAB) and the like, which are disposed on or within a dielectric substrate that provides support and electrical insulation. For example, the semiconductor device assembly 10 may include a first plurality of self-supporting conductive leads 14A, a second plurality of self-supporting conductive leads 14B, and a third plurality of self-supporting conductive leads 14C. Each self-supporting conductive lead 14A-14C has a first end 22A-22C, respectively, and a second end 24A-24C, respectively. In some embodiments, each of the second plurality of self-supporting conductive leads 14B may be longer than each of the first plurality of self-supporting conductive leads 14A, and each of the third plurality of self-supporting conductive leads 14C may be longer than each of the second plurality of self-supporting conductive leads 14B, as shown in FIG. 1.

The self-supporting conductive leads 14A-14C may be arranged in a plurality of lead stacks 15, each lead stack 15 comprising one self-supporting conductive lead 14A, one self-supporting conductive lead 14B, and one self-supporting conductive lead 14C. In the embodiment shown in FIG. 1, the semiconductor device assembly 10 includes a plurality of lead stacks 15 disposed along each of two sides of the semiconductor device assembly 10. In additional embodiments, lead stacks 15 may be disposed along only one side of the semiconductor device assembly 10, or along more than two sides of the semiconductor device assembly 10.

As shown in FIG. 1, each self-supporting conductive lead 14A may wrap around the side of the first semiconductor device 12A, such that the first end 22A thereof extends generally over a portion of the first major surface 18A of the first semiconductor device 12A, and the second end 24A extends generally over the second major surface 20A of the first semiconductor device 12A. Each second self-supporting conductive lead 14B may wrap around the sides of both the first and second semiconductor devices 12A and 12B, such that the first end 22B thereof extends generally over the first end 22A of a first self-supporting conductive lead 14A, and the second end 24B thereof extends generally over the second major surface 20B of the second semiconductor device 12B. Similarly, each third self-supporting conductive lead 14C may wrap around the sides of each of the first, second, and third semiconductor devices 12A-12C, such that the first end 22C thereof extends generally over the first end 22B of a second self-supporting conductive lead 14B, and the second end 24C thereof extends generally over the second major surface 20C of the third semiconductor device 12C.

In this configuration, the first ends 22A-22C of the self-supporting conductive leads 14A-14C in each lead stack 15 may be situated one over another, such that the first end 22A of the first self-supporting conductive lead 14A is disposed between the first major surface 18A of the first semiconductor device 12A and the first end 22B of the second self-supporting conductive lead 14B, and the first end 22B of the second self-supporting conductive lead 14B is disposed between the first end 22A of the first self-supporting conductive lead 14A and the first end 22C of the third self-supporting conductive lead 14C. Electrical communication may be established between the self-supporting conductive leads 14A-14C of each lead stack 15. For example, electrical communication may be established between the first ends 22A-22C of the self-supporting conductive leads 14A-14C of each lead stack 15. In some embodiments, the first ends 22A-22C of the self-supporting conductive leads 14A-14C in each lead stack 15 may be structurally and electrically coupled together by, for example, using a conductive adhesive, a soldering process, a brazing process, or a welding process (e.g., a spot welding process).

As shown in FIG. 1, each conductive element 16A of the first semiconductor device 12A may be structurally and electrically coupled to a first end 22A of a first self-supporting conductive lead 14A using conductive material 28. Each conductive element 16B of the second semiconductor device 12B may be structurally and electrically coupled to a second end 24A of a first self-supporting conductive lead 14A using conductive material 28. Similarly, each conductive element 16C of the third semiconductor device 12C may be structurally and electrically coupled to a second end 24B of a second self-supporting conductive lead 14B using conductive material 28, and each conductive element 16D of the third semiconductor device 12D may be structurally and electrically coupled to a second end 24C of a third self-supporting conductive lead 14C using conductive material 28. By way of example and not limitation, the conductive material 28 may include solder material (e.g., solder balls, solder bumps; etc.), conductive or conductor-filled epoxy, anisotropically conductive film, or any other suitable conductive material that may be used to structurally and electrically couple together the respective conductive structures (such as, for example, bond pads and conductive leads).

Additionally, each lead stack 15 may be structurally and electrically coupled to conductive terminals and/or traces (not shown) of the substrate 26 using, for example, conductive material 28. In this configuration, electrical communication may be established between the components of the integrated circuits (not shown) contained within each semiconductor device 12A-12D and conductive terminals and/or traces of the substrate 26 through the self-supporting conductive leads 14A-14C.

As will be apparent to those of ordinary skill in the art, it is not necessary that all lead stacks 15 of the semiconductor device assembly 10 communicate electrically with each of the semiconductor devices 12A-12D. For example, some of the lead stacks may be configured as “chip-select” lead stacks and may communicate with only one of the semiconductor devices 12A-12D. In such chip-select lead stacks, non-conductive material (not shown) may be used in place of the conductive material 28 as necessary to electrically insulate one or more of the semiconductor devices 12A-12D from the self-supporting conductive leads 14A-14C of such chip-select lead stacks.

FIG. 2 illustrates another embodiment of the present invention in the form of semiconductor device assembly 60. The semiconductor device assembly 60 is generally similar to the semiconductor device assembly 10 shown in FIG. 1, and may include a plurality of semiconductor devices 12A-12D, which may be coupled to a substrate 26. The semiconductor device assembly 60 includes a plurality of self-supporting conductive leads, which may include the conductive leads 14A-14C, and an additional fourth plurality of self-supporting conductive leads 14D.

As illustrated in this example, the semiconductor devices 12A-12D of the semiconductor device assembly 60 may be situated with their respective first major surfaces 18A-18D facing upwards, away from the substrate 26. Each self-supporting conductive lead 14D of the additional fourth plurality of self-supporting conductive leads 14D, may extend over the sides of semiconductor devices 12A-12D. The second end 24D of each self-supporting conductive lead 14D may extend generally over the first major surface 18D of the fourth semiconductor device 12D, and the first end 22D of each self-supporting conductive lead 14D may extend generally over the first end 22C of a third self-supporting conductive lead 14C. Additionally, the conductive elements 16A-16D of the semiconductor devices 12A-12D may be structurally and electrically coupled to the corresponding second ends 24A-24D of the self-supporting conductive leads 14A-14D using conductive material 28, in a manner substantially similar to that previously described in relation to the semiconductor device assembly 10 shown in FIG. 1.

FIG. 3 illustrates yet another embodiment of the present invention in the form of semiconductor device assembly 70. The semiconductor device assembly 70 is generally similar to the semiconductor device assembly 10 shown in FIG. 1, and may include a plurality of semiconductor devices 12A-12D, which may be coupled to a substrate 26. The semiconductor device assembly 70 includes a plurality of self-supporting conductive leads. For example, the semiconductor device assembly 70 may include a first plurality of self-supporting conductive leads 14E and a second plurality of self-supporting conductive leads 14F, each having a respective first end 22E and 22F and a respective second end 24E and 24F.

As illustrated in FIG. 3, the first major surfaces 18A and 18C of the. semiconductor devices 12A and 12C may face downwards, towards the substrate 26, and the first major surfaces 18B and 18D of the semiconductor devices 12B and 12D may face upwards, away from the substrate 26.

With continued reference to FIG. 3, the first ends 22E of the first plurality of self-supporting conductive leads 14E may be disposed between the first major surface 18A of the first semiconductor device 12A and the first ends 22F of the second plurality of self-supporting conductive leads 14F. In this configuration, a first side of each of the first ends 22E of the self-supporting conductive leads 14E may be structurally and electrically coupled to the conductive elements 16A of the first semiconductor device 12A using conductive material 28, and a second side of each of the first ends 22E of the self-supporting conductive leads 14E may be structurally and electrically coupled to a first side of the first end 22F of a second self-supporting conductive lead 14F. The first ends 22F of the second plurality of self-supporting conductive leads 14F may be disposed between a substrate 26 and the first ends 22E of the first plurality of self-supporting conductive leads 14E. A second side of each of the first ends 22F of the second self-supporting conductive leads 14F may be structurally and electrically coupled to the substrate 26 using conductive material 28.

The second ends 24E of the first self-supporting conductive leads 14E, may be disposed between the first major surface 18B of the second semiconductor device 12B and the first major surface 18C of the third semiconductor device 12C. The second end 24E of each of the first conductive leads 14E may be structurally and electrically coupled to both a conductive element 16B of the second semiconductor device 12B and a conductive element 16C of the third semiconductor device 12C using conductive material 28, as shown in FIG. 3. The second end 24F of each of the second self-supporting conductive leads 14F may extend over the first major surface 18D of the fourth semiconductor device 12D and may be structurally and electrically coupled to a conductive elements 16D of the fourth semiconductor device 12D using conductive material 28.

FIG. 4 illustrates another embodiment of the present invention in the form of semiconductor device assembly 80. The semiconductor device assembly 80 is generally similar to the semiconductor device assembly 10 shown in FIG. 1, and may include a plurality of semiconductor devices 12A-12D, which may be coupled to a substrate 26. The semiconductor device assembly 80 may include a plurality of self-supporting conductive leads. For example, the semiconductor device assembly 80 may include a first plurality of self-supporting conductive leads 14G and a second plurality of self-supporting conductive leads 14H, each having a respective first end 22G and 22H and a respective second end 24G and 24H.

As illustrated in FIG. 4, the first major surfaces 18A and 18C of the semiconductor devices 12A and 12C may face upwards, away from the substrate 26, and the first major surfaces 18B and 18D of the semiconductor devices 12B and 12D may face downwards, towards the substrate 26.

The first ends 22G and 22H of the self-supporting conductive leads 14G and 14H may be configured substantially identical to the first ends 22E and 22F of the self-supporting conductive leads 14E and 14F shown in FIG. 3, with the exception that the first end 22G of the self-supporting conductive lead 14G is not structurally and electrically coupled directly to a conductive element 16A of the first semiconductor device 12A, as is the first end 22E of the self-supporting conductive lead 14E.

The second end 24G of each first self-supporting conductive lead 14G, may be disposed between the first major surface 18A of the first semiconductor device 12A and the first major surface 18B of the second semiconductor device 12B. Furthermore, a first side of the second end 24G of each first self-supporting conductive lead 14G may be structurally and electrically coupled directly to a conductive element 16A of the first semiconductor device 12A using conductive material 28, and a second side of the second end 24G of each first self-supporting conductive lead 14G may be structurally and electrically coupled directly to a conductive element 16B of the second semiconductor device 12B using conductive material 28. The second end 24H of each second self-supporting conductive leads 14H may be disposed between the first major surface 18C of the third semiconductor device 12C and the first major surface 18D of the fourth semiconductor device 12D. Furthermore, a first side of the second end 24H of each second self-supporting conductive lead 14H may be structurally and electrically coupled directly to a conductive element 16C of the third semiconductor device 12C using conductive material 28, and a second side of the second end 24H of each second self-supporting conductive lead 14H may be structurally and electrically coupled directly to a conductive element 16D of the fourth semiconductor device 12D using conductive material 28.

As previously mentioned, it is not necessary that semiconductor device assemblies that embody teachings of the present invention include four semiconductor devices. FIG. 5 illustrates another embodiment of the present invention in the form of semiconductor device assembly 100 that includes only two semiconductor devices. For example, the semiconductor device assembly 100 may include a first substantially bare die 112A and a second substantially bare die 112B, which may be structurally and electrically coupled to a substrate 26. The semiconductor device assembly 100 further includes a plurality of self-supporting conductive leads 114, each having a first end 122, and a second end 124.

The semiconductor dice 112A and 112B may have bond pads 116A and 116B on or in their respective first major surfaces 118A and 118B. The bond pads 116A of the first semiconductor die 112A may be structurally and electrically coupled to the first ends 122 of the self-supporting conductive leads 114 using solder balls 128, and the bond pads 116B of the second semiconductor die 112B may be structurally and electrically coupled to the second ends 124 using solder balls 128. In addition, the first ends 122 also may be structurally and electrically coupled to the substrate 26 using solder balls 128. In additional embodiments, other solder structures (e.g., solder bumps, solder balls, etc.), conductive or conductor-filled epoxy, anisotropically conductive film, or any other conductive material that may be used to structurally and electrically couple together conductive structures may be used in addition to, or as an alternative to, the solder balls 128.

In addition to substantially bare semiconductor dice, semiconductor device assemblies that embody teachings of the present invention may include other types of semiconductor devices, such as, for example, semiconductor device packages. FIG. 6 illustrates another semiconductor device assembly 150 that embodies teachings of the present invention in a somewhat different structural form. The semiconductor device assembly 150 is generally similar to the semiconductor device assembly 100 shown in FIG. 5. In contrast to substantially bare semiconductor dice of the semiconductor device assembly 100, however, the semiconductor device assembly 150 may include a first semiconductor device package 152A and a second semiconductor device package 152B. By way of example and not limitation, each of the first and second semiconductor device packages 152A and 152B may include a package substrate 154, a first semiconductor die 156, and a second semiconductor die 158. In additional embodiments, each of the semiconductor device packages 152A and 152B may include only one semiconductor die. In yet other embodiments, each of the semiconductor device packages 152A and 152B may include more than two semiconductor dice.

As shown in FIG. 6, the first and second semiconductor device packages 152A and 152B may be substantially identical in some embodiments of the present invention. In other embodiments, the second semiconductor device package 152B may differ from the first semiconductor device package 152A in at least one aspect. As shown in FIG. 6, in each of the first and second semiconductor device packages 152A and 152B, the first semiconductor die 156 may be situated generally over the package substrate 154, and the second semiconductor die 158 may be situated generally over the first semiconductor die 156. A dielectric spacer 160A may be disposed between the first semiconductor die 156 and the second semiconductor die 158. Similarly, another dielectric spacer 160B may be disposed between the first semiconductor die 156 and the package substrate 154. The dielectric spacers 160A and 160B may be used to electrically isolate each of the package substrate 154, the first semiconductor die 156, and the second semiconductor die 158 from one another. By way of example and not limitation, the dielectric spacers 160A and 160B may be or include a layer of disc comprising an electrically insulating material, such as, for example a polymer material (e.g., epoxy), a ceramic material (e.g., silica), or silicon.

Each of the first semiconductor die 156 and the second semiconductor die 158 may communicate electrically with the respective package substrate 154. By way of example and not limitation, bond wires 162 may be used to provide electrical communication between bond pads 164 on or in a surface of each semiconductor die 156 and 158 and corresponding conductive lands 166 on or in a surface of the package substrate 154. Conductive traces and/or vias (not shown) on and/or in the package substrates 154 may provide electrical communication between the conductive lands 166 and the conductive terminals 168.

Optionally, each of the semiconductor device packages 152A and 152B may include a dielectric encapsulant material 170, shown for purposes of illustration only as a transfer-molded encapsulant. By way of example and not limitation, an encapsulant material 170 may be disposed around the bond wires 162 and over at least a portion of the package substrate 154 and the semiconductor dice 156, 158. The semiconductor device packages 152A and 152B shown in FIG. 6 and described herein are disclosed merely as an example of one type of a semiconductor device package that may be used in semiconductor device assemblies that embody teachings of the present invention.

As will be apparent to those of ordinary skill in the art, the semiconductor device packages 152A and 152B shown in FIG. 6 have a “board-on-chip” (BOC) configuration. In additional embodiments, the semiconductor device packages 152A and 152B may have a “chip-on-board” (COB) configuration. Furthermore, each of the semiconductor device packages 152A and 152B may include semiconductor dice that are flip-chip bonded to the underlying semiconductor die or package substrate 154, and may not include bond wires 162. Various other types of semiconductor device packages are known in the art and may be used to provide additional semiconductor device assemblies that embody teachings of the present invention.

Each of the previously described semiconductor device assemblies include conductive pathways provided by self-supporting conductive leads extending between the semiconductor devices and the respective substrate 26. The present invention is not so limited, however, and such conductive pathways may be provided by conductive traces carried on or in a carrier substrate, such as, for example, those conventionally used in so-called “flex-circuit” and tape-automated bonding (TAB) applications.

The semiconductor device assembly 350 shown in FIG. 7 illustrates an example of a semiconductor device assembly 350 that embodies teachings of the present invention and includes conductive traces 352A-352D carried on or in a carrier substrate 358A-358D. The semiconductor device assembly 350 is generally similar to the previously described semiconductor device assembly 60 shown in FIG. 2, and may include a plurality of semiconductor devices 12A-12D. The semiconductor device assembly 350 may further include a first plurality of conductive traces 352A carried by at least one first layer carrier substrate 358A, a second plurality of conductive traces 352B carried by at least one second layer carrier substrate 358B, a third plurality of conductive traces 352C carried by at least one third layer carrier substrate 358C, and a fourth plurality of conductive traces 352D carried by at least one fourth layer carrier substrate 358D. In the embodiment shown in FIG. 7, the semiconductor device assembly 350 includes two first layer carrier substrates 358A, two second layer carrier substrates 358B, two third layer carrier substrates 358C, and two fourth layer carrier substrates 358D. The carrier substrates 358A-358D are configured to wrap generally around two sides of each of the semiconductor devices 12A-12D. The carrier substrates 358A-358D may, respectively, provide structural support for conductive traces 352A-352D.

In additional embodiments, the semiconductor device assembly 350 may include only one of each of the first through fourth layers of carrier substrates 358A-358D, or more than two of each of the first through fourth layers of carrier substrates 358A-358D. Furthermore, the carrier substrates 358A-358D may be configured to wrap generally around only one side of each of the semiconductor devices 12A-12D, or to wrap generally around more than two sides of each of the semiconductor devices 12A-12D.

By way of example and not limitation, the conductive traces 352A-352D each may include a conductive material such as, for example, copper or copper-based alloy (including alloys based on copper and beryllium), aluminum or aluminum-based alloy, nickel-chromium-iron superalloy (such as that sold under the trademark INCONEL®), or a conductive polymer material.

By way of example and not limitation, each of the carrier substrates 358A-358D may include a flexible dielectric material such as, for example, a polyimide or polyimide-based material, a polyester or polyester-based material, an aramid or aramid-based material, a reinforced composite material, or a fluorocarbon-based material (e.g., polytetrafluoroethylene).

As shown in FIG. 7, each conductive trace 352A-352D may have a respective first end 354A-354D and a respective second end 356A-356D. The conductive traces 352A and 352B may be configured to provide stacks of conductive traces, similar to the lead stacks 15 previously described in relation to FIG. 1. Electrical communication may be provided between the conductive traces 356A amd 356D in each stack at the first ends 354A-354D thereof. For example, in some embodiments, the conductive traces 352A-352D on each carrier substrate 358A-358D may have a substantially similar configuration, differing only in the length of the respective conductive traces 352A-352D. In this configuration, the first ends 354A-354D of the conductive traces 352A-352D may be aligned with one another by aligning the carrier substrates 358A-358D. By way of example and not limitation, through holes may be formed through the carrier substrates 358A-358D and each of the conductive traces 352A-352D in each trace stack. The through holes then may be aligned and filled with a conductive material, such as, for example, a conductive metal or metal alloy, to form conductive vias 360 that provide electrical communication between the conductive traces 352A-352D in each stack.

With continued reference to FIG. 7, the second end 356A of each of the first plurality of conductive traces 352A may be structurally and electrically coupled to a conductive element 16A of the first semiconductor device 12A using conductive material 28. The second end 356B of each of the second plurality of conductive traces 352B may be structurally and electrically coupled to a conductive element 16B of the second semiconductor device 12B using conductive material 28. Similarly, the second end 356C of each of the third plurality of conductive traces 352C may be structurally and electrically coupled to a conductive element 16C of the third semiconductor device 12C using conductive material 28. Finally, the second end 356D of each of the fourth plurality of conductive traces 352D may be structurally and electrically coupled to a conductive element 16D of the fourth semiconductor device 12D using conductive material 28.

In addition, the first ends 354A-354D may be structurally and electrically coupled to the substrate by way of vias 360 through the carrier substrates 358A-358D (e.g., flexible dielectric films) using conductive material 28.

Any of the previously described semiconductor device assemblies (e.g., the semiconductor device assembly 10 shown in FIG. 1, the semiconductor device assembly 60 shown in FIG. 2, the semiconductor device assembly 70 shown in FIG. 3, the semiconductor device assembly 80 shown in FIG. 4, the semiconductor device assembly 100 shown in FIG. 5, and the semiconductor device assembly 150 shown in FIG. 6) may include conductive pathways provided by conductive traces carried on or in a carrier substrate, in addition to, or as an alternative to, the previously described self-supporting conductive leads.

Additional embodiments of the present invention include methods of manufacturing semiconductor device assemblies. One example of a method that embodies teachings of the present invention and that may be used to manufacture a semiconductor device assembly, such as the semiconductor device assembly 10 shown in FIG. 1, is described below with reference to FIGS. 8-17.

Referring to FIG. 8, a first lead frame 200A may be provided that includes a first plurality of self-supporting conductive leads 14A. The self-supporting conductive leads 14A may be attached to a carrier strip 206A as shown in FIG. 8 (providing an integral tie bar extending laterally between self-supporting conductive leads 14A, and/or to an outer frame member 201A of the first lead frame 200A). The first lead frame 200A may further include additional tie bars (not shown), which may extend laterally between adjacent self-supporting conductive leads 14A to provide additional support to the first plurality of self-supporting conductive leads 14A during forming, as known in the art. The lead frame 200A may be formed by, for example, cutting, stamping, punching, or etching a sheet of metal or metal alloy, or by any other method known in the art for forming conventional lead frames.

The area of FIG. 8 enclosed within the dashed line 202 is illustrated in an enlarged perspective view in FIG. 9 to facilitate description thereof. As shown in FIG. 9, the first ends 22A of the self-supporting conductive leads 14A may be cantilevered from the carrier strip 206A (or other element of the lead frame 200A) and positioned in a generally central region of the lead frame 200A.

Referring to FIG. 10, a first semiconductor device 12A may be positioned over the self-supporting conductive leads 14A such that conductive elements 16A (FIG. 1), disposed on a surface thereof, are aligned with and adjacent the first ends 22A of the conductive elements 16A, and the first ends 22A of the conductive elements 16A may be structurally and electrically coupled to the conductive elements 16A using a conductive material 28, as previously described. Referring to FIG. 11, the carrier strip 206A may be severed from the self-supporting conductive leads 14A. After severing the carrier strip 206A from the self-supporting conductive leads 14A, the self-supporting conductive leads 14A may extend laterally from the semiconductor device 12A, and the second ends 24A of the self-supporting conductive leads 14A may be disposed laterally outward from the semiconductor device 12A and coplanar with the first ends 22A of the self-supporting conductive leads 14A.

As shown in FIG. 12, the self-supporting conductive leads 14A may be bent or wrapped around side 30A of the semiconductor device 12A, such that the second ends 24A extend generally over the second major surface 20A of the first semiconductor device 12A. By way of example and not limitation, each of the self-supporting conductive leads 14A may be bent or wrapped around the side 30A of the semiconductor device 12A using commercially available trim-and-form equipment for bending or forming self-supporting conductive leads 14A.

As the self-supporting conductive leads 14A are bent or wrapped around the side 30A of the semiconductor device 12A, the second ends 24A of the self-supporting conductive leads 14A may be positioned at relative positions substantially corresponding to a pattern of conductive elements on a second semiconductor device 12B to be attached thereto, as described in further detail below.

In some embodiments, the self-supporting conductive leads 14A may be caused to substantially conform to the exterior surfaces of the semiconductor device 12A. In additional embodiments, the self-supporting conductive leads 14A may not substantially conform to the exterior surfaces of the semiconductor device 12A.

Referring to FIG. 13, a second lead frame 200B may be provided that is generally similar to the first lead frame 200A (FIGS. 8-10), with the exception that the self-supporting conductive leads 14B of the second lead frame 200B may be longer than the self-supporting conductive leads 14A of the first lead frame 200A. As shown in FIG. 13, the first ends 22B of the second self-supporting conductive leads 14B may be aligned with and positioned over the first ends 22A of the self-supporting conductive leads 14A, and the first ends 22B of the self-supporting conductive leads 14B may be structurally and electrically coupled to the first ends 22A of the self-supporting conductive leads 14A, as previously described.

As shown in FIG. 14, a second semiconductor device 12B may be positioned over the second ends 24A (FIG. 13) of the first self-supporting conductive leads 14A such that conductive elements 16B (FIG. 1) disposed on a surface of the second semiconductor device 12B are aligned with and adjacent the second ends 24A of the self-supporting conductive leads 14A. The second ends 24A of the self-supporting conductive leads 14A may be structurally and electrically coupled to the conductive elements 16B of the second semiconductor device 12B using a conductive material 28, as previously described. In additional embodiments, the conductive elements 16B of the second semiconductor device 12B may be attached to the second ends 24A of the self-supporting conductive leads 14A prior to attaching the first ends 22B of the self-supporting conductive leads 14B to the first ends 22A of the self-supporting conductive leads 14A.

Referring to FIG. 15, the carrier strip 206B may be severed from the self-supporting conductive leads 14B in a manner substantially identical to that previously described in relation to the carrier strip 206A with reference to FIG. 11. After severing the carrier strip 206B from the self-supporting conductive leads 14B, the self-supporting conductive leads 14B may extend laterally from the assembly, and the second ends 24B of the self-supporting conductive leads 14B may be disposed laterally outward from the assembly and coplanar with the first ends 22B of the self-supporting conductive leads 14B.

As shown in FIG. 16, the self-supporting conductive leads 14B may be bent or wrapped around the side 30A of the first semiconductor device 12A and the side 30B of the second semiconductor device 12B, such that the second ends 24B extend generally over the second major surface 20B of the second semiconductor device 12B. As the self-supporting conductive leads 14B are bent or wrapped around the side 30A of the first semiconductor device 12A and the side 30B of the second semiconductor device 12B, the second ends 24B of the self-supporting conductive leads 14B may be positioned at relative positions substantially corresponding to a pattern of conductive elements on a third semiconductor device 12C (FIG. 1) to be attached thereto.

Referring to FIG. 17, a third lead frame 200C may be provided that is generally similar to the first lead frame 200A and the second lead frame 200B, with the exception that the self-supporting conductive leads 14C of the third lead frame 200C may be longer than the self-supporting conductive leads 14B of the second lead frame 200B. As shown in FIG. 17, the first ends 22C of the third self-supporting conductive leads 14C may be aligned with and positioned over the first ends 22B of the self-supporting conductive leads 14B, and the first ends 22C of the self-supporting conductive leads 14C may be structurally and electrically coupled to the first ends 22B of the self-supporting conductive leads 14B, as previously described.

The above-described processes may be repeated until a selected number of semiconductor devices have been structurally and electrically coupled to one another, to provide a semiconductor device assembly that embodies teachings of the present invention. For example, the above-described processes may be repeated to structurally and electrically couple together four semiconductor devices 12A-12D, thereby providing the semiconductor device assembly 10 shown in FIG. 1. Furthermore, the process described above with reference to FIGS. 8-17 may be used to provide any of the previously described semiconductor device assemblies, simply by flipping the semiconductor devices over as necessary and attaching the conductive elements of each semiconductor devices to the respective ends of the conductive leads that are disposed adjacent thereto.

In additional methods that embody teachings of the present invention, the leads of each lead stack 15 (FIG. 1) may be structurally and electrically coupled to one another prior to attaching any semiconductor device to the conductive leads. For example, the previously described first lead frame 200A, second lead frame 200B, and third lead frame 200C may be provided and stacked one on top of another, such that the first ends 22A, 22B, 22C of the self-supporting conductive leads 14A, 14B, 14C are disposed adjacent one another, as shown in FIG. 18. The first ends 22A, 22B, 22C of the self-supporting conductive leads 14A, 14B, 14C then may be structurally and electrically coupled together by, for example, using a conductive adhesive, a welding process (e.g., a spot welding process), a soldering process, or a brazing process.

Referring to FIG. 19, a first semiconductor device 12A may be positioned over the self-supporting conductive leads 14A such that conductive elements 16A, disposed on or in a surface thereof, are aligned with and adjacent the first ends 22A of the conductive leads 16A, and the first ends 22A of the self-supporting conductive leads 14A may be structurally and electrically coupled to the conductive elements 16A using a conductive material 28, as previously described. The carrier strip 206A (FIG. 18) may be severed from the self-supporting conductive leads 14A, and the self-supporting conductive leads 14A may be bent or wrapped around the side 30A of the first semiconductor device 12A such that the second ends 24A extend generally over the second major surface 20A of the first semiconductor device 12A, as shown in FIG. 20.

Referring to FIG. 21, a second semiconductor device 12B may be positioned over the second ends 24A (of the first self-supporting conductive leads 14A such that conductive elements 16B disposed on a surface of the second semiconductor device 12B are aligned with and adjacent the second ends 24A of the self-supporting conductive leads 14A. The second ends 24A of the self-supporting conductive leads 14A may be structurally and electrically coupled to the conductive elements 16B of the second semiconductor device 12B using a conductive material 28, as previously described. The carrier strip 206B (FIG. 18) may be severed from the self-supporting conductive leads 14B, and the self-supporting conductive leads 14B may be bent or wrapped around the side 30A of the first semiconductor device 12A and the side 30B of the second semiconductor device 12B such that the second ends 24B extend generally over the second major surface 20B of the second semiconductor device 12B, as shown in FIG. 21.

The above-described processes may be repeated until a selected number of semiconductor devices have been structurally and electrically coupled to one another, thereby providing a semiconductor device assembly that embodies teachings of the present invention. For example, the above described processes may be repeated to structurally and electrically couple together four semiconductor devices 12A-12D, thereby providing the semiconductor device assembly 10 shown in FIG. 1. Furthermore, the process described above with reference to FIGS. 18-21 may be used to provide any of the previously described semiconductor device assemblies, simply by flipping the semiconductor devices over as necessary and attaching the conductive elements of each semiconductor devices to the respective ends of the conductive leads that are disposed adjacent thereto.

In yet additional methods that embody teachings of the present invention, the semiconductor devices may be structurally coupled to one another and to the conductive leads prior to bending or wrapping the conductive leads around any of the semiconductor devices. For example, referring to FIG. 22, the conductive elements 16D of the fourth semiconductor device 12D may be structurally and electrically coupled to the first ends 22D of a fourth plurality of self-supporting conductive leads 14D using a conductive material 28. The first ends 22C of the third plurality of self-supporting conductive leads 14C may be structurally coupled to the second major surface 20D of a fourth semiconductor device 12D using, for example, a non-conducting adhesive material (epoxy, double-sided adhesive film, etc.). The conductive elements 16C of the third semiconductor device 12C may be structurally and electrically coupled to the first ends 22C of the third plurality of self-supporting conductive leads 14C using a conductive material 28. The first ends 22B of the second plurality of self-supporting conductive leads 14B may be structurally coupled to the second major surface 20C of the third semiconductor device 12C using, for example, a non-conducting adhesive material. The conductive elements 16B of the second semiconductor device 12B may be structurally and electrically coupled to the first ends 22C of the third plurality of self-supporting conductive leads 14C using a conductive material 28. The first ends 22A of the first plurality of self-supporting conductive leads 14A may be structurally coupled to the second major surface 20B of the second semiconductor device 12B using, for example, a non-conducting adhesive material. The conductive elements 16A of the first semiconductor device 12A may be structurally and electrically coupled to the first ends 22A of the first plurality of self-supporting conductive leads 14A using a conductive material 28.

After forming the structure shown in FIG. 22, the first self-supporting conductive leads 14A may be bent or wrapped around the first semiconductor device 12A as previously described, followed by the second plurality of self-supporting conductive leads 14B, the third plurality of self-supporting conductive leads 14C, and the fourth plurality of self-supporting conductive leads 14D. The second ends 24A, 24B, 24C, 24D of the self-supporting conductive leads 14A, 14B, 14C, 14D thus may be positioned generally over the second major surface 20A of the first semiconductor device 12A and structurally and electrically coupled to one another, as previously described, thereby forming the semiconductor device assembly 60 shown in FIG. 2.

The previously described methods have been described with reference to self-supporting conductive leads. Additional methods that embody teachings of the present invention may be carried out using other configurations of electrical pathways, including, for example, conductive traces carried on or in a carrier substrate, as previously described with reference to FIG. 7. In such methods, some ends of the conductive traces may be electrically coupled to conductive elements of semiconductor devices as necessary, while other ends of the conductive traces may be electrically coupled to one another in a manner substantially identical to that previously described with reference to FIG. 7. Furthermore, the carrier substrate (and conductive traces carried thereby) may be bent or wrapped around the sides of the semiconductor devices in a manner substantially similar to that previously described in relation to the self-supporting conductive leads.

Semiconductor device assemblies that embody teachings of the present invention may be used in electronic systems such as, for example, a desktop computer, a laptop computer, a handheld computer (e.g., a personal data assistant (PDA)), a mobile telephone, an audio player, a digital camera, a video player, and a visual display. Furthermore, such electronic systems may include, for example, computer subsystems such as graphic cards, etc. FIG. 23 is a simplified schematic diagram of a computer system 300 that embodies teachings of the present invention and includes a processor device 302 and a memory device 304. At least one of the processor device 302 and the memory device 304 may be or include a semiconductor device assembly that embodies teachings of the present invention (e.g., the semiconductor device assembly 10 shown in FIG. 1, the semiconductor device assembly 60 shown in FIG. 2, the semiconductor device assembly 70 shown in FIG. 3, the semiconductor device assembly 80 shown in FIG. 4, the semiconductor device assembly 100 shown in FIG. 5, and the semiconductor device assembly 150 shown in FIG. 6).

Additionally, the computer system 300 may include an input device 306 (such as, for example, a key pad, a pointing device, or an electronic sensor) and an output device 308 (such as, for example, a monitor, an audio speaker, a printer, or an electromechanical actuator).

Semiconductor device assemblies that embody teachings of the present invention may provide a robust POP structure with enhanced solder joint reliability, and a lower stacked package profile in comparison to conventional POP structures. Such semiconductor device assemblies may also exhibit improved RLC performance by, for example, providing greater speed with higher signal quality and experiencing or exhibiting reduced parasitic capacitances along the conductive pathways extending between the semiconductor devices of the assemblies because the pathways extend around the sides of the semiconductor devices, instead of through each of the semiconductor devices. Furthermore, the self-supporting conductive leads described herein may behave as a heat sink, drawing heat generated within the semiconductor devices to the outside of the assembly, which may provide enhanced performance and/or longer product life. In addition, each semiconductor device, which may be a semiconductor device package or a bare die, may optionally be burned-in and tested prior to assembly in the stack.

While the present invention has been described in terms of certain illustrated embodiments and variations thereof, it will be understood and appreciated by those of ordinary skill in the art that the invention is not so limited. Rather, additions, deletions and modifications to the illustrated embodiments may be effected without departing from the spirit and scope of the invention as defined by the claims, which follow.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4437235 *23 Aug 198220 Mar 1984Honeywell Information Systems Inc.Integrated circuit package
US4996587 *23 Mar 199026 Feb 1991International Business Machines CorporationIntegrated semiconductor chip package
US5138438 *25 Nov 199111 Aug 1992Akita Electronics Co. Ltd.Lead connections means for stacked tab packaged IC chips
US5216283 *3 May 19901 Jun 1993Motorola, Inc.Semiconductor device having an insertable heat sink and method for mounting the same
US5281852 *10 Dec 199125 Jan 1994Normington Peter J CSemiconductor device including stacked die
US5291061 *6 Apr 19931 Mar 1994Micron Semiconductor, Inc.Multi-chip stacked devices
US5313096 *29 Jul 199217 May 1994Dense-Pac Microsystems, Inc.IC chip package having chip attached to and wire bonded within an overlying substrate
US5323060 *2 Jun 199321 Jun 1994Micron Semiconductor, Inc.Multichip module having a stacked chip arrangement
US534715924 Sep 199113 Sep 1994Tessera, Inc.Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate
US53863411 Nov 199331 Jan 1995Motorola, Inc.Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5394010 *12 Mar 199228 Feb 1995Kabushiki Kaisha ToshibaSemiconductor assembly having laminated semiconductor devices
US5394303 *9 Sep 199328 Feb 1995Kabushiki Kaisha ToshibaSemiconductor device
US5432378 *15 Dec 199311 Jul 1995Cooper Industries, Inc.Subminiature surface mounted circuit protector
US5448511 *1 Jun 19945 Sep 1995Storage Technology CorporationMemory stack with an integrated interconnect and mounting structure
US5455740 *7 Mar 19943 Oct 1995Staktek CorporationBus communication system for stacked high density integrated circuit packages
US5486798 *7 Dec 199423 Jan 1996At&T Ipm Corp.Multiplanar hybrid coupler
US5499160 *30 Jan 199512 Mar 1996Staktek CorporationHigh density integrated circuit module with snap-on rail assemblies
US555291029 Nov 19943 Sep 1996Sharp Kabushiki KaishaLiquid crystal display having zinc sulfide switching elements and method for producing the same
US5552963 *24 Jul 19953 Sep 1996Staktek CorporationBus communication system for stacked high density integrated circuit packages
US5571754 *9 Nov 19955 Nov 1996International Business Machines CorporationMethod of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack
US559803316 Oct 199528 Jan 1997Advanced Micro Devices, Inc.Micro BGA stacking scheme
US564644622 Dec 19958 Jul 1997Fairchild Space And Defense CorporationThree-dimensional flexible assembly of integrated circuits
US5776797 *2 Jul 19977 Jul 1998Fairchild Space And Defense CorporationThree-dimensional flexible assembly of integrated circuits
US5835988 *24 Oct 199610 Nov 1998Mitsubishi Denki Kabushiki KaishaPacked semiconductor device with wrap around external leads
US5854534 *16 Nov 199529 Dec 1998Fujitsu LimitedControlled impedence interposer substrate
US5898220 *14 Aug 199727 Apr 1999Micron Technology, Inc.Multi-chip device and method of fabrication employing leads over and under processes
US5910685 *3 Dec 19978 Jun 1999Akita Electronics, Co., Ltd.Semiconductor memory module having double-sided stacked memory chip layout
US5952717 *19 Dec 199514 Sep 1999Sony CorporationSemiconductor device and method for producing the same
US5960539 *11 Feb 19985 Oct 1999Staktek CorporationMethod of making high density integrated circuit module
US597764026 Jun 19982 Nov 1999International Business Machines CorporationHighly integrated chip-on-chip packaging
US598203027 Feb 19989 Nov 1999Macintrye; Donald MalcomRigid package with low stress mounting of semiconductor die
US6002167 *20 Sep 199614 Dec 1999Hitachi Cable, Ltd.Semiconductor device having lead on chip structure
US60139481 Apr 199811 Jan 2000Micron Technology, Inc.Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6014316 *10 Jun 199811 Jan 2000Irvine Sensors CorporationIC stack utilizing BGA contacts
US60206295 Jun 19981 Feb 2000Micron Technology, Inc.Stacked semiconductor package and method of fabrication
US6028352 *10 Jun 199822 Feb 2000Irvine Sensors CorporationIC stack utilizing secondary leadframes
US602836530 Mar 199822 Feb 2000Micron Technology, Inc.Integrated circuit package and method of fabrication
US6049123 *22 Sep 199711 Apr 2000Staktek CorporationUltra high density integrated circuit packages
US60722334 May 19986 Jun 2000Micron Technology, Inc.Stackable ball grid array package
US6137163 *16 Apr 199824 Oct 2000Hyundai Electronics Industries Co., Ltd.Semiconductor substrate and stackable semiconductor package and fabrication method thereof
US6153929 *21 Aug 199828 Nov 2000Micron Technology, Inc.Low profile multi-IC package connector
US615754121 Dec 19985 Dec 2000Siemens AktiengesellschaftStack arrangement for two semiconductor memory chips and printed board for accepting a plurality of such stack arrangements
US6165817 *17 Sep 199926 Dec 2000Micron Technology, Inc.Method of bonding a flexible polymer tape to a substrate to reduce stresses on the electrical connections
US6190944 *19 May 199920 Feb 2001Hyundai Electronics Industries Co., Ltd.Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package
US6208521 *19 May 199827 Mar 2001Nitto Denko CorporationFilm carrier and laminate type mounting structure using same
US62256884 Feb 19991 May 2001Tessera, Inc.Stacked microelectronic assembly and method therefor
US62586238 Jul 199910 Jul 2001Micron Technology, Inc.Low profile multi-IC chip package connector
US626289513 Jan 200017 Jul 2001John A. ForthunStackable chip package with flex carrier
US6291892 *31 Dec 199818 Sep 2001Oki Electric Industry Co., LtdSemiconductor package that includes a shallow metal basin surrounded by an insulator frame
US6297544 *29 Aug 19972 Oct 2001Hitachi, Ltd.Semiconductor device and method for manufacturing the same
US63006791 Jun 19989 Oct 2001Semiconductor Components Industries, LlcFlexible substrate for packaging a semiconductor component
US63230605 May 199927 Nov 2001Dense-Pac Microsystems, Inc.Stackable flex circuit IC package and method of making same
US6337510 *17 Nov 20008 Jan 2002Walsin Advanced Electronics LtdStackable QFN semiconductor package
US6376769 *14 Mar 200023 Apr 2002Amerasia International Technology, Inc.High-density electronic package, and method for making same
US6380619 *31 Mar 199930 Apr 2002Tdk CorporationChip-type electronic component having external electrodes that are spaced at predetermined distances from side surfaces of a ceramic substrate
US6380624 *10 Oct 200030 Apr 2002Walsin Advanced Electronics Ltd.Stacked integrated circuit structure
US6404662 *23 Mar 199811 Jun 2002Staktek Group, L.P.Rambus stakpak
US6424031 *8 May 200023 Jul 2002Amkor Technology, Inc.Stackable package with heat sink
US6458617 *20 Feb 20011 Oct 2002Vanguard International Semiconductor Corp.Multi-chip semiconductor package structure
US6483718 *23 Aug 200119 Nov 2002Seiko Epson CorporationSemiconductor device and method of manufacture thereof, circuit board, and electronic instrument
US64865443 Sep 199926 Nov 2002Seiko Epson CorporationSemiconductor device and method manufacturing the same, circuit board, and electronic instrument
US6509639 *30 Apr 200221 Jan 2003Charles W. C. LinThree-dimensional stacked semiconductor package
US6528870 *26 Jan 20014 Mar 2003Kabushiki Kaisha ToshibaSemiconductor device having a plurality of stacked wiring boards
US65632237 Dec 200113 May 2003Micron Technology, Inc.Interconnection component for facilitating testing of packaged integrated circuits
US6564454 *28 Dec 200020 May 2003Amkor Technology, Inc.Method of making and stacking a semiconductor package
US657699226 Oct 200110 Jun 2003Staktek Group L.P.Chip scale stacking system and method
US6600222 *17 Jul 200229 Jul 2003Intel CorporationStacked microelectronic packages
US6608371 *11 Jul 200119 Aug 2003Seiko Epson CorporationSemiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US6611052 *16 Nov 200126 Aug 2003Micron Technology, Inc.Wafer level stackable semiconductor package
US6617671 *10 Jun 19999 Sep 2003Micron Technology, Inc.High density stackable and flexible substrate-based semiconductor device modules
US6667544 *30 Jun 200023 Dec 2003Amkor Technology, Inc.Stackable package having clips for fastening package and tool for opening clips
US6683377 *30 May 200027 Jan 2004Amkor Technology, Inc.Multi-stacked memory package
US6717250 *17 Oct 20006 Apr 2004Seiko Epson CorporationStacked semiconductor apparatus and electronic device including stacked semiconductor apparatus
US673085517 Jan 20034 May 2004Renesas Technology Corp.Electronic element
US675625130 Aug 200129 Jun 2004Micron Technology, Inc.Method of manufacturing microelectronic devices, including methods of underfilling microelectronic components through an underfill aperture
US6768191 *12 Aug 200227 Jul 2004Infineon Technologies AgElectronic component with stacked electronic elements
US6773955 *22 Jul 200210 Aug 2004Micron Technology, Inc.Low profile multi-IC chip package connector
US6785144 *24 Aug 200031 Aug 2004Micron Technology, Inc.High density stackable and flexible substrate-based devices and systems and methods of fabricating
US6858922 *15 Jan 200222 Feb 2005International Rectifier CorporationBack-to-back connected power semiconductor device package
US686749629 Sep 200015 Mar 2005Seiko Epson CorporationInterconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US688465321 Mar 200126 Apr 2005Micron Technology, Inc.Folded interposer
US6897553 *4 Aug 200324 May 2005Micron Technology, Inc.Apparatus for forming a stack of packaged memory dice
US69143243 Jun 20035 Jul 2005Staktek Group L.P.Memory expansion and chip scale stacking system and method
US6919626 *16 Jan 200119 Jul 2005Staktek Group L.P.High density integrated circuit module
US69407292 May 20026 Sep 2005Staktek Group L.P.Integrated circuit stacking system and method
US695594525 May 200418 Oct 2005Staktek Group L.P.Memory expansion and chip scale stacking system and method
US695628431 Mar 200418 Oct 2005Staktek Group L.P.Integrated circuit stacking system and method
US697503517 May 200213 Dec 2005Micron Technology, Inc.Method and apparatus for dielectric filling of flip chip on interposer assembly
US6984885 *11 Aug 200010 Jan 2006Renesas Technology Corp.Semiconductor device having densely stacked semiconductor chips
US6992376 *17 Jul 200331 Jan 2006Intel CorporationElectronic package having a folded package substrate
US702670814 Jul 200311 Apr 2006Staktek Group L.P.Low profile chip scale stacking system and method
US7030488 *30 Oct 200118 Apr 2006Intel CorporationPackaged combination memory for electronic devices
US7033861 *18 May 200525 Apr 2006Staktek Group L.P.Stacked module systems and method
US7033911 *31 Mar 200425 Apr 2006Intel CorporationAdhesive of folded package
US70534789 Aug 200430 May 2006Staktek Group L.P.Pitch change and chip scale stacking system
US7087442 *24 Sep 20018 Aug 2006Pac Tech-Packaging Technologies GmbhProcess for the formation of a spatial chip arrangement and spatial chip arrangement
US7087459 *30 Dec 20038 Aug 2006Dongbu Electronics Co., Ltd.Method for packaging a multi-chip module of a semiconductor device
US7091061 *29 Mar 200515 Aug 2006Micron Technology, Inc.Method of forming a stack of packaged memory dice
US712620921 Dec 200424 Oct 2006Matsushita Electric Industrial Co., Ltd.Lead frame, resin-encapsulated semiconductor device, and method of producing the same
US7126829 *9 Feb 200424 Oct 2006Pericom Semiconductor Corp.Adapter board for stacking Ball-Grid-Array (BGA) chips
US7132754 *16 Dec 20057 Nov 2006Alfred E. Mann Foundation For Scientific ResearchFlip chip stack
US7180168 *7 Sep 200520 Feb 2007Seiko Epson CorporationStacked semiconductor chips
US7227249 *22 Dec 20045 Jun 2007Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package with chips on opposite sides of lead
US7247933 *3 Feb 200424 Jul 2007Advanced Interconnect Technologies LimitedThin multiple semiconductor die package
US7285442 *22 Feb 200523 Oct 2007Micron Technology, Inc.Stackable ceramic FBGA for high thermal applications
US7291906 *29 Dec 20036 Nov 2007Ki Bon ChaStack package and fabricating method thereof
US7309923 *16 Jun 200318 Dec 2007Sandisk CorporationIntegrated circuit package having stacked integrated circuits and method therefor
US7358444 *13 Oct 200415 Apr 2008Intel CorporationFolded substrate with interposer package for integrated circuit devices
US7410832 *26 Mar 200712 Aug 2008Samsung Electronics Co., Ltd.Semiconductor chip package having an adhesive tape attached on bonding wires
US7417308 *1 Dec 200526 Aug 2008Hynix Semiconductor Inc.Stack type package module and method for manufacturing the same
US7425758 *28 Aug 200616 Sep 2008Micron Technology, Inc.Metal core foldover package structures
US7436055 *25 Jul 200614 Oct 2008Advanced Semiconductor Engineering, Inc.Packaging method of a plurality of chips stacked on each other and package structure thereof
US7468553 *6 Mar 200723 Dec 2008Entorian Technologies, LpStackable micropackages and stacked modules
US7476962 *6 Mar 200613 Jan 2009Samsung Electronics Co., Ltd.Stack semiconductor package formed by multiple molding and method of manufacturing the same
US7479408 *28 Sep 200620 Jan 2009Samsung Electronics Co., Ltd.Stack package made of chip scale packages
US7495334 *4 Aug 200524 Feb 2009Entorian Technologies, LpStacking system and method
US7503155 *26 Aug 200217 Mar 2009Meyers John GMethod for packaging a tape substrate
US20010040793 *31 Jan 200115 Nov 2001Tetsuya InabaElectronic device and method of producing the same
US20020043658 *28 Aug 200118 Apr 2002Mess Leonard E.Apparatus and methods of packaging and testing die
US20020164838 *5 Jun 20017 Nov 2002Moon Ow CheeFlexible ball grid array chip scale packages and methods of fabrication
US20020180022 *19 Jul 20025 Dec 2002Seiko Epson CorporationSemiconductor device
US2003016454017 May 20024 Sep 2003Lee Teck KhengSemiconductor die packages with recessed interconnecting structures and methods for assembling the same
US2003016454317 May 20024 Sep 2003Teck Kheng LeeInterposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US2003016454817 May 20024 Sep 2003Lee Teck KhengFlip chip packaging using recessed interposer terminals
US2003016455117 May 20024 Sep 2003Lee Teck KhengMethod and apparatus for flip-chip packaging providing testing capability
US2003016631217 May 20024 Sep 2003Lee Teck KhengMethods for assembly and packaging of flip chip configured dice with interposer
US20040000707 *9 May 20031 Jan 2004Staktek Group, L.P.Modularized die stacking system and method
US2004003617020 Aug 200226 Feb 2004Lee Teck KhengDouble bumping of flexible substrate for first and second level interconnects
US20040124527 *31 Dec 20021 Jul 2004Chia-Pin ChiuFolded BGA package design with shortened communication paths and more electrical routing flexibility
US2004022940222 Jun 200418 Nov 2004Staktek Group, L.P.Low profile chip scale stacking system and method
US20050051880 *27 Feb 200410 Mar 2005Lee Teck KhengTape substrates with mold gate support structures that are coplanar with conductive traces thereof and associated methods
US20050098873 *17 Dec 200412 May 2005Staktek Group L.P.Stacked module systems and methods
US20050110128 *19 Nov 200426 May 2005Eun-Chul AhnHighly reliable stack type semiconductor package
US20050189627 *25 Feb 20051 Sep 2005Fujio ItoMethod of surface mounting a semiconductor device
US200502801354 Aug 200522 Dec 2005Staktek Group L.P.Stacking system and method
US20060138628 *23 Jun 200529 Jun 2006Domintech Co., Ltd.Stack chip package
US20080054437 *6 Sep 20076 Mar 2008Samsung Electronics Co., Ltd.Pop package and method of fabricating the same
USRE40061 *16 Jan 200312 Feb 2008Micron Technology, Inc.Multi-chip stacked devices
JP2001077294A Title not available
WO1999065282A110 Jun 199916 Dec 1999Irvine Sensors CorpIc stack utilizing flexible circuits with bga contacts
Non-Patent Citations
Reference
1Isaak, H., et al., "Development of flex stackable carriers," Electronic Components and Technology Conference, 2000 Proceedings, Las Vegas, NV, pp. 378-384, May 21, 2000-May 24, 2000.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8304876 *12 Aug 20096 Nov 2012Samsung Electronics Co., Ltd.Semiconductor package and method for manufacturing the same
US8441112 *1 Oct 201014 May 2013Headway Technologies, Inc.Method of manufacturing layered chip package
US8446018 *7 Mar 201121 May 2013Samsung Electronics Co., Ltd.Package on package
US20100038765 *12 Aug 200918 Feb 2010Samsung Electronics Co., Ltd.Semiconductor package and method for manufacturing the same
US20110215471 *7 Mar 20118 Sep 2011Samsung Electronics Co., Ltd.Package On Package
US20120080782 *1 Oct 20105 Apr 2012Sae Magnetics (H.K.) Ltd.Method of manufacturing layered chip package
US20130099392 *25 Apr 201225 Apr 2013Vertical Circuits, Inc.Support mounted electrically interconnected die assembly
Legal Events
DateCodeEventDescription
26 Apr 2011CCCertificate of correction
11 Sep 2006ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CORISIS, DAVID J.;CHONG, CHIN HUI;LEE, CHOON KUAN;REEL/FRAME:018281/0547;SIGNING DATES FROM 20060906 TO 20060907
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CORISIS, DAVID J.;CHONG, CHIN HUI;LEE, CHOON KUAN;SIGNING DATES FROM 20060906 TO 20060907;REEL/FRAME:018281/0547