US7767587B2 - Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers - Google Patents
Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers Download PDFInfo
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- US7767587B2 US7767587B2 US12/034,692 US3469208A US7767587B2 US 7767587 B2 US7767587 B2 US 7767587B2 US 3469208 A US3469208 A US 3469208A US 7767587 B2 US7767587 B2 US 7767587B2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
patterning said structure to provide an opening that extends through the structure, said patterning comprising lithography and etching, wherein said etching is performed in a fluorocarbon-based plasma having a fluorine to carbon ratio and at an ion current that selectively etches the non-porous organosilicate glass interlevel dielectrics relative to the porous organosilicate glass.
patterning said structure to provide an opening in the structure, said patterning comprising lithography and etching, wherein said etching is performed in a fluorocarbon-based plasma having a fluorine to carbon ratio and at an ion current that selectively etches the non-porous organosilicate glass hardmask relative to the porous organosilicate glass interlevel dielectric.
- 7-oxabicyclo[4.1.0]heptane or cyclohexene oxide (bp=129° C. at 760 mm Hg);
- 9-oxabicyclo[6.1.0]nonane or cyclooctene oxide (bp=55° C. at 5 mm Hg); and
- 7-oxabicyclo[2.2.1]heptane or 1,4-epoxycyclohexane (bp=119° C. at 713 mm Hg). One highly preferred fused ring species that is employed in the first embodiment of the present invention is cyclopentene oxide (CPO).
SiCOH(s)+CFx(g), F(g) SiF(g), CO(g), COF(g), HF(g)(x=1-3)
+N(g), O(g) CN(g), CO(g), OH(g)
TABLE I | ||
Plasma Parameter | Tolerance Range | Function |
27 MHz Power (W) | 200 to 400 | Gas-Phase FC Ratio/ |
2 MHz Power (W) | <100 | Ion Current |
Pressure (mT) | 70 to 140 | Gas-Phase FC Ratio/Ion Current |
C4F8 Flow (sccm) | 4 to 10 | Gas-Phase FC Ratio |
CF4 Flow (sccm) | 7 to 20 | Gas-Phase |
Ar | ||
50 to 200 | Ion Current | |
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/034,692 US7767587B2 (en) | 2004-05-14 | 2008-02-21 | Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/845,718 US7504727B2 (en) | 2004-05-14 | 2004-05-14 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials |
US12/034,692 US7767587B2 (en) | 2004-05-14 | 2008-02-21 | Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers |
Related Parent Applications (1)
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US10/845,718 Division US7504727B2 (en) | 2004-05-14 | 2004-05-14 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials |
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US20080146037A1 US20080146037A1 (en) | 2008-06-19 |
US7767587B2 true US7767587B2 (en) | 2010-08-03 |
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US10/845,718 Active US7504727B2 (en) | 2004-05-14 | 2004-05-14 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials |
US12/034,692 Expired - Fee Related US7767587B2 (en) | 2004-05-14 | 2008-02-21 | Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers |
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US10/845,718 Active US7504727B2 (en) | 2004-05-14 | 2004-05-14 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials |
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Cited By (2)
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US8916475B1 (en) * | 2013-11-01 | 2014-12-23 | United Microelectronics Corp. | Patterning method |
US9058983B2 (en) | 2013-06-17 | 2015-06-16 | International Business Machines Corporation | In-situ hardmask generation |
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US20060183055A1 (en) * | 2005-02-15 | 2006-08-17 | O'neill Mark L | Method for defining a feature on a substrate |
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US20070232046A1 (en) * | 2006-03-31 | 2007-10-04 | Koji Miyata | Damascene interconnection having porous low K layer with improved mechanical properties |
US7704680B2 (en) * | 2006-06-08 | 2010-04-27 | Advanced Micro Devices, Inc. | Double exposure technology using high etching selectivity |
US7772663B2 (en) * | 2007-02-21 | 2010-08-10 | International Business Machines Corporation | Method and apparatus for bitline and contact via integration in magnetic random access memory arrays |
US20080230907A1 (en) * | 2007-03-22 | 2008-09-25 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system with carbon enhancement |
US9719169B2 (en) | 2010-12-20 | 2017-08-01 | Novellus Systems, Inc. | System and apparatus for flowable deposition in semiconductor fabrication |
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US9370907B2 (en) * | 2014-03-20 | 2016-06-21 | Seagate Technology Llc | Apparatuses and methods utilizing etch stop layers |
US10049921B2 (en) * | 2014-08-20 | 2018-08-14 | Lam Research Corporation | Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor |
US9502255B2 (en) | 2014-10-17 | 2016-11-22 | Lam Research Corporation | Low-k damage repair and pore sealing agents with photosensitive end groups |
US9916977B2 (en) | 2015-11-16 | 2018-03-13 | Lam Research Corporation | Low k dielectric deposition via UV driven photopolymerization |
US10388546B2 (en) | 2015-11-16 | 2019-08-20 | Lam Research Corporation | Apparatus for UV flowable dielectric |
FR3100377A1 (en) * | 2019-08-30 | 2021-03-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Contact on germanium |
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US9058983B2 (en) | 2013-06-17 | 2015-06-16 | International Business Machines Corporation | In-situ hardmask generation |
US8916475B1 (en) * | 2013-11-01 | 2014-12-23 | United Microelectronics Corp. | Patterning method |
Also Published As
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US7504727B2 (en) | 2009-03-17 |
US20050258542A1 (en) | 2005-11-24 |
US20080146037A1 (en) | 2008-06-19 |
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